Added new semaphore API chSemSetCounterI().

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2569 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2011-01-02 10:13:43 +00:00
parent 90aa3805a2
commit 89c12799e1
4 changed files with 40 additions and 13 deletions

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@ -51,6 +51,7 @@ extern "C" {
msg_t chSemWaitTimeoutS(Semaphore *sp, systime_t time);
void chSemSignal(Semaphore *sp);
void chSemSignalI(Semaphore *sp);
void chSemSetCounterI(Semaphore *sp, cnt_t n);
#if CH_USE_SEMSW
msg_t chSemSignalWait(Semaphore *sps, Semaphore *spw);
#endif

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@ -311,6 +311,38 @@ void chSemSignalI(Semaphore *sp) {
}
}
/**
* @brief Sets the semaphore counter to the specified value.
* @post After invoking this function all the threads waiting on the
* semaphore, if any, are released and the semaphore counter is set
* to the specified, non negative, value.
* @post This function does not reschedule so a call to a rescheduling
* function must be performed before unlocking the kernel. Note that
* interrupt handlers always reschedule on exit so an explicit
* reschedule must not be performed in ISRs.
*
* @param[in] sp pointer to a @p Semaphore structure
* @param[in] n the new value of the semaphore counter. The value must
* be non-negative.
*
* @iclass
*/
void chSemSetCounterI(Semaphore *sp, cnt_t n) {
cnt_t cnt;
chDbgCheck((sp != NULL) && (n >= 0), "chSemSetCounterI");
chDbgAssert(((sp->s_cnt >= 0) && isempty(&sp->s_queue)) ||
((sp->s_cnt < 0) && notempty(&sp->s_queue)),
"chSemSetCounterI(), #1",
"inconsistent semaphore");
cnt = sp->s_cnt;
sp->s_cnt = n;
while (++cnt <= 0)
chSchReadyI(lifo_remove(&sp->s_queue))->p_u.rdymsg = RDY_OK;
}
#if CH_USE_SEMSW
/**
* @brief Performs atomic signal and wait operations on two semaphores.

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@ -74,6 +74,7 @@
- NEW: Integrated the STM32 GCC, IAR and RVCT demos in a single demo with
multiple project files, the code is exactly the same.
- NEW: Added an USB clock configuration in the STM32 HAL driver (LD, MD, HD).
- NEW: New semaphore API chSemSetCounterI().
- CHANGE: Modified the ADC and CAN drivers to allow a NULL pointer for
the configuration structure if it is not required by the implementation.
- CHANGE: Modified the MMC_SPI driver to *require* a NULL as pointer to

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@ -62,18 +62,11 @@ X Support for not just Makefiles (Ride7, Crossworks etc).
? Make thread functions return void.
- Introduce a "THREAD" function prefix in order to hide compiler-specific
optimizations for thread functions.
- Move I/O queues out of the kernel into an new "oslib" category.
- Add an I/O buffers mechanism to the oslib category.
- Move MemStreams to the oslib category.
- Move iochannels and file interfaces to the oslib category.
? Evaluate moving mailboxes to the oslib category.
- Make the oslib category appear in the general documentation and the various
kernel reference manuals.
- IAR port for Cortex-Mx, add demos for all the supported families.
- Keil port for Cortex-Mx, add demos for all the supported families.
- Add an USB abstract device driver class.
- USB driver implementation for STM32F103/STM32F102.
- Add a Serial over USB generic device driver implementing a USB Communication
X IAR port for Cortex-Mx, add demos for all the supported families.
X Keil port for Cortex-Mx, add demos for all the supported families.
X Add an USB abstract device driver class.
X USB driver implementation for STM32F103/STM32F102.
X Add a Serial over USB generic device driver implementing a USB Communication
Device Class and offering a Serial-like interface to the applications.
X Except for the above, bug fixing only until the 2.2.0 release.
@ -87,7 +80,7 @@ X I2C device driver class support and at least one implementation.
- Serial over UART complex driver driver, evaluate from the performance
results if to make obsolete the current dedicated Serial driver.
X Shared DMA channels support in the STM32/STM8L HALs.
X New device driver models: Clock, Systick, RTC, WDG, DAC, USB, Power Monitor.
X New device driver models: Clock, Systick, RTC, WDG, DAC, Power Monitor.
- MAC driver for STM32F107 (hardware missing).
- Device drivers for STM8/STM8L (ADC, PWM, bring them on par with STM32).
- Batch testing of the ARM7/ARMCMx port using OpenOCD, with reports.