andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

STM32WLxx port: fixed RTC driver copilation problems, added IPCC, RTC attributes to registry file, fixed some naming mistakes in stm32_isr.c and stm32_rcc.h 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14264 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-04-23 07:14:45 +00:00
parent b9c0908faf
commit 89e00b005c
6 changed files with 48 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h
View File

@ -46,7 +46,8 @@
/* Handling differences in ST headers.*/
#if !defined(STM32H7XX) && !defined(STM32L4XX) && !defined(STM32L4XXP) && \
!defined(STM32G0XX) && !defined(STM32G4XX) && !defined(STM32WBXX)
!defined(STM32G0XX) && !defined(STM32G4XX) && !defined(STM32WBXX) && \
!defined(STM32WLXX)
#define EMR1 EMR
#define IMR1 IMR
#define PR1 PR

4
os/hal/ports/STM32/LLD/RTCv3/hal_rtc_lld.c
View File

@ -577,8 +577,10 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
if (alarm == 0) {
if (alarmspec != NULL) {
rtcp->rtc->CR &= ~RTC_CR_ALRAE;
#if defined(RTC_ICSR_ALRAWF)
while (!(rtcp->rtc->ICSR & RTC_ICSR_ALRAWF))
;
#endif
rtcp->rtc->ALRMAR = alarmspec->alrmr;
rtcp->rtc->CR |= RTC_CR_ALRAE;
rtcp->rtc->CR |= RTC_CR_ALRAIE;
@ -592,8 +594,10 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
else {
if (alarmspec != NULL) {
rtcp->rtc->CR &= ~RTC_CR_ALRBE;
#if defined(RTC_ICSR_ALRBWF)
while (!(rtcp->rtc->ICSR & RTC_ICSR_ALRBWF))
;
#endif
rtcp->rtc->ALRMBR = alarmspec->alrmr;
rtcp->rtc->CR |= RTC_CR_ALRBE;
rtcp->rtc->CR |= RTC_CR_ALRBIE;

4
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -82,6 +82,8 @@ static void hal_lld_backup_domain_init(void) {
#endif
#if HAL_USE_RTC
/* RTC APB bus clock enable */
RCC->APB1ENR1 |= RCC_APB1ENR1_RTCAPBEN;
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
@ -278,7 +280,7 @@ void stm32_clock_init(void) {
uint32_t ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_LPTIM3SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C3SEL |
STM32_I2C2SEL | STM32_I2C1SEL | STM32_LPUART1SEL |
STM32_SPI2SEL | STM32_USART2SEL | STM32_USART1SEL;
STM32_SPI2SEL | STM32_USART2SEL | STM32_USART1SEL;
RCC->CCIPR = ccipr;
}

6
os/hal/ports/STM32/STM32WLxx/stm32_isr.c
View File

@ -15,10 +15,10 @@
*/
/**
* @file STM32L4xx/stm32_isr.c
* @brief STM32L4xx ISR handler code.
* @file STM32WLxx/stm32_isr.c
* @brief STM32WLxx ISR handler code.
*
* @addtogroup STM32L4xx_ISR
* @addtogroup STM32WLxx_ISR
* @{
*/

10
os/hal/ports/STM32/STM32WLxx/stm32_rcc.h
View File

@ -363,14 +363,14 @@
*
* @api
*/
#define rccEnableADC1(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADCEN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
*
* @api
*/
#define rccDisableADC1() rccDisableAHB2(RCC_APB2RSTR_ADCRST)
#define rccDisableADC1() rccDisableAPB2(RCC_APB2RSTR_ADCRST)
/**
* @brief Resets the ADC1 peripheral.
@ -621,14 +621,14 @@
#define rccEnableSPIR(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
* @brief Disables the SPIR peripheral clock.
*
* @api
*/
#define rccDisableSPIR() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN)
/**
* @brief Resets the SPI2 peripheral.
* @brief Resets the SPIR peripheral.
*
* @api
*/
@ -799,7 +799,7 @@
#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
/**
* @brief Resets the USART1 peripheral.
* @brief Resets the LPUART1 peripheral.
*
* @api
*/

33
os/hal/ports/STM32/STM32WLxx/stm32_registry.h
View File

@ -129,6 +129,15 @@
#define STM32_HAS_I2C2 FALSE
#define STM32_HAS_I2C4 FALSE
/* IPCC attributes.*/
#if defined(STM32WL55xx) || defined(STM32WL54xx) || defined(__DOXYGEN__)
#define STM32_HAS_IPCC TRUE
#define STM32_IPCC_RX_CHANNELS 6
#define STM32_IPCC_TX_CHANNELS 6
#else
#define STM32_HAS_IPCC FALSE
#endif /* defined(STM32WL55xx) || defined(STM32WL54xx) */
/* IWDG attributes.*/
#define STM32_HAS_IWDG TRUE
#define STM32_IWDG_IS_WINDOWED TRUE
@ -167,7 +176,7 @@
#define STM32_RTC_STORAGE_SIZE 32
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
#define STM32_RTC_WKUP_HANDLER Vector4C
#define STM32_RTC_ALARM_HANDLER VectorE4
#define STM32_RTC_ALARM_HANDLER VectorE8
#define STM32_RTC_TAMP_STAMP_NUMBER 2
#define STM32_RTC_WKUP_NUMBER 3
#define STM32_RTC_ALARM_NUMBER 42
@ -177,9 +186,29 @@
#define STM32_RTC_IRQ_ENABLE() do { \
nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
} while (false)
/* Enabling RTC-related EXTI lines.*/
#define STM32_RTC_ENABLE_ALL_EXTI() do { \
extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
} while (false)
/* Clearing EXTI interrupts. */
#define STM32_RTC_CLEAR_ALL_EXTI() do { \
} while (false)
/* Masks used to preserve state of RTC and TAMP register reserved bits. */
#define STM32_RTC_CR_MASK 0xE7FFFF7F
#define STM32_RTC_PRER_MASK 0x007F7FFF
#define STM32_TAMP_CR1_MASK 0xFFFF0007
#define STM32_TAMP_CR2_MASK 0x07070007
#define STM32_TAMP_FLTCR_MASK 0x000000FF
#define STM32_TAMP_IER_MASK 0x003C0003
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE
#define STM32_HAS_SDMMC2 FALSE