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Problem with L496 board. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13180 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-11-10 16:00:05 +00:00
parent 56f83f861c
commit 89e02bd7a4
3 changed files with 323 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
os/hal/boards/ST_NUCLEO144_L496ZG/board.c
View File

@ -45,6 +45,8 @@ typedef struct {
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
uint32_t ascr;
uint32_t lockr;
} gpio_setup_t;
/**
@ -92,47 +94,58 @@ typedef struct {
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
VAL_GPIOA_LOCKR},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
VAL_GPIOB_LOCKR},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
VAL_GPIOC_LOCKR},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
VAL_GPIOD_LOCKR},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
VAL_GPIOE_LOCKR},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
VAL_GPIOF_LOCKR},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
VAL_GPIOG_LOCKR},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
VAL_GPIOH_LOCKR},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
VAL_GPIOI_LOCKR},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
VAL_GPIOJ_LOCKR},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
VAL_GPIOK_LOCKR}
#endif
};
@ -143,20 +156,22 @@ static const gpio_config_t gpio_default_config = {
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->ASCR = config->ascr;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
gpiop->LOCKR = config->lockr;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
rccResetAHB2(STM32_GPIO_EN_MASK);
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA

294
os/hal/boards/ST_NUCLEO144_L496ZG/board.h
View File

@ -45,6 +45,8 @@
#define STM32_LSECLK 0U
#endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 0U
#endif
@ -279,6 +281,10 @@
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
#define PIN_ASCR_DISABLED(n) (0U << (n))
#define PIN_ASCR_ENABLED(n) (1U << (n))
#define PIN_LOCKR_DISABLED(n) (0U << (n))
#define PIN_LOCKR_ENABLED(n) (1U << (n))
/*
* GPIOA setup:
@ -396,6 +402,38 @@
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
PIN_AFIO_AF(GPIOA_PIN15, 0U))
#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_PIN0) | \
PIN_ASCR_DISABLED(GPIOA_PIN1) | \
PIN_ASCR_DISABLED(GPIOA_PIN2) | \
PIN_ASCR_DISABLED(GPIOA_PIN3) | \
PIN_ASCR_DISABLED(GPIOA_PIN4) | \
PIN_ASCR_DISABLED(GPIOA_PIN5) | \
PIN_ASCR_DISABLED(GPIOA_PIN6) | \
PIN_ASCR_DISABLED(GPIOA_PIN7) | \
PIN_ASCR_DISABLED(GPIOA_USB_SOF) | \
PIN_ASCR_DISABLED(GPIOA_USB_VBUS) | \
PIN_ASCR_DISABLED(GPIOA_USB_ID) | \
PIN_ASCR_DISABLED(GPIOA_USB_DM) | \
PIN_ASCR_DISABLED(GPIOA_USB_DP) | \
PIN_ASCR_DISABLED(GPIOA_SWDIO) | \
PIN_ASCR_DISABLED(GPIOA_SWCLK) | \
PIN_ASCR_DISABLED(GPIOA_PIN15))
#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_PIN0) | \
PIN_LOCKR_DISABLED(GPIOA_PIN1) | \
PIN_LOCKR_DISABLED(GPIOA_PIN2) | \
PIN_LOCKR_DISABLED(GPIOA_PIN3) | \
PIN_LOCKR_DISABLED(GPIOA_PIN4) | \
PIN_LOCKR_DISABLED(GPIOA_PIN5) | \
PIN_LOCKR_DISABLED(GPIOA_PIN6) | \
PIN_LOCKR_DISABLED(GPIOA_PIN7) | \
PIN_LOCKR_DISABLED(GPIOA_USB_SOF) | \
PIN_LOCKR_DISABLED(GPIOA_USB_VBUS) | \
PIN_LOCKR_DISABLED(GPIOA_USB_ID) | \
PIN_LOCKR_DISABLED(GPIOA_USB_DM) | \
PIN_LOCKR_DISABLED(GPIOA_USB_DP) | \
PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \
PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \
PIN_LOCKR_DISABLED(GPIOA_PIN15))
/*
* GPIOB setup:
@ -513,6 +551,38 @@
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_LED3, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_PIN0) | \
PIN_ASCR_DISABLED(GPIOB_PIN1) | \
PIN_ASCR_DISABLED(GPIOB_PIN2) | \
PIN_ASCR_DISABLED(GPIOB_SWO) | \
PIN_ASCR_DISABLED(GPIOB_PIN4) | \
PIN_ASCR_DISABLED(GPIOB_PIN5) | \
PIN_ASCR_DISABLED(GPIOB_PIN6) | \
PIN_ASCR_DISABLED(GPIOB_LED2) | \
PIN_ASCR_DISABLED(GPIOB_PIN8) | \
PIN_ASCR_DISABLED(GPIOB_PIN9) | \
PIN_ASCR_DISABLED(GPIOB_PIN10) | \
PIN_ASCR_DISABLED(GPIOB_PIN11) | \
PIN_ASCR_DISABLED(GPIOB_PIN12) | \
PIN_ASCR_DISABLED(GPIOB_PIN13) | \
PIN_ASCR_DISABLED(GPIOB_LED3) | \
PIN_ASCR_DISABLED(GPIOB_PIN15))
#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_PIN0) | \
PIN_LOCKR_DISABLED(GPIOB_PIN1) | \
PIN_LOCKR_DISABLED(GPIOB_PIN2) | \
PIN_LOCKR_DISABLED(GPIOB_SWO) | \
PIN_LOCKR_DISABLED(GPIOB_PIN4) | \
PIN_LOCKR_DISABLED(GPIOB_PIN5) | \
PIN_LOCKR_DISABLED(GPIOB_PIN6) | \
PIN_LOCKR_DISABLED(GPIOB_LED2) | \
PIN_LOCKR_DISABLED(GPIOB_PIN8) | \
PIN_LOCKR_DISABLED(GPIOB_PIN9) | \
PIN_LOCKR_DISABLED(GPIOB_PIN10) | \
PIN_LOCKR_DISABLED(GPIOB_PIN11) | \
PIN_LOCKR_DISABLED(GPIOB_PIN12) | \
PIN_LOCKR_DISABLED(GPIOB_PIN13) | \
PIN_LOCKR_DISABLED(GPIOB_LED3) | \
PIN_LOCKR_DISABLED(GPIOB_PIN15))
/*
* GPIOC setup:
@ -630,6 +700,38 @@
PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
PIN_AFIO_AF(GPIOC_PIN14, 0U) | \
PIN_AFIO_AF(GPIOC_PIN15, 0U))
#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \
PIN_ASCR_DISABLED(GPIOC_PIN1) | \
PIN_ASCR_DISABLED(GPIOC_PIN2) | \
PIN_ASCR_DISABLED(GPIOC_PIN3) | \
PIN_ASCR_DISABLED(GPIOC_PIN4) | \
PIN_ASCR_DISABLED(GPIOC_PIN5) | \
PIN_ASCR_DISABLED(GPIOC_PIN6) | \
PIN_ASCR_DISABLED(GPIOC_LED1) | \
PIN_ASCR_DISABLED(GPIOC_PIN8) | \
PIN_ASCR_DISABLED(GPIOC_PIN9) | \
PIN_ASCR_DISABLED(GPIOC_PIN10) | \
PIN_ASCR_DISABLED(GPIOC_PIN11) | \
PIN_ASCR_DISABLED(GPIOC_PIN12) | \
PIN_ASCR_DISABLED(GPIOC_BUTTON) | \
PIN_ASCR_DISABLED(GPIOC_PIN14) | \
PIN_ASCR_DISABLED(GPIOC_PIN15))
#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \
PIN_LOCKR_DISABLED(GPIOC_PIN1) | \
PIN_LOCKR_DISABLED(GPIOC_PIN2) | \
PIN_LOCKR_DISABLED(GPIOC_PIN3) | \
PIN_LOCKR_DISABLED(GPIOC_PIN4) | \
PIN_LOCKR_DISABLED(GPIOC_PIN5) | \
PIN_LOCKR_DISABLED(GPIOC_PIN6) | \
PIN_LOCKR_DISABLED(GPIOC_LED1) | \
PIN_LOCKR_DISABLED(GPIOC_PIN8) | \
PIN_LOCKR_DISABLED(GPIOC_PIN9) | \
PIN_LOCKR_DISABLED(GPIOC_PIN10) | \
PIN_LOCKR_DISABLED(GPIOC_PIN11) | \
PIN_LOCKR_DISABLED(GPIOC_PIN12) | \
PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \
PIN_LOCKR_DISABLED(GPIOC_PIN14) | \
PIN_LOCKR_DISABLED(GPIOC_PIN15))
/*
* GPIOD setup:
@ -747,6 +849,38 @@
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
PIN_AFIO_AF(GPIOD_PIN15, 0U))
#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \
PIN_ASCR_DISABLED(GPIOD_PIN1) | \
PIN_ASCR_DISABLED(GPIOD_PIN2) | \
PIN_ASCR_DISABLED(GPIOD_PIN3) | \
PIN_ASCR_DISABLED(GPIOD_PIN4) | \
PIN_ASCR_DISABLED(GPIOD_PIN5) | \
PIN_ASCR_DISABLED(GPIOD_PIN6) | \
PIN_ASCR_DISABLED(GPIOD_PIN7) | \
PIN_ASCR_DISABLED(GPIOD_PIN8) | \
PIN_ASCR_DISABLED(GPIOD_PIN9) | \
PIN_ASCR_DISABLED(GPIOD_PIN10) | \
PIN_ASCR_DISABLED(GPIOD_PIN11) | \
PIN_ASCR_DISABLED(GPIOD_PIN12) | \
PIN_ASCR_DISABLED(GPIOD_PIN13) | \
PIN_ASCR_DISABLED(GPIOD_PIN14) | \
PIN_ASCR_DISABLED(GPIOD_PIN15))
#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \
PIN_LOCKR_DISABLED(GPIOD_PIN1) | \
PIN_LOCKR_DISABLED(GPIOD_PIN2) | \
PIN_LOCKR_DISABLED(GPIOD_PIN3) | \
PIN_LOCKR_DISABLED(GPIOD_PIN4) | \
PIN_LOCKR_DISABLED(GPIOD_PIN5) | \
PIN_LOCKR_DISABLED(GPIOD_PIN6) | \
PIN_LOCKR_DISABLED(GPIOD_PIN7) | \
PIN_LOCKR_DISABLED(GPIOD_PIN8) | \
PIN_LOCKR_DISABLED(GPIOD_PIN9) | \
PIN_LOCKR_DISABLED(GPIOD_PIN10) | \
PIN_LOCKR_DISABLED(GPIOD_PIN11) | \
PIN_LOCKR_DISABLED(GPIOD_PIN12) | \
PIN_LOCKR_DISABLED(GPIOD_PIN13) | \
PIN_LOCKR_DISABLED(GPIOD_PIN14) | \
PIN_LOCKR_DISABLED(GPIOD_PIN15))
/*
* GPIOE setup:
@ -864,6 +998,38 @@
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
PIN_AFIO_AF(GPIOE_PIN15, 0U))
#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \
PIN_ASCR_DISABLED(GPIOE_PIN1) | \
PIN_ASCR_DISABLED(GPIOE_PIN2) | \
PIN_ASCR_DISABLED(GPIOE_PIN3) | \
PIN_ASCR_DISABLED(GPIOE_PIN4) | \
PIN_ASCR_DISABLED(GPIOE_PIN5) | \
PIN_ASCR_DISABLED(GPIOE_PIN6) | \
PIN_ASCR_DISABLED(GPIOE_PIN7) | \
PIN_ASCR_DISABLED(GPIOE_PIN8) | \
PIN_ASCR_DISABLED(GPIOE_PIN9) | \
PIN_ASCR_DISABLED(GPIOE_PIN10) | \
PIN_ASCR_DISABLED(GPIOE_PIN11) | \
PIN_ASCR_DISABLED(GPIOE_PIN12) | \
PIN_ASCR_DISABLED(GPIOE_PIN13) | \
PIN_ASCR_DISABLED(GPIOE_PIN14) | \
PIN_ASCR_DISABLED(GPIOE_PIN15))
#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \
PIN_LOCKR_DISABLED(GPIOE_PIN1) | \
PIN_LOCKR_DISABLED(GPIOE_PIN2) | \
PIN_LOCKR_DISABLED(GPIOE_PIN3) | \
PIN_LOCKR_DISABLED(GPIOE_PIN4) | \
PIN_LOCKR_DISABLED(GPIOE_PIN5) | \
PIN_LOCKR_DISABLED(GPIOE_PIN6) | \
PIN_LOCKR_DISABLED(GPIOE_PIN7) | \
PIN_LOCKR_DISABLED(GPIOE_PIN8) | \
PIN_LOCKR_DISABLED(GPIOE_PIN9) | \
PIN_LOCKR_DISABLED(GPIOE_PIN10) | \
PIN_LOCKR_DISABLED(GPIOE_PIN11) | \
PIN_LOCKR_DISABLED(GPIOE_PIN12) | \
PIN_LOCKR_DISABLED(GPIOE_PIN13) | \
PIN_LOCKR_DISABLED(GPIOE_PIN14) | \
PIN_LOCKR_DISABLED(GPIOE_PIN15))
/*
* GPIOF setup:
@ -981,6 +1147,38 @@
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
PIN_AFIO_AF(GPIOF_PIN15, 0U))
#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \
PIN_ASCR_DISABLED(GPIOF_PIN1) | \
PIN_ASCR_DISABLED(GPIOF_PIN2) | \
PIN_ASCR_DISABLED(GPIOF_PIN3) | \
PIN_ASCR_DISABLED(GPIOF_PIN4) | \
PIN_ASCR_DISABLED(GPIOF_PIN5) | \
PIN_ASCR_DISABLED(GPIOF_PIN6) | \
PIN_ASCR_DISABLED(GPIOF_PIN7) | \
PIN_ASCR_DISABLED(GPIOF_PIN8) | \
PIN_ASCR_DISABLED(GPIOF_PIN9) | \
PIN_ASCR_DISABLED(GPIOF_PIN10) | \
PIN_ASCR_DISABLED(GPIOF_PIN11) | \
PIN_ASCR_DISABLED(GPIOF_PIN12) | \
PIN_ASCR_DISABLED(GPIOF_PIN13) | \
PIN_ASCR_DISABLED(GPIOF_PIN14) | \
PIN_ASCR_DISABLED(GPIOF_PIN15))
#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \
PIN_LOCKR_DISABLED(GPIOF_PIN1) | \
PIN_LOCKR_DISABLED(GPIOF_PIN2) | \
PIN_LOCKR_DISABLED(GPIOF_PIN3) | \
PIN_LOCKR_DISABLED(GPIOF_PIN4) | \
PIN_LOCKR_DISABLED(GPIOF_PIN5) | \
PIN_LOCKR_DISABLED(GPIOF_PIN6) | \
PIN_LOCKR_DISABLED(GPIOF_PIN7) | \
PIN_LOCKR_DISABLED(GPIOF_PIN8) | \
PIN_LOCKR_DISABLED(GPIOF_PIN9) | \
PIN_LOCKR_DISABLED(GPIOF_PIN10) | \
PIN_LOCKR_DISABLED(GPIOF_PIN11) | \
PIN_LOCKR_DISABLED(GPIOF_PIN12) | \
PIN_LOCKR_DISABLED(GPIOF_PIN13) | \
PIN_LOCKR_DISABLED(GPIOF_PIN14) | \
PIN_LOCKR_DISABLED(GPIOF_PIN15))
/*
* GPIOG setup:
@ -1098,6 +1296,38 @@
PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
PIN_AFIO_AF(GPIOG_PIN15, 0U))
#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \
PIN_ASCR_DISABLED(GPIOG_PIN1) | \
PIN_ASCR_DISABLED(GPIOG_PIN2) | \
PIN_ASCR_DISABLED(GPIOG_PIN3) | \
PIN_ASCR_DISABLED(GPIOG_PIN4) | \
PIN_ASCR_DISABLED(GPIOG_USB_OVER_CURRENT) |\
PIN_ASCR_DISABLED(GPIOG_USB_POWER_SWITCH_ON) |\
PIN_ASCR_DISABLED(GPIOG_LPUART1_TX) | \
PIN_ASCR_DISABLED(GPIOG_LPUART1_RX) | \
PIN_ASCR_DISABLED(GPIOG_PIN9) | \
PIN_ASCR_DISABLED(GPIOG_PIN10) | \
PIN_ASCR_DISABLED(GPIOG_PIN11) | \
PIN_ASCR_DISABLED(GPIOG_PIN12) | \
PIN_ASCR_DISABLED(GPIOG_PIN13) | \
PIN_ASCR_DISABLED(GPIOG_PIN14) | \
PIN_ASCR_DISABLED(GPIOG_PIN15))
#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \
PIN_LOCKR_DISABLED(GPIOG_PIN1) | \
PIN_LOCKR_DISABLED(GPIOG_PIN2) | \
PIN_LOCKR_DISABLED(GPIOG_PIN3) | \
PIN_LOCKR_DISABLED(GPIOG_PIN4) | \
PIN_LOCKR_DISABLED(GPIOG_USB_OVER_CURRENT) |\
PIN_LOCKR_DISABLED(GPIOG_USB_POWER_SWITCH_ON) |\
PIN_LOCKR_DISABLED(GPIOG_LPUART1_TX) | \
PIN_LOCKR_DISABLED(GPIOG_LPUART1_RX) | \
PIN_LOCKR_DISABLED(GPIOG_PIN9) | \
PIN_LOCKR_DISABLED(GPIOG_PIN10) | \
PIN_LOCKR_DISABLED(GPIOG_PIN11) | \
PIN_LOCKR_DISABLED(GPIOG_PIN12) | \
PIN_LOCKR_DISABLED(GPIOG_PIN13) | \
PIN_LOCKR_DISABLED(GPIOG_PIN14) | \
PIN_LOCKR_DISABLED(GPIOG_PIN15))
/*
* GPIOH setup:
@ -1215,6 +1445,38 @@
PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
PIN_AFIO_AF(GPIOH_PIN15, 0U))
#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_PIN0) | \
PIN_ASCR_DISABLED(GPIOH_PIN1) | \
PIN_ASCR_DISABLED(GPIOH_PIN2) | \
PIN_ASCR_DISABLED(GPIOH_PIN3) | \
PIN_ASCR_DISABLED(GPIOH_PIN4) | \
PIN_ASCR_DISABLED(GPIOH_PIN5) | \
PIN_ASCR_DISABLED(GPIOH_PIN6) | \
PIN_ASCR_DISABLED(GPIOH_PIN7) | \
PIN_ASCR_DISABLED(GPIOH_PIN8) | \
PIN_ASCR_DISABLED(GPIOH_PIN9) | \
PIN_ASCR_DISABLED(GPIOH_PIN10) | \
PIN_ASCR_DISABLED(GPIOH_PIN11) | \
PIN_ASCR_DISABLED(GPIOH_PIN12) | \
PIN_ASCR_DISABLED(GPIOH_PIN13) | \
PIN_ASCR_DISABLED(GPIOH_PIN14) | \
PIN_ASCR_DISABLED(GPIOH_PIN15))
#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_PIN0) | \
PIN_LOCKR_DISABLED(GPIOH_PIN1) | \
PIN_LOCKR_DISABLED(GPIOH_PIN2) | \
PIN_LOCKR_DISABLED(GPIOH_PIN3) | \
PIN_LOCKR_DISABLED(GPIOH_PIN4) | \
PIN_LOCKR_DISABLED(GPIOH_PIN5) | \
PIN_LOCKR_DISABLED(GPIOH_PIN6) | \
PIN_LOCKR_DISABLED(GPIOH_PIN7) | \
PIN_LOCKR_DISABLED(GPIOH_PIN8) | \
PIN_LOCKR_DISABLED(GPIOH_PIN9) | \
PIN_LOCKR_DISABLED(GPIOH_PIN10) | \
PIN_LOCKR_DISABLED(GPIOH_PIN11) | \
PIN_LOCKR_DISABLED(GPIOH_PIN12) | \
PIN_LOCKR_DISABLED(GPIOH_PIN13) | \
PIN_LOCKR_DISABLED(GPIOH_PIN14) | \
PIN_LOCKR_DISABLED(GPIOH_PIN15))
/*
* GPIOI setup:
@ -1332,6 +1594,38 @@
PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
PIN_AFIO_AF(GPIOI_PIN15, 0U))
#define VAL_GPIOI_ASCR (PIN_ASCR_DISABLED(GPIOI_PIN0) | \
PIN_ASCR_DISABLED(GPIOI_PIN1) | \
PIN_ASCR_DISABLED(GPIOI_PIN2) | \
PIN_ASCR_DISABLED(GPIOI_PIN3) | \
PIN_ASCR_DISABLED(GPIOI_PIN4) | \
PIN_ASCR_DISABLED(GPIOI_PIN5) | \
PIN_ASCR_DISABLED(GPIOI_PIN6) | \
PIN_ASCR_DISABLED(GPIOI_PIN7) | \
PIN_ASCR_DISABLED(GPIOI_PIN8) | \
PIN_ASCR_DISABLED(GPIOI_PIN9) | \
PIN_ASCR_DISABLED(GPIOI_PIN10) | \
PIN_ASCR_DISABLED(GPIOI_PIN11) | \
PIN_ASCR_DISABLED(GPIOI_PIN12) | \
PIN_ASCR_DISABLED(GPIOI_PIN13) | \
PIN_ASCR_DISABLED(GPIOI_PIN14) | \
PIN_ASCR_DISABLED(GPIOI_PIN15))
#define VAL_GPIOI_LOCKR (PIN_LOCKR_DISABLED(GPIOI_PIN0) | \
PIN_LOCKR_DISABLED(GPIOI_PIN1) | \
PIN_LOCKR_DISABLED(GPIOI_PIN2) | \
PIN_LOCKR_DISABLED(GPIOI_PIN3) | \
PIN_LOCKR_DISABLED(GPIOI_PIN4) | \
PIN_LOCKR_DISABLED(GPIOI_PIN5) | \
PIN_LOCKR_DISABLED(GPIOI_PIN6) | \
PIN_LOCKR_DISABLED(GPIOI_PIN7) | \
PIN_LOCKR_DISABLED(GPIOI_PIN8) | \
PIN_LOCKR_DISABLED(GPIOI_PIN9) | \
PIN_LOCKR_DISABLED(GPIOI_PIN10) | \
PIN_LOCKR_DISABLED(GPIOI_PIN11) | \
PIN_LOCKR_DISABLED(GPIOI_PIN12) | \
PIN_LOCKR_DISABLED(GPIOI_PIN13) | \
PIN_LOCKR_DISABLED(GPIOI_PIN14) | \
PIN_LOCKR_DISABLED(GPIOI_PIN15))
/*===========================================================================*/
/* External declarations. */

2
os/hal/boards/ST_NUCLEO144_L496ZG/cfg/board.fmpp
View File

@ -1,4 +1,4 @@
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f4xx/templates
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l4xx/templates
outputRoot: ..
dataRoot: .