diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c index 7c09ed160..c0bf010f5 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c @@ -537,7 +537,6 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 rccEnableADC12(true); rccResetADC12(); - osalSysPolledDelayX(10); ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; rccDisableADC12(); #endif @@ -545,7 +544,6 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC1 rccEnableADC12(true); rccResetADC12(); - osalSysPolledDelayX(10); ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; rccDisableADC12(); #endif @@ -553,7 +551,6 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4 rccEnableADC34(true); rccResetADC34(); - osalSysPolledDelayX(10); ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; rccDisableADC34(); #endif @@ -562,7 +559,6 @@ void adc_lld_init(void) { #if defined(STM32L4XX) rccEnableADC123(true); rccResetADC123(); - osalSysPolledDelayX(10); #if defined(ADC1_2_COMMON) ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; #elif defined(ADC123_COMMON) diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h index 091f60882..94bc77955 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h @@ -62,6 +62,7 @@ */ #define rccEnableAPB1(mask, lp) { \ RCC->APB1ENR |= (mask); \ + (void)RCC->APB1ENR; \ } /** @@ -73,6 +74,7 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + (void)RCC->APB1ENR; \ } /** @@ -84,7 +86,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -98,6 +101,7 @@ */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ + (void)RCC->APB2ENR; \ } /** @@ -109,6 +113,7 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + (void)RCC->APB2ENR; \ } /** @@ -120,7 +125,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -134,6 +140,7 @@ */ #define rccEnableAHB(mask, lp) { \ RCC->AHBENR |= (mask); \ + (void)RCC->AHBENR; \ } /** @@ -145,6 +152,7 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ + (void)RCC->AHBENR; \ } /** @@ -156,7 +164,8 @@ */ #define rccResetAHB(mask) { \ RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h index 9ba874cd9..9578bf145 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h @@ -62,6 +62,7 @@ */ #define rccEnableAPB1(mask, lp) { \ RCC->APB1ENR |= (mask); \ + (void)RCC->APB1ENR; \ } /** @@ -74,6 +75,7 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + (void)RCC->APB1ENR; \ } /** @@ -85,7 +87,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -99,6 +102,7 @@ */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ + (void)RCC->APB2ENR; \ } /** @@ -111,6 +115,7 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + (void)RCC->APB2ENR; \ } /** @@ -122,7 +127,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -136,6 +142,7 @@ */ #define rccEnableAHB(mask, lp) { \ RCC->AHBENR |= (mask); \ + (void)RCC->AHBENR; \ } /** @@ -148,6 +155,7 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ + (void)RCC->AHBENR; \ } /** @@ -159,7 +167,8 @@ */ #define rccResetAHB(mask) { \ RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h index 6cf48250f..0b929d3cd 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h @@ -61,6 +61,7 @@ */ #define rccEnableAPB1(mask, lp) { \ RCC->APB1ENR |= (mask); \ + (void)RCC->APB1ENR; \ } /** @@ -72,6 +73,7 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + (void)RCC->APB1ENR; \ } /** @@ -83,7 +85,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -96,6 +99,7 @@ */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ + (void)RCC->APB2ENR; \ } /** @@ -107,6 +111,7 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + (void)RCC->APB2ENR; \ } /** @@ -118,7 +123,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -131,6 +137,7 @@ */ #define rccEnableAHB(mask, lp) { \ RCC->AHBENR |= (mask); \ + (void)RCC->AHBENR; \ } /** @@ -142,6 +149,7 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ + (void)RCC->AHBENR; \ } /** @@ -153,7 +161,8 @@ */ #define rccResetAHB(mask) { \ RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h index cf043bfa1..4db714d80 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h @@ -61,6 +61,7 @@ */ #define rccEnableAPB1(mask, lp) { \ RCC->APB1ENR |= (mask); \ + (void)RCC->APB1ENR; \ } /** @@ -72,6 +73,7 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + (void)RCC->APB1ENR; \ } /** @@ -83,7 +85,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -96,6 +99,7 @@ */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ + (void)RCC->APB2ENR; \ } /** @@ -107,6 +111,7 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + (void)RCC->APB2ENR; \ } /** @@ -118,7 +123,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -131,6 +137,7 @@ */ #define rccEnableAHB(mask, lp) { \ RCC->AHBENR |= (mask); \ + (void)RCC->AHBENR; \ } /** @@ -142,6 +149,7 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ + (void)RCC->AHBENR; \ } /** @@ -153,7 +161,8 @@ */ #define rccResetAHB(mask) { \ RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index e55caf2f6..e4eb67a2a 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -64,6 +64,7 @@ RCC->APB1LPENR |= (mask); \ else \ RCC->APB1LPENR &= ~(mask); \ + (void)RCC->APB1LPENR; \ } /** @@ -75,6 +76,8 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + RCC->APB1LPENR &= ~(mask); \ + (void)RCC->APB1LPENR; \ } /** @@ -86,7 +89,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -102,6 +106,7 @@ RCC->APB2LPENR |= (mask); \ else \ RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -113,6 +118,8 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -124,7 +131,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -141,6 +149,7 @@ RCC->AHB1LPENR |= (mask); \ else \ RCC->AHB1LPENR &= ~(mask); \ + (void)RCC->AHB1LPENR; \ } /** @@ -152,6 +161,8 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ + RCC->AHB1LPENR &= ~(mask); \ + (void)RCC->AHB1LPENR; \ } /** @@ -163,7 +174,8 @@ */ #define rccResetAHB1(mask) { \ RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR = 0; \ + RCC->AHB1RSTR &= ~(mask); \ + (void)RCC->AHB1RSTR; \ } /** @@ -180,6 +192,7 @@ RCC->AHB2LPENR |= (mask); \ else \ RCC->AHB2LPENR &= ~(mask); \ + (void)RCC->AHB2LPENR; \ } /** @@ -191,6 +204,8 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ + RCC->AHB2LPENR &= ~(mask); \ + (void)RCC->AHB2LPENR; \ } /** @@ -202,7 +217,8 @@ */ #define rccResetAHB2(mask) { \ RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR = 0; \ + RCC->AHB2RSTR &= ~(mask); \ + (void)RCC->AHB2RSTR; \ } /** @@ -219,6 +235,7 @@ RCC->AHB3LPENR |= (mask); \ else \ RCC->AHB3LPENR &= ~(mask); \ + (void)RCC->AHB3LPENR; \ } /** @@ -230,6 +247,8 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ + RCC->AHB3LPENR &= ~(mask); \ + (void)RCC->AHB3LPENR; \ } /** @@ -241,7 +260,8 @@ */ #define rccResetAHB3(mask) { \ RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR = 0; \ + RCC->AHB3RSTR &= ~(mask); \ + (void)RCC->AHB3RSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 6b110b146..68fc7f18b 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -64,6 +64,7 @@ RCC->APB1LPENR |= (mask); \ else \ RCC->APB1LPENR &= ~(mask); \ + (void)RCC->APB1LPENR; \ } /** @@ -75,6 +76,8 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + RCC->APB1LPENR &= ~(mask); \ + (void)RCC->APB1LPENR; \ } /** @@ -86,7 +89,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -103,6 +107,7 @@ RCC->APB2LPENR |= (mask); \ else \ RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -114,6 +119,8 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -125,7 +132,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -142,6 +150,7 @@ RCC->AHB1LPENR |= (mask); \ else \ RCC->AHB1LPENR &= ~(mask); \ + (void)RCC->AHB1LPENR; \ } /** @@ -153,6 +162,8 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ + RCC->AHB1LPENR &= ~(mask); \ + (void)RCC->AHB1LPENR; \ } /** @@ -164,7 +175,8 @@ */ #define rccResetAHB1(mask) { \ RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR = 0; \ + RCC->AHB1RSTR &= ~(mask); \ + (void)RCC->AHB1RSTR; \ } /** @@ -181,6 +193,7 @@ RCC->AHB2LPENR |= (mask); \ else \ RCC->AHB2LPENR &= ~(mask); \ + (void)RCC->AHB2LPENR; \ } /** @@ -192,6 +205,8 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ + RCC->AHB2LPENR &= ~(mask); \ + (void)RCC->AHB2LPENR; \ } /** @@ -203,7 +218,8 @@ */ #define rccResetAHB2(mask) { \ RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR = 0; \ + RCC->AHB2RSTR &= ~(mask); \ + (void)RCC->AHB2RSTR; \ } /** @@ -220,6 +236,7 @@ RCC->AHB3LPENR |= (mask); \ else \ RCC->AHB3LPENR &= ~(mask); \ + (void)RCC->AHB3LPENR; \ } /** @@ -231,6 +248,8 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ + RCC->AHB3LPENR &= ~(mask); \ + (void)RCC->AHB3LPENR; \ } /** @@ -242,7 +261,8 @@ */ #define rccResetAHB3(mask) { \ RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR = 0; \ + RCC->AHB3RSTR &= ~(mask); \ + (void)RCC->AHB3RSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h index c607985c2..b81ad8f25 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h @@ -64,6 +64,7 @@ RCC->APB1LLPENR |= (mask); \ else \ RCC->APB1LLPENR &= ~(mask); \ + (void)RCC->APB1LLPENR; \ } /** @@ -80,6 +81,7 @@ RCC->APB1HLPENR |= (mask); \ else \ RCC->APB1HLPENR &= ~(mask); \ + (void)RCC->APB1HLPENR; \ } /** @@ -91,6 +93,8 @@ */ #define rccDisableAPB1L(mask) { \ RCC->APB1LENR &= ~(mask); \ + RCC->APB1LLPENR &= ~(mask); \ + (void)RCC->APB1LLPENR; \ } /** @@ -102,6 +106,8 @@ */ #define rccDisableAPB1H(mask) { \ RCC->APB1HENR &= ~(mask); \ + RCC->APB1HLPENR &= ~(mask); \ + (void)RCC->APB1HLPENR; \ } /** @@ -113,7 +119,8 @@ */ #define rccResetAPB1L(mask) { \ RCC->APB1LRSTR |= (mask); \ - RCC->APB1LRSTR = 0; \ + RCC->APB1LRSTR &= ~(mask); \ + (void)RCC->APB1LRSTR; \ } /** @@ -125,7 +132,8 @@ */ #define rccResetAPB1H(mask) { \ RCC->APB1HRSTR |= (mask); \ - RCC->APB1HRSTR = 0; \ + RCC->APB1HRSTR &= ~(mask); \ + (void)RCC->APB1HRSTR; \ } /** @@ -142,6 +150,7 @@ RCC->APB2LPENR |= (mask); \ else \ RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -153,6 +162,8 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -164,7 +175,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -181,6 +193,7 @@ RCC->APB3LPENR |= (mask); \ else \ RCC->APB3LPENR &= ~(mask); \ + (void)RCC->APB3LPENR; \ } /** @@ -192,6 +205,8 @@ */ #define rccDisableAPB3(mask) { \ RCC->APB3ENR &= ~(mask); \ + RCC->APB3LPENR &= ~(mask); \ + (void)RCC->APB3LPENR; \ } /** @@ -203,7 +218,8 @@ */ #define rccResetAPB3(mask) { \ RCC->APB3RSTR |= (mask); \ - RCC->APB3RSTR = 0; \ + RCC->APB3RSTR &= ~(mask); \ + (void)RCC->APB3RSTR; \ } /** @@ -220,6 +236,7 @@ RCC->APB4LPENR |= (mask); \ else \ RCC->APB4LPENR &= ~(mask); \ + (void)RCC->APB4LPENR; \ } /** @@ -231,6 +248,8 @@ */ #define rccDisableAPB4(mask) { \ RCC->APB4ENR &= ~(mask); \ + RCC->APB4LPENR &= ~(mask); \ + (void)RCC->APB4LPENR; \ } /** @@ -242,7 +261,8 @@ */ #define rccResetAPB4(mask) { \ RCC->APB4RSTR |= (mask); \ - RCC->APB4RSTR = 0; \ + RCC->APB4RSTR &= ~(mask); \ + (void)RCC->APB4RSTR; \ } /** @@ -259,6 +279,7 @@ RCC->AHB1LPENR |= (mask); \ else \ RCC->AHB1LPENR &= ~(mask); \ + (void)RCC->AHB1LPENR; \ } /** @@ -270,6 +291,8 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ + RCC->AHB1LPENR &= ~(mask); \ + (void)RCC->AHB1LPENR; \ } /** @@ -281,7 +304,8 @@ */ #define rccResetAHB1(mask) { \ RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR = 0; \ + RCC->AHB1RSTR &= ~(mask); \ + (void)RCC->AHB1RSTR; \ } /** @@ -298,6 +322,7 @@ RCC->AHB2LPENR |= (mask); \ else \ RCC->AHB2LPENR &= ~(mask); \ + (void)RCC->AHB2LPENR \ } /** @@ -309,6 +334,8 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ + RCC->AHB2LPENR &= ~(mask); \ + (void)RCC->AHB2LPENR; \ } /** @@ -320,7 +347,8 @@ */ #define rccResetAHB2(mask) { \ RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR = 0; \ + RCC->AHB2RSTR &= ~(mask); \ + (void)RCC->AHB2RSTR; \ } /** @@ -337,6 +365,7 @@ RCC->AHB3LPENR |= (mask); \ else \ RCC->AHB3LPENR &= ~(mask); \ + (void)RCC->AHB3LPENR; \ } /** @@ -348,6 +377,8 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ + RCC->AHB3LPENR &= ~(mask); \ + (void)RCC->AHB3LPENR; \ } /** @@ -359,7 +390,8 @@ */ #define rccResetAHB3(mask) { \ RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR = 0; \ + RCC->AHB3RSTR &= ~(mask); \ + (void)RCC->AHB3RSTR; \ } /** @@ -376,6 +408,7 @@ RCC->AHB4LPENR |= (mask); \ else \ RCC->AHB4LPENR &= ~(mask); \ + (void)RCC->AHB4LPENR; \ } /** @@ -387,6 +420,8 @@ */ #define rccDisableAHB4(mask) { \ RCC->AHB4ENR &= ~(mask); \ + RCC->AHB4LPENR &= ~(mask); \ + (void)RCC->AHB4LPENR; \ } /** @@ -398,7 +433,8 @@ */ #define rccResetAHB4(mask) { \ RCC->AHB4RSTR |= (mask); \ - RCC->AHB4RSTR = 0; \ + RCC->AHB4RSTR &= ~(mask); \ + (void)RCC->AHB4RSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 2e4462ae9..510ecb6dc 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -65,6 +65,7 @@ RCC->APB1SMENR |= (mask); \ else \ RCC->APB1SMENR &= ~(mask); \ + (void)RCC->APB1SMENR; \ } /** @@ -76,6 +77,8 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + RCC->APB1SMENR &= ~(mask); \ + (void)RCC->APB1SMENR; \ } /** @@ -87,7 +90,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -104,6 +108,7 @@ RCC->APB2SMENR |= (mask); \ else \ RCC->APB2SMENR &= ~(mask); \ + (void)RCC->APB2SMENR; \ } /** @@ -115,6 +120,8 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + RCC->APB2SMENR &= ~(mask); \ + (void)RCC->APB2SMENR; \ } /** @@ -126,7 +133,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -143,6 +151,7 @@ RCC->AHBSMENR |= (mask); \ else \ RCC->AHBSMENR &= ~(mask); \ + (void)RCC->AHBSMENR; \ } /** @@ -154,6 +163,8 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ + RCC->AHBSMENR &= ~(mask); \ + (void)RCC->AHBSMENR; \ } /** @@ -165,7 +176,8 @@ */ #define rccResetAHB(mask) { \ RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ } /** @@ -182,6 +194,7 @@ RCC->IOPSMENR |= (mask); \ else \ RCC->IOPSMENR &= ~(mask); \ + (void)RCC->IOPSMENR; \ } /** @@ -193,6 +206,8 @@ */ #define rccDisableIOP(mask) { \ RCC->IOPENR &= ~(mask); \ + RCC->IOPSMENR &= ~(mask); \ + (void)RCC->IOPSMENR; \ } /** @@ -204,7 +219,8 @@ */ #define rccResetIOP(mask) { \ RCC->IOPRSTR |= (mask); \ - RCC->IOPRSTR = 0; \ + RCC->IOPRSTR &= ~(mask); \ + (void)RCC->IOPRSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h index 1c52db0a8..11cbe332c 100644 --- a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h @@ -65,6 +65,7 @@ RCC->APB1LPENR |= (mask); \ else \ RCC->APB1LPENR &= ~(mask); \ + (void)RCC->APB1LPENR; \ } /** @@ -76,6 +77,8 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ + RCC->APB1LPENR &= ~(mask); \ + (void)RCC->APB1LPENR; \ } /** @@ -87,7 +90,8 @@ */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ - RCC->APB1RSTR = 0; \ + RCC->APB1RSTR &= ~(mask); \ + (void)RCC->APB1RSTR; \ } /** @@ -104,6 +108,7 @@ RCC->APB2LPENR |= (mask); \ else \ RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -115,6 +120,8 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + RCC->APB2LPENR &= ~(mask); \ + (void)RCC->APB2LPENR; \ } /** @@ -126,7 +133,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -143,6 +151,7 @@ RCC->AHBLPENR |= (mask); \ else \ RCC->AHBLPENR &= ~(mask); \ + (void)RCC->AHBLPENR; \ } /** @@ -154,6 +163,8 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ + RCC->AHBLPENR &= ~(mask); \ + (void)RCC->AHBLPENR; \ } /** @@ -165,7 +176,8 @@ */ #define rccResetAHB(mask) { \ RCC->AHBRSTR |= (mask); \ - RCC->AHBRSTR = 0; \ + RCC->AHBRSTR &= ~(mask); \ + (void)RCC->AHBRSTR; \ } /** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index e034f9ce8..2a8a7904d 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -64,6 +64,7 @@ RCC->APB1SMENR1 |= (mask); \ else \ RCC->APB1SMENR1 &= ~(mask); \ + (void)RCC->APB1SMENR1; \ } /** @@ -75,6 +76,8 @@ */ #define rccDisableAPB1R1(mask) { \ RCC->APB1ENR1 &= ~(mask); \ + RCC->APB1SMENR1 &= ~(mask); \ + (void)RCC->APB1SMENR1; \ } /** @@ -86,7 +89,8 @@ */ #define rccResetAPB1R1(mask) { \ RCC->APB1RSTR1 |= (mask); \ - RCC->APB1RSTR1 = 0; \ + RCC->APB1RSTR1 &= ~(mask); \ + (void)RCC->APB1RSTR1; \ } /** @@ -103,6 +107,7 @@ RCC->APB1SMENR2 |= (mask); \ else \ RCC->APB1SMENR2 &= ~(mask); \ + (void)RCC->APB1SMENR2; \ } /** @@ -114,6 +119,8 @@ */ #define rccDisableAPB1R2(mask) { \ RCC->APB1ENR2 &= ~(mask); \ + RCC->APB1SMENR2 &= ~(mask); \ + (void)RCC->APB1SMENR2; \ } /** @@ -125,7 +132,8 @@ */ #define rccResetAPB1R2(mask) { \ RCC->APB1RSTR2 |= (mask); \ - RCC->APB1RSTR2 = 0; \ + RCC->APB1RSTR2 &= ~(mask); \ + (void)RCC->APB1RSTR2; \ } /** @@ -142,6 +150,7 @@ RCC->APB2SMENR |= (mask); \ else \ RCC->APB2SMENR &= ~(mask); \ + (void)RCC->APB2SMENR; \ } /** @@ -153,6 +162,8 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ + RCC->APB2SMENR &= ~(mask); \ + (void)RCC->APB2SMENR; \ } /** @@ -164,7 +175,8 @@ */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ - RCC->APB2RSTR = 0; \ + RCC->APB2RSTR &= ~(mask); \ + (void)RCC->APB2RSTR; \ } /** @@ -181,6 +193,7 @@ RCC->AHB1SMENR |= (mask); \ else \ RCC->AHB1SMENR &= ~(mask); \ + (void)RCC->AHB1SMENR; \ } /** @@ -192,6 +205,8 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ + RCC->AHB1SMENR &= ~(mask); \ + (void)RCC->AHB1SMENR; \ } /** @@ -203,7 +218,8 @@ */ #define rccResetAHB1(mask) { \ RCC->AHB1RSTR |= (mask); \ - RCC->AHB1RSTR = 0; \ + RCC->AHB1RSTR &= ~(mask); \ + (void)RCC->AHB1RSTR; \ } /** @@ -220,6 +236,7 @@ RCC->AHB2SMENR |= (mask); \ else \ RCC->AHB2SMENR &= ~(mask); \ + (void)RCC->AHB2SMENR; \ } /** @@ -231,6 +248,8 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ + RCC->AHB2SMENR &= ~(mask); \ + (void)RCC->AHB2SMENR; \ } /** @@ -242,7 +261,8 @@ */ #define rccResetAHB2(mask) { \ RCC->AHB2RSTR |= (mask); \ - RCC->AHB2RSTR = 0; \ + RCC->AHB2RSTR &= ~(mask); \ + (void)RCC->AHB2RSTR; \ } /** @@ -259,6 +279,7 @@ RCC->AHB3SMENR |= (mask); \ else \ RCC->AHB3SMENR &= ~(mask); \ + (void)RCC->AHB3SMENR; \ } /** @@ -270,6 +291,8 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ + RCC->AHB3SMENR &= ~(mask); \ + (void)RCC->AHB3SMENR; \ } /** @@ -281,7 +304,8 @@ */ #define rccResetAHB3(mask) { \ RCC->AHB3RSTR |= (mask); \ - RCC->AHB3RSTR = 0; \ + RCC->AHB3RSTR &= ~(mask); \ + (void)RCC->AHB3RSTR; \ } /** @} */