From 8a41cbbfb4bc6891988b77fc3db56798a53885a2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 13 Oct 2012 09:23:58 +0000
Subject: [PATCH] Fixed bug 3575297.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4749 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F2xx/adc_lld.c | 6 ++++--
 os/hal/platforms/STM32F4xx/adc_lld.c | 6 ++++--
 readme.txt                           | 1 +
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/os/hal/platforms/STM32F2xx/adc_lld.c b/os/hal/platforms/STM32F2xx/adc_lld.c
index 016b12c52..1b566c256 100644
--- a/os/hal/platforms/STM32F2xx/adc_lld.c
+++ b/os/hal/platforms/STM32F2xx/adc_lld.c
@@ -181,8 +181,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
  */
 void adc_lld_init(void) {
 
-  ADC->CCR = STM32_ADC_ADCPRE;
-
 #if STM32_ADC_USE_ADC1
   /* Driver initialization.*/
   adcObjectInit(&ADCD1);
@@ -277,6 +275,10 @@ void adc_lld_start(ADCDriver *adcp) {
     }
 #endif /* STM32_ADC_USE_ADC3 */
 
+    /* This is a common register but apparently it requires that at least one
+       of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+    ADC->CCR = STM32_ADC_ADCPRE << 16;
+
     /* ADC initial setup, starting the analog part here in order to reduce
        the latency when starting a conversion.*/
     adcp->adc->CR1 = 0;
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index 4340f8fa7..479018519 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -181,8 +181,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
  */
 void adc_lld_init(void) {
 
-  ADC->CCR = STM32_ADC_ADCPRE;
-
 #if STM32_ADC_USE_ADC1
   /* Driver initialization.*/
   adcObjectInit(&ADCD1);
@@ -277,6 +275,10 @@ void adc_lld_start(ADCDriver *adcp) {
     }
 #endif /* STM32_ADC_USE_ADC3 */
 
+    /* This is a common register but apparently it requires that at least one
+       of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+    ADC->CCR = STM32_ADC_ADCPRE << 16;
+
     /* ADC initial setup, starting the analog part here in order to reduce
        the latency when starting a conversion.*/
     adcp->adc->CR1 = 0;
diff --git a/readme.txt b/readme.txt
index fe845e9ca..9e12f2cab 100644
--- a/readme.txt
+++ b/readme.txt
@@ -79,6 +79,7 @@
 *****************************************************************************
 
 *** 2.4.3 ***
+- FIX: Fixed STM32F4 ADC prescaler incorrectly initialized (bug 3575297).
 - FIX: Fixed RCC_APB2ENR_IOPEEN undeclared on STM32F10X_LD_VL devices (bug
   3575098).
 - FIX: Fixed optimization disable (-O0) breaks kernel in CortexM/RVCT (bug