git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3017 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/ports/GCC/ARMCMx/crt0.c

@@ -21,7 +21,7 @@
  * @file    ARMCMx/crt0.c
  * @brief   Generic ARMvx-M (Cortex-M0/M1/M3/M4) startup file for ChibiOS/RT.
  *
- * @addtogroup ARMCMx_CORE
+ * @addtogroup ARMCMx_STARTUP
  * @{
  */
 

os/ports/GCC/ARMCMx/port.dox

@@ -159,17 +159,24 @@
  * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
  *   thread. Usually there is no need to change this value unless inserting
  *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
- *   code. Code running at higher priority levels must not invoke any OS API.
- *   This setting is specific to the ARMv7-M architecture.
  * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
  * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
  * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
  *   @p <b>wfi</b> instruction from within the idle loop. This option is
  *   defaulted to FALSE because it can create problems with some debuggers.
  *   Setting this option to TRUE reduces the system power requirements.
  * .
+ * @section ARMCMx_CONF_1 ARMv6-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
+ *   exception instead of NMI as preemption handler.
+ * .
+ * @section ARMCMx_CONF_2 ARMv7-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
+ * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
+ *   mode.
+ * .
  * @ingroup ARMCMx
  */
 
@@ -219,15 +226,19 @@
  * @section ARMCMx_STARTUP_2 Expected linker symbols
  * The startup code starts at the symbol @p ResetHandler and expects the
  * following symbols to be defined in the linker script:
- * - @p __ram_end__ RAM end location +1.
+ * - @p __ram_end__ End of RAM.
  * - @p __main_stack_size__ Exception stack size.
  * - @p __process_stack_size__ Process stack size. This is the stack area used
  *      by the @p main() function.
- * - @p _textdata address of the data segment source read only data.
+ * - @p _textdata Address of the data segment source read only data.
- * - @p _data data segment start location.
+ * - @p _data Start of the data segment.
- * - @p _edata data segment end location +1.
+ * - @p _edata End of the data segment end location.
- * - @p _bss_start BSS start location.
+ * - @p _bss_start Start of the BSS.
- * - @p _bss_end BSS end location +1.
+ * - @p _bss_end End of the BSS segment.
+ * - @p __init_array_start Start of the constructors array.
+ * - @p __init_array_end End of the constructors array.
+ * - @p __fini_array_start Start of the destructors array.
+ * - @p __fini_array_end End of the destructors array.
  * .
  * @ingroup ARMCMx
  */

os/ports/IAR/ARMCMx/port.dox

@@ -26,9 +26,28 @@
  * This port supports all the cores implementing the ARMv6-M and ARMv7-M
  * architectures.
  *
- * @section IAR_ARMCMx_STATES_A System logical states in ARMv6-M mode
+ * @section IAR_ARMCMx_MODES Kernel Modes
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
+ * The Cortex-Mx port supports two distinct kernel modes:
- * Cortex-M0 port:
+ * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
+ *   interrupt sources with priorities below or equal to the
+ *   @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
+ *   the kernel critical sections and can be used for fast interrupts.
+ *   This mode is not available in the ARMv6-M architecture which does not
+ *   support priority masking.
+ * - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
+ *   in a simplified way, all interrupt sources are disabled when the kernel
+ *   enters into a critical zone and re-enabled on exit. This is simple and
+ *   adequate for most applications, this mode results in a more compact and
+ *   faster kernel.
+ * .
+ * The selection of the mode is performed using the port configuration option
+ * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
+ * interrupts there are no other differences between the two modes. The
+ * kernel API is exactly the same.
+ *
+ * @section IAR_ARMCMx_STATES_A System logical states in Compact Kernel mode
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
+ * Kernel mode:
  * - <b>Init</b>. This state is represented by the startup code and the
  *   initialization code before @p chSysInit() is executed. It has not a
  *   special hardware state associated.
@@ -53,21 +72,21 @@
  *   mode.
  * - <b>Serving Fast Interrupt</b>. This state is not implemented in the
  *   ARMv6-M implementation.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
  *   asynchronous NMI vector and several synchronous fault vectors that can
  *   be considered belonging to this category.
  * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
  *   the maskable interrupt sources. The ARM state is whatever the processor
  *   was running when @p chSysHalt() was invoked.
  *
- * @section IAR_ARMCMx_STATES_B System logical states in ARMv7-M mode
+ * @section IAR_ARMCMx_STATES_B System logical states in Advanced Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * Cortex-M3 port:
+ * Advanced Kernel mode:
  * - <b>Init</b>. This state is represented by the startup code and the
  *   initialization code before @p chSysInit() is executed. It has not a
  *   special hardware state associated.
  * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
+ *   @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
  *   set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
  *   processor is running in thread-privileged mode.
  * - <b>Suspended</b>. In this state the interrupt sources are not globally
@@ -93,7 +112,7 @@
  * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
  *   but it is not possible to switch to the I-Locked state because fast
  *   interrupts can preempt the kernel critical zone.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
  *   asynchronous NMI vector and several synchronous fault vectors that can
  *   be considered belonging to this category.
  * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
@@ -140,17 +159,24 @@
  * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
  *   thread. Usually there is no need to change this value unless inserting
  *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
- *   code. Code running at higher priority levels must not invoke any OS API.
- *   This setting is specific to the ARMv7-M architecture.
  * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
  * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
  * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
  *   @p <b>wfi</b> instruction from within the idle loop. This option is
  *   defaulted to FALSE because it can create problems with some debuggers.
  *   Setting this option to TRUE reduces the system power requirements.
  * .
+ * @section IAR_ARMCMx_CONF_1 ARMv6-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
+ *   exception instead of NMI as preemption handler.
+ * .
+ * @section IAR_ARMCMx_CONF_2 ARMv7-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
+ * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
+ *   mode.
+ * .
  * @ingroup IAR_ARMCMx
  */
 

os/ports/RVCT/ARMCMx/port.dox

@@ -26,9 +26,28 @@
  * This port supports all the cores implementing the ARMv6-M and ARMv7-M
  * architectures.
  *
- * @section RVCT_ARMCMx_STATES_A System logical states in ARMv6-M mode
+ * @section RVCT_ARMCMx_MODES Kernel Modes
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
+ * The Cortex-Mx port supports two distinct kernel modes:
- * Cortex-M0 port:
+ * - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
+ *   interrupt sources with priorities below or equal to the
+ *   @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
+ *   the kernel critical sections and can be used for fast interrupts.
+ *   This mode is not available in the ARMv6-M architecture which does not
+ *   support priority masking.
+ * - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
+ *   in a simplified way, all interrupt sources are disabled when the kernel
+ *   enters into a critical zone and re-enabled on exit. This is simple and
+ *   adequate for most applications, this mode results in a more compact and
+ *   faster kernel.
+ * .
+ * The selection of the mode is performed using the port configuration option
+ * @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
+ * interrupts there are no other differences between the two modes. The
+ * kernel API is exactly the same.
+ *
+ * @section RVCT_ARMCMx_STATES_A System logical states in Compact Kernel mode
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
+ * Kernel mode:
  * - <b>Init</b>. This state is represented by the startup code and the
  *   initialization code before @p chSysInit() is executed. It has not a
  *   special hardware state associated.
@@ -53,21 +72,21 @@
  *   mode.
  * - <b>Serving Fast Interrupt</b>. This state is not implemented in the
  *   ARMv6-M implementation.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
  *   asynchronous NMI vector and several synchronous fault vectors that can
  *   be considered belonging to this category.
  * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
  *   the maskable interrupt sources. The ARM state is whatever the processor
  *   was running when @p chSysHalt() was invoked.
  *
- * @section RVCT_ARMCMx_STATES_B System logical states in ARMv7-M mode
+ * @section RVCT_ARMCMx_STATES_B System logical states in Advanced Kernel mode
- * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the
- * Cortex-M3 port:
+ * Advanced Kernel mode:
  * - <b>Init</b>. This state is represented by the startup code and the
  *   initialization code before @p chSysInit() is executed. It has not a
  *   special hardware state associated.
  * - <b>Normal</b>. This is the state the system has after executing
- *   @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
+ *   @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
  *   set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
  *   processor is running in thread-privileged mode.
  * - <b>Suspended</b>. In this state the interrupt sources are not globally
@@ -93,7 +112,7 @@
  * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
  *   but it is not possible to switch to the I-Locked state because fast
  *   interrupts can preempt the kernel critical zone.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
  *   asynchronous NMI vector and several synchronous fault vectors that can
  *   be considered belonging to this category.
  * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
@@ -140,17 +159,24 @@
  * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
  *   thread. Usually there is no need to change this value unless inserting
  *   code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
- * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
- *   code. Code running at higher priority levels must not invoke any OS API.
- *   This setting is specific to the ARMv7-M architecture.
  * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
- * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
  * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
  * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
  *   @p <b>wfi</b> instruction from within the idle loop. This option is
  *   defaulted to FALSE because it can create problems with some debuggers.
  *   Setting this option to TRUE reduces the system power requirements.
  * .
+ * @section RVCT_ARMCMx_CONF_1 ARMv6-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
+ *   exception instead of NMI as preemption handler.
+ * .
+ * @section RVCT_ARMCMx_CONF_2 ARMv7-M specific options
+ * The following options are specific for the ARMv6-M architecture:
+ * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
+ * - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
+ *   mode.
+ * .
  * @ingroup RVCT_ARMCMx
  */
 

readme.txt

@@ -77,6 +77,8 @@
   Optimized the driver for single block read and write operations.
 - NEW: Finished the reorganization of the Cortex-Mx ports, now also the
   IAR and RVCT ports support the new Compact mode.
+- NEW: Added to the ARMv6-M sub-port an option to use the PendSV exception
+  instead of NMI for preemption (backported to 2.2.5).
 
 *** 2.3.3 ***
 - FIX: Fixed race condition in output queues (bug 3303908)(backported
@@ -86,12 +88,12 @@
 - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420)
   (backported to 2.2.4).
 - NEW: Reorganization of the Cortex-Mx ports in order to reduced code and
-  comments duplication in the various headers.
+  comments duplication in the various headers (backported to 2.2.5).
 - NEW: Improved the ARMv7-M sub-port now there are two modes: Compact and
   Advanced.
   The advanced mode is equivalent to the previous versions, the compact mode
   is new and makes the kernel *much* smaller and generally faster but does
-  not support fast interrupts, see the reports for details.
+  not support fast interrupts (backported to 2.2.5).
 - NEW: Now the port layer exports info regarding the compiler and the port
   options. The info are printed into the test reports.
 - CHANGE: Renamed the macros IDLE_THREAD_STACK_SIZE and INT_REQUIRED_STACK