diff --git a/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.c b/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.c new file mode 100644 index 000000000..82ff9e8a0 --- /dev/null +++ b/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.c @@ -0,0 +1,566 @@ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.c + * @brief STM32G4xx Embedded Flash subsystem low level driver source. + * + * @addtogroup HAL_EFL + * @{ + */ + +#include + +#include "hal.h" + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U) + +#define FLASH_PDKEY1 0x04152637U +#define FLASH_PDKEY2 0xFAFBFCFDU + +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU + +#define FLASH_OPTKEY1 0x08192A3BU +#define FLASH_OPTKEY2 0x4C5D6E7FU + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EFL1 driver identifier. + */ +EFlashDriver EFLD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const flash_descriptor_t efl_lld_desc = { + /* Bank 1 & 2 (DBM) organisation. */ + .attributes = FLASH_ATTR_ERASED_IS_ONE | + FLASH_ATTR_MEMORY_MAPPED | + FLASH_ATTR_ECC_CAPABLE | + FLASH_ATTR_ECC_ZERO_LINE_CAPABLE, + .page_size = STM32_FLASH_LINE_SIZE, + .sectors_count = STM32_FLASH_SECTORS_PER_BANK * STM32_FLASH_NUMBER_OF_BANKS, + .sectors = NULL, + .sectors_size = STM32_FLASH_SECTOR_SIZE, + .address = (uint8_t *)FLASH_BASE, + .size = STM32_FLASH_NUMBER_OF_BANKS * STM32_FLASH_SECTORS_PER_BANK * STM32_FLASH_SECTOR_SIZE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static inline void stm32_flash_lock(EFlashDriver *eflp) { + + eflp->flash->CR |= FLASH_CR_LOCK; +} + +static inline void stm32_flash_unlock(EFlashDriver *eflp) { + + eflp->flash->KEYR |= FLASH_KEY1; + eflp->flash->KEYR |= FLASH_KEY2; +} + +static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) { + + eflp->flash->CR |= FLASH_CR_PG; +} + +static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) { + + eflp->flash->CR &= ~FLASH_CR_PG; +} + +static inline void stm32_flash_clear_status(EFlashDriver *eflp) { + + eflp->flash->SR = 0x0000FFFFU; +} + +static inline void stm32_flash_wait_busy(EFlashDriver *eflp) { + + /* Wait for busy bit clear.*/ + while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) { + } +} + +static inline size_t stm32_flash_get_size(void) { + return *(uint16_t*)((uint32_t) STM32_FLASH_SIZE_REGISTER) * STM32_FLASH_SIZE_SCALE; +} + +static inline bool stm32_flash_dual_bank(EFlashDriver *eflp) { + +#if STM32_FLASH_NUMBER_OF_BANKS > 1 + return ((eflp->flash->OPTR & (FLASH_OPTR_DBANK)) != 0U); +#endif + return false; +} + +static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) { + uint32_t sr = eflp->flash->SR; + + /* Clearing error conditions.*/ + eflp->flash->SR = sr & 0x0000FFFFU; + + /* Some errors are only caught by assertion.*/ + osalDbgAssert((sr & (FLASH_SR_FASTERR | + FLASH_SR_MISERR | + FLASH_SR_SIZERR)) == 0U, "unexpected flash error"); + + /* Decoding relevant errors.*/ + if ((sr & FLASH_SR_WRPERR) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)) != 0U) { + return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE; + } + + return FLASH_NO_ERROR; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level Embedded Flash driver initialization. + * + * @notapi + */ +void efl_lld_init(void) { + + /* Driver initialization.*/ + eflObjectInit(&EFLD1); + EFLD1.flash = FLASH; + EFLD1.descriptor = &efl_lld_desc; +} + +/** + * @brief Configures and activates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_start(EFlashDriver *eflp) { + stm32_flash_unlock(eflp); + FLASH->CR = 0x00000000U; +} + +/** + * @brief Deactivates the Embedded Flash peripheral. + * + * @param[in] eflp pointer to a @p EFlashDriver structure + * + * @notapi + */ +void efl_lld_stop(EFlashDriver *eflp) { + + stm32_flash_lock(eflp); +} + +/** + * @brief Gets the flash descriptor structure. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return A flash device descriptor. + * @retval Pointer to single bank if DBM not enabled. + * @retval Pointer to bank1 if DBM enabled. + * + * @notapi + */ +const flash_descriptor_t *efl_lld_get_descriptor(void *instance) { + EFlashDriver *devp = (EFlashDriver *)instance; + return devp->descriptor; +} + +/** + * @brief Read operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be read + * @param[out] rp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_READ if the read operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); + + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + osalDbgCheck((size_t)offset + n <= (size_t)bank->size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No reading while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Actual read implementation.*/ + memcpy((void *)rp, (const void *)efl_lld_get_descriptor(instance)->address + + offset, n); + + /* Checking for errors after reading.*/ + if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) { + err = FLASH_ERROR_READ; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; + +} + +/** + * @brief Program operation. + * @note The device supports ECC. It is only possible to write erased + * pages once except when writing all zeroes to a location. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] offset offset within full flash address space + * @param[in] n number of bytes to be programmed + * @param[in] pp pointer to the data buffer + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_PROGRAM if the program operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp) { + EFlashDriver *devp = (EFlashDriver *)instance; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + flash_error_t err = FLASH_NO_ERROR; + + osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); + osalDbgCheck((size_t)offset + n <= (size_t)bank->size); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No programming while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_PGM; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Enabling PGM mode in the controller.*/ + stm32_flash_enable_pgm(devp); + + /* Actual program implementation.*/ + while (n > 0U) { + volatile uint32_t *address; + + union { + uint32_t w[STM32_FLASH_LINE_SIZE / sizeof (uint32_t)]; + uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)]; + } line; + + /* Unwritten bytes are initialized to all ones.*/ + line.w[0] = 0xFFFFFFFFU; + line.w[1] = 0xFFFFFFFFU; + + /* Programming address aligned to flash lines.*/ + address = (volatile uint32_t *)(bank->address + + (offset & ~STM32_FLASH_LINE_MASK)); + + /* Copying data inside the prepared line.*/ + do { + line.b[offset & STM32_FLASH_LINE_MASK] = *pp; + offset++; + n--; + pp++; + } + while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U)); + + /* Programming line.*/ + address[0] = line.w[0]; + address[1] = line.w[1]; + stm32_flash_wait_busy(devp); + err = stm32_flash_check_errors(devp); + if (err != FLASH_NO_ERROR) { + break; + } + } + + /* Disabling PGM mode in the controller.*/ + stm32_flash_disable_pgm(devp); + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +/** + * @brief Starts a whole-device erase operation. + * @note This function only erases bank 2 if it is present. Bank 1 is not + * allowed since it is normally where the primary program is located. + * Pages on bank 1 can be individually erased. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_all(void *instance) { + EFlashDriver *devp = (EFlashDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + +#if defined(FLASH_CR_MER2) + /* If dual bank is active then mass erase bank2. */ + if (stm32_flash_dual_bank(devp)) { + + /* FLASH_ERASE state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + devp->flash->CR |= FLASH_CR_MER2; + devp->flash->CR |= FLASH_CR_STRT; + return FLASH_NO_ERROR; + } +#endif + + /* Mass erase not allowed. */ + return FLASH_ERROR_UNIMPLEMENTED; +} + +/** + * @brief Starts an sector erase operation. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be erased + * this is an index within the total sectors + * in a flash bank + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < bank->sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No erasing while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* FLASH_PGM state while the operation is performed.*/ + devp->state = FLASH_ERASE; + + /* Clearing error status bits.*/ + stm32_flash_clear_status(devp); + + /* Enable page erase.*/ + devp->flash->CR |= FLASH_CR_PER; + +#if defined(FLASH_CR_BKER) + /* If dual bank is active then setup relevant bank. */ + if (stm32_flash_dual_bank(devp)) { + if (sector < (bank->sectors_count / 2)) { + /* First bank.*/ + devp->flash->CR &= ~FLASH_CR_BKER; + } + else { + /* Second bank. Adjust sector index. */ + sector -= (bank->sectors_count / 2); + devp->flash->CR |= FLASH_CR_BKER; + } + } +#endif + + /* Mask off the page selection bits.*/ + devp->flash->CR &= ~FLASH_CR_PNB; + + /* Set the page selection bits.*/ + devp->flash->CR |= sector << FLASH_CR_PNB_Pos; + + /* Start the erase.*/ + devp->flash->CR |= FLASH_CR_STRT; + + return FLASH_NO_ERROR; +} + +/** + * @brief Queries the driver for erase operation progress. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[out] msec recommended time, in milliseconds, that + * should be spent before calling this + * function again, can be @p NULL + * @return An error code. + * @retval FLASH_NO_ERROR if there is no erase operation in progress. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_ERASE if the erase operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @api + */ +flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) { + EFlashDriver *devp = (EFlashDriver *)instance; + flash_error_t err; + + /* If there is an erase in progress then the device must be checked.*/ + if (devp->state == FLASH_ERASE) { + + /* Checking for operation in progress.*/ + if ((devp->flash->SR & FLASH_SR_BSY) == 0U) { + + /* Disabling the various erase control bits.*/ + devp->flash->CR &= ~(FLASH_CR_MER1 | +#if defined(FLASH_CR_MER2) + FLASH_CR_MER2 | +#endif + FLASH_CR_PER); + + /* No operation in progress, checking for errors.*/ + err = stm32_flash_check_errors(devp); + + /* Back to ready state.*/ + devp->state = FLASH_READY; + } + else { + /* Recommended time before polling again. This is a simplified + implementation.*/ + if (msec != NULL) { + *msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS; + } + + err = FLASH_BUSY_ERASING; + } + } + else { + err = FLASH_NO_ERROR; + } + + return err; +} + +/** + * @brief Returns the erase state of a sector. + * + * @param[in] ip pointer to a @p EFlashDriver instance + * @param[in] sector sector to be verified + * @return An error code. + * @retval FLASH_NO_ERROR if the sector is erased. + * @retval FLASH_BUSY_ERASING if there is an erase operation in progress. + * @retval FLASH_ERROR_VERIFY if the verify operation failed. + * @retval FLASH_ERROR_HW_FAILURE if access to the memory failed. + * + * @notapi + */ +flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) { + EFlashDriver *devp = (EFlashDriver *)instance; + uint32_t *address; + const flash_descriptor_t *bank = efl_lld_get_descriptor(instance); + flash_error_t err = FLASH_NO_ERROR; + unsigned i; + + osalDbgCheck(instance != NULL); + osalDbgCheck(sector < bank->sectors_count); + osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), + "invalid state"); + + /* No verifying while erasing.*/ + if (devp->state == FLASH_ERASE) { + return FLASH_BUSY_ERASING; + } + + /* Address of the sector in the bank.*/ + address = (uint32_t *)(bank->address + + flashGetSectorOffset(getBaseFlash(devp), sector)); + + /* FLASH_READ state while the operation is performed.*/ + devp->state = FLASH_READ; + + /* Scanning the sector space.*/ + uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector); + for (i = 0U; i < sector_size / sizeof(uint32_t); i++) { + if (*address != 0xFFFFFFFFU) { + err = FLASH_ERROR_VERIFY; + break; + } + address++; + } + + /* Ready state again.*/ + devp->state = FLASH_READY; + + return err; +} + +#endif /* HAL_USE_EFL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.h b/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.h new file mode 100644 index 000000000..dbb971fa5 --- /dev/null +++ b/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.h @@ -0,0 +1,130 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_efl_lld.h + * @brief STM32G4xx Embedded Flash subsystem low level driver header. + * + * @addtogroup HAL_EFL + * @{ + */ + +#ifndef HAL_EFL_LLD_H +#define HAL_EFL_LLD_H + +#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name STM32G4xx configuration options + * @{ + */ +/** + * @brief Suggested wait time during erase operations polling. + */ +#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) +#define STM32_FLASH_WAIT_TIME_MS 22 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(STM32_FLASH_SECTOR_SIZE) +#error "STM32_FLASH_SECTOR_SIZE not defined in registry" +#endif + +#if !defined(STM32_FLASH_NUMBER_OF_BANKS) +#error "STM32_FLASH_NUMBER_OF_BANKS not defined in registry" +#endif + +#if !defined(STM32_FLASH_SECTORS_PER_BANK) +#error "STM32_FLASH_SECTORS_PER_BANK not defined in registry" +#endif + +/* Flash size register. */ +#define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0 +#define STM32_FLASH_SIZE_SCALE 1024U + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/* A flash size declaration. */ +typedef struct { + const flash_descriptor_t* desc; +} efl_lld_size_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the embedded flash driver structure. + */ +#define efl_lld_driver_fields \ + /* Flash registers.*/ \ + FLASH_TypeDef *flash; \ + const flash_descriptor_t *descriptor; + +/** + * @brief Low level fields of the embedded flash configuration structure. + */ +#define efl_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EFlashDriver EFLD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void efl_lld_init(void); + void efl_lld_start(EFlashDriver *eflp); + void efl_lld_stop(EFlashDriver *eflp); + const flash_descriptor_t *efl_lld_get_descriptor(void *instance); + flash_error_t efl_lld_read(void *instance, flash_offset_t offset, + size_t n, uint8_t *rp); + flash_error_t efl_lld_program(void *instance, flash_offset_t offset, + size_t n, const uint8_t *pp); + flash_error_t efl_lld_start_erase_all(void *instance); + flash_error_t efl_lld_start_erase_sector(void *instance, + flash_sector_t sector); + flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec); + flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EFL == TRUE */ + +#endif /* HAL_EFL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32G4xx/platform.mk b/os/hal/ports/STM32/STM32G4xx/platform.mk index 93b13e2c0..dee5b31f4 100644 --- a/os/hal/ports/STM32/STM32G4xx/platform.mk +++ b/os/hal/ports/STM32/STM32G4xx/platform.mk @@ -1,48 +1,49 @@ -# Required platform files. -PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/stm32_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/hal_lld.c - -# Required include directories. -PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ - $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx - -# Optional platform files. -ifeq ($(USE_SMART_BUILD),yes) - -# Configuration files directory -ifeq ($(HALCONFDIR),) - ifeq ($(CONFDIR),) - HALCONFDIR = . - else - HALCONFDIR := $(CONFDIR) - endif -endif - -HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) - -else -endif - -# Drivers compatible with the platform. -include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/FDCANv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver_v2.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk -include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk - -# Shared variables -ALLCSRC += $(PLATFORMSRC) -ALLINC += $(PLATFORMINC) +# Required platform files. +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/stm32_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/hal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/hal_efl_lld.c + +# Required include directories. +PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/FDCANv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver_v2.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/STM32/STM32G4xx/stm32_registry.h b/os/hal/ports/STM32/STM32G4xx/stm32_registry.h index 392dfd289..a713b15c0 100644 --- a/os/hal/ports/STM32/STM32G4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32G4xx/stm32_registry.h @@ -1,753 +1,758 @@ -/* - ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32G4xx/stm32_registry.h - * @brief STM32G4xx capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef STM32_REGISTRY_H -#define STM32_REGISTRY_H - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32G4xx capabilities - * @{ - */ - -/*===========================================================================*/ -/* Common. */ -/*===========================================================================*/ - -/* RNG attributes.*/ -#define STM32_HAS_RNG1 TRUE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_STORAGE_SIZE 128 -#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 -#define STM32_RTC_WKUP_HANDLER Vector4C -#define STM32_RTC_ALARM_HANDLER VectorE4 -#define STM32_RTC_TAMP_STAMP_NUMBER 2 -#define STM32_RTC_WKUP_NUMBER 3 -#define STM32_RTC_ALARM_NUMBER 41 -#define STM32_RTC_ALARM_EXTI 18 -#define STM32_RTC_TAMP_STAMP_EXTI 19 -#define STM32_RTC_WKUP_EXTI 20 -#define STM32_RTC_IRQ_ENABLE() do { \ - nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ - nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ - nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \ -} while (false) - - /* Enabling RTC-related EXTI lines.*/ -#define STM32_RTC_ENABLE_ALL_EXTI() do { \ - extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \ - EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \ - EXTI_MASK1(STM32_RTC_WKUP_EXTI), \ - EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \ -} while (false) - -/* Clearing EXTI interrupts. */ -#define STM32_RTC_CLEAR_ALL_EXTI() do { \ - extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \ - EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \ - EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \ -} while (false) - -/* Masks used to preserve state of RTC and TAMP register reserved bits. */ -#define STM32_RTC_CR_MASK 0xE7FFFF7F -#define STM32_RTC_PRER_MASK 0x007F7FFF -#define STM32_TAMP_CR1_MASK 0x003C0007 -#define STM32_TAMP_CR2_MASK 0x07070007 -#define STM32_TAMP_FLTCR_MASK 0x000000FF -#define STM32_TAMP_IER_MASK 0x003C0007 - -#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ - defined(__DOXYGEN__) -#define STM32_HAS_HASH1 TRUE -#define STM32_HAS_CRYP1 TRUE -#else -#define STM32_HAS_HASH1 FALSE -#define STM32_HAS_CRYP1 FALSE -#endif - -/* RCC attributes.*/ -#define STM32_RCC_HAS_HSI16 TRUE -#define STM32_RCC_HAS_HSI48 TRUE -#define STM32_RCC_HAS_MSI FALSE -#define STM32_RCC_HAS_LSI TRUE -#define STM32_RCC_HAS_LSI_PRESCALER FALSE -#define STM32_RCC_HAS_LSE TRUE -#define STM32_RCC_HAS_HSE TRUE - -#define STM32_RCC_HAS_PLL TRUE -#define STM32_RCC_PLL_HAS_P TRUE -#define STM32_RCC_PLL_HAS_Q TRUE -#define STM32_RCC_PLL_HAS_R TRUE - -#define STM32_RCC_HAS_PLLSAI1 FALSE -#define STM32_RCC_HAS_PLLSAI2 FALSE - -/*===========================================================================*/ -/* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */ -/*===========================================================================*/ - -#if defined(STM32G473xx) || defined(STM32G483xx) || \ - defined(STM32G474xx) || defined(STM32G484xx) || \ - defined(__DOXYGEN__) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE -#define STM32_HAS_ADC4 TRUE -#define STM32_HAS_ADC5 TRUE - -/* CAN attributes.*/ -#define STM32_HAS_FDCAN1 TRUE -#define STM32_HAS_FDCAN2 TRUE -#define STM32_HAS_FDCAN3 TRUE -#define STM32_FDCAN_FLS_NBR 28U -#define STM32_FDCAN_FLE_NBR 8U -#define STM32_FDCAN_RF0_NBR 3U -#define STM32_FDCAN_RF1_NBR 3U -#define STM32_FDCAN_RB_NBR 0U -#define STM32_FDCAN_TEF_NBR 3U -#define STM32_FDCAN_TB_NBR 3U -#define STM32_FDCAN_TM_NBR 0U - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_HAS_DAC2_CH1 TRUE -#define STM32_HAS_DAC2_CH2 FALSE -#define STM32_HAS_DAC3_CH1 TRUE -#define STM32_HAS_DAC3_CH2 TRUE -#define STM32_HAS_DAC4_CH1 TRUE -#define STM32_HAS_DAC4_CH2 TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 8 -#define STM32_DMA2_NUM_CHANNELS 8 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_HAS_CR FALSE -#define STM32_EXTI_SEPARATE_RF FALSE -#define STM32_EXTI_NUM_LINES 44 -#define STM32_EXTI_IMR1_MASK 0x1F840000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 2 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ - RCC_AHB2ENR_GPIOBEN | \ - RCC_AHB2ENR_GPIOCEN | \ - RCC_AHB2ENR_GPIODEN | \ - RCC_AHB2ENR_GPIOEEN | \ - RCC_AHB2ENR_GPIOFEN | \ - RCC_AHB2ENR_GPIOGEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_HAS_I2C4 TRUE - -/* OCTOSPI attributes.*/ -#define STM32_HAS_OCTOSPI1 FALSE -#define STM32_HAS_OCTOSPI2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 TRUE - -/* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 6 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 6 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 - -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 1 - -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 1 - -#define STM32_HAS_TIM20 TRUE -#define STM32_TIM20_IS_32BITS FALSE -#define STM32_TIM20_CHANNELS 6 - -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* OTG/USB attributes.*/ -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 -#define STM32_USB_HAS_BCDR TRUE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED TRUE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE - -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - -#endif /* defined(STM32G474xx) || defined(STM32G484xx) */ - -/*===========================================================================*/ -/* STM32G491xx. */ -/*===========================================================================*/ - -#if defined(STM32G491xx) || \ - defined(__DOXYGEN__) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE -#define STM32_HAS_ADC4 FALSE -#define STM32_HAS_ADC5 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_FDCAN1 TRUE -#define STM32_HAS_FDCAN2 TRUE -#define STM32_HAS_FDCAN3 FALSE -#define STM32_FDCAN_FLS_NBR 28U -#define STM32_FDCAN_FLE_NBR 8U -#define STM32_FDCAN_RF0_NBR 3U -#define STM32_FDCAN_RF1_NBR 3U -#define STM32_FDCAN_RB_NBR 0U -#define STM32_FDCAN_TEF_NBR 3U -#define STM32_FDCAN_TB_NBR 3U -#define STM32_FDCAN_TM_NBR 0U - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE -#define STM32_HAS_DAC3_CH1 TRUE -#define STM32_HAS_DAC3_CH2 TRUE -#define STM32_HAS_DAC4_CH1 FALSE -#define STM32_HAS_DAC4_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 8 -#define STM32_DMA2_NUM_CHANNELS 8 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_HAS_CR FALSE -#define STM32_EXTI_SEPARATE_RF FALSE -#define STM32_EXTI_NUM_LINES 44 -#define STM32_EXTI_IMR1_MASK 0x1F840000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 2 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ - RCC_AHB2ENR_GPIOBEN | \ - RCC_AHB2ENR_GPIOCEN | \ - RCC_AHB2ENR_GPIODEN | \ - RCC_AHB2ENR_GPIOEEN | \ - RCC_AHB2ENR_GPIOFEN | \ - RCC_AHB2ENR_GPIOGEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_HAS_I2C4 FALSE - -/* OCTOSPI attributes.*/ -#define STM32_HAS_OCTOSPI1 FALSE -#define STM32_HAS_OCTOSPI2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 TRUE - -/* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI4 FALSE -#define STM32_SPI4_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 6 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 FALSE -#define STM32_TIM5_IS_32BITS FALSE -#define STM32_TIM5_CHANNELS 0 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 4 - -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 - -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 1 - -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 1 - -#define STM32_HAS_TIM20 TRUE -#define STM32_TIM20_IS_32BITS FALSE -#define STM32_TIM20_CHANNELS 4 - -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* OTG/USB attributes.*/ -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 -#define STM32_USB_HAS_BCDR TRUE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED TRUE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE - -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - -#endif /* defined(STM32G491xx) */ - -/*===========================================================================*/ -/* STM32G431xx, STM32G441xx, STM32G471xx. */ -/*===========================================================================*/ - -#if defined(STM32G431xx) || defined(STM32G441xx) || \ - defined(__DOXYGEN__) - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE -#define STM32_HAS_ADC5 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_FDCAN1 TRUE -#define STM32_HAS_FDCAN2 FALSE -#define STM32_HAS_FDCAN3 FALSE -#define STM32_FDCAN_FLS_NBR 28U -#define STM32_FDCAN_FLE_NBR 8U -#define STM32_FDCAN_RF0_NBR 3U -#define STM32_FDCAN_RF1_NBR 3U -#define STM32_FDCAN_RB_NBR 0U -#define STM32_FDCAN_TEF_NBR 3U -#define STM32_FDCAN_TB_NBR 3U -#define STM32_FDCAN_TM_NBR 0U - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE -#define STM32_HAS_DAC3_CH1 TRUE -#define STM32_HAS_DAC3_CH2 TRUE -#define STM32_HAS_DAC4_CH1 FALSE -#define STM32_HAS_DAC4_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 6 -#define STM32_DMA2_NUM_CHANNELS 6 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_HAS_CR FALSE -#define STM32_EXTI_SEPARATE_RF FALSE -#define STM32_EXTI_NUM_LINES 44 -#define STM32_EXTI_IMR1_MASK 0x1F840000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 2 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ - RCC_AHB2ENR_GPIOBEN | \ - RCC_AHB2ENR_GPIOCEN | \ - RCC_AHB2ENR_GPIODEN | \ - RCC_AHB2ENR_GPIOEEN | \ - RCC_AHB2ENR_GPIOFEN | \ - RCC_AHB2ENR_GPIOGEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_HAS_I2C4 FALSE - -/* OCTOSPI attributes.*/ -#define STM32_HAS_OCTOSPI1 FALSE -#define STM32_HAS_OCTOSPI2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 FALSE - -/* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE - -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 6 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 6 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 - -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 1 - -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 1 - -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* OTG/USB attributes.*/ -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 -#define STM32_USB_HAS_BCDR TRUE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED TRUE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE - -/* DCMI attributes.*/ -#define STM32_HAS_DCMI FALSE - -#endif /* defined(STM32G431xx) || defined(STM32G441xx) */ - -/** @} */ - -#endif /* STM32_REGISTRY_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32G4xx/stm32_registry.h + * @brief STM32G4xx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef STM32_REGISTRY_H +#define STM32_REGISTRY_H + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32G4xx capabilities + * @{ + */ + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + +/* RNG attributes.*/ +#define STM32_HAS_RNG1 TRUE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_STORAGE_SIZE 128 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 18 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \ +} while (false) + + /* Enabling RTC-related EXTI lines.*/ +#define STM32_RTC_ENABLE_ALL_EXTI() do { \ + extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \ + EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \ + EXTI_MASK1(STM32_RTC_WKUP_EXTI), \ + EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \ +} while (false) + +/* Clearing EXTI interrupts. */ +#define STM32_RTC_CLEAR_ALL_EXTI() do { \ + extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \ + EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \ + EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \ +} while (false) + +/* Masks used to preserve state of RTC and TAMP register reserved bits. */ +#define STM32_RTC_CR_MASK 0xE7FFFF7F +#define STM32_RTC_PRER_MASK 0x007F7FFF +#define STM32_TAMP_CR1_MASK 0x003C0007 +#define STM32_TAMP_CR2_MASK 0x07070007 +#define STM32_TAMP_FLTCR_MASK 0x000000FF +#define STM32_TAMP_IER_MASK 0x003C0007 + +#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(__DOXYGEN__) +#define STM32_HAS_HASH1 TRUE +#define STM32_HAS_CRYP1 TRUE +#else +#define STM32_HAS_HASH1 FALSE +#define STM32_HAS_CRYP1 FALSE +#endif + +/* RCC attributes.*/ +#define STM32_RCC_HAS_HSI16 TRUE +#define STM32_RCC_HAS_HSI48 TRUE +#define STM32_RCC_HAS_MSI FALSE +#define STM32_RCC_HAS_LSI TRUE +#define STM32_RCC_HAS_LSI_PRESCALER FALSE +#define STM32_RCC_HAS_LSE TRUE +#define STM32_RCC_HAS_HSE TRUE + +#define STM32_RCC_HAS_PLL TRUE +#define STM32_RCC_PLL_HAS_P TRUE +#define STM32_RCC_PLL_HAS_Q TRUE +#define STM32_RCC_PLL_HAS_R TRUE + +#define STM32_RCC_HAS_PLLSAI1 FALSE +#define STM32_RCC_HAS_PLLSAI2 FALSE + +/*===========================================================================*/ +/* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */ +/*===========================================================================*/ + +#if defined(STM32G473xx) || defined(STM32G483xx) || \ + defined(STM32G474xx) || defined(STM32G484xx) || \ + defined(__DOXYGEN__) + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE +#define STM32_HAS_ADC4 TRUE +#define STM32_HAS_ADC5 TRUE + +/* CAN attributes.*/ +#define STM32_HAS_FDCAN1 TRUE +#define STM32_HAS_FDCAN2 TRUE +#define STM32_HAS_FDCAN3 TRUE +#define STM32_FDCAN_FLS_NBR 28U +#define STM32_FDCAN_FLE_NBR 8U +#define STM32_FDCAN_RF0_NBR 3U +#define STM32_FDCAN_RF1_NBR 3U +#define STM32_FDCAN_RB_NBR 0U +#define STM32_FDCAN_TEF_NBR 3U +#define STM32_FDCAN_TB_NBR 3U +#define STM32_FDCAN_TM_NBR 0U + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_HAS_DAC2_CH1 TRUE +#define STM32_HAS_DAC2_CH2 FALSE +#define STM32_HAS_DAC3_CH1 TRUE +#define STM32_HAS_DAC3_CH2 TRUE +#define STM32_HAS_DAC4_CH1 TRUE +#define STM32_HAS_DAC4_CH2 TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE +#define STM32_DMA1_NUM_CHANNELS 8 +#define STM32_DMA2_NUM_CHANNELS 8 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_HAS_CR FALSE +#define STM32_EXTI_SEPARATE_RF FALSE +#define STM32_EXTI_NUM_LINES 44 +#define STM32_EXTI_IMR1_MASK 0x1F840000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU + +/* Flash attributes.*/ +#define STM32_FLASH_NUMBER_OF_BANKS 2 +#define STM32_FLASH_SECTOR_SIZE 2048U +#define STM32_FLASH_LINE_SIZE 8U +#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ + RCC_AHB2ENR_GPIOBEN | \ + RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | \ + RCC_AHB2ENR_GPIOEEN | \ + RCC_AHB2ENR_GPIOFEN | \ + RCC_AHB2ENR_GPIOGEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 TRUE +#define STM32_HAS_I2C4 TRUE + +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE +#define STM32_HAS_OCTOSPI2 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM20 TRUE +#define STM32_TIM20_IS_32BITS FALSE +#define STM32_TIM20_CHANNELS 6 + +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* OTG/USB attributes.*/ +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 1024 +#define STM32_USB_HAS_BCDR TRUE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE + +/* DCMI attributes.*/ +#define STM32_HAS_DCMI FALSE + +#endif /* defined(STM32G474xx) || defined(STM32G484xx) */ + +/*===========================================================================*/ +/* STM32G491xx. */ +/*===========================================================================*/ + +#if defined(STM32G491xx) || \ + defined(__DOXYGEN__) + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE +#define STM32_HAS_ADC4 FALSE +#define STM32_HAS_ADC5 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_FDCAN1 TRUE +#define STM32_HAS_FDCAN2 TRUE +#define STM32_HAS_FDCAN3 FALSE +#define STM32_FDCAN_FLS_NBR 28U +#define STM32_FDCAN_FLE_NBR 8U +#define STM32_FDCAN_RF0_NBR 3U +#define STM32_FDCAN_RF1_NBR 3U +#define STM32_FDCAN_RB_NBR 0U +#define STM32_FDCAN_TEF_NBR 3U +#define STM32_FDCAN_TB_NBR 3U +#define STM32_FDCAN_TM_NBR 0U + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE +#define STM32_HAS_DAC3_CH1 TRUE +#define STM32_HAS_DAC3_CH2 TRUE +#define STM32_HAS_DAC4_CH1 FALSE +#define STM32_HAS_DAC4_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE +#define STM32_DMA1_NUM_CHANNELS 8 +#define STM32_DMA2_NUM_CHANNELS 8 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_HAS_CR FALSE +#define STM32_EXTI_SEPARATE_RF FALSE +#define STM32_EXTI_NUM_LINES 44 +#define STM32_EXTI_IMR1_MASK 0x1F840000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU + +/* Flash attributes.*/ +#define STM32_FLASH_NUMBER_OF_BANKS 2 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ + RCC_AHB2ENR_GPIOBEN | \ + RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | \ + RCC_AHB2ENR_GPIOEEN | \ + RCC_AHB2ENR_GPIOFEN | \ + RCC_AHB2ENR_GPIOGEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 TRUE +#define STM32_HAS_I2C4 FALSE + +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE +#define STM32_HAS_OCTOSPI2 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI4 FALSE +#define STM32_SPI4_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 FALSE +#define STM32_TIM5_IS_32BITS FALSE +#define STM32_TIM5_CHANNELS 0 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 4 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM20 TRUE +#define STM32_TIM20_IS_32BITS FALSE +#define STM32_TIM20_CHANNELS 4 + +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* OTG/USB attributes.*/ +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 1024 +#define STM32_USB_HAS_BCDR TRUE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE + +/* DCMI attributes.*/ +#define STM32_HAS_DCMI FALSE + +#endif /* defined(STM32G491xx) */ + +/*===========================================================================*/ +/* STM32G431xx, STM32G441xx, STM32G471xx. */ +/*===========================================================================*/ + +#if defined(STM32G431xx) || defined(STM32G441xx) || \ + defined(__DOXYGEN__) + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE +#define STM32_HAS_ADC5 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_FDCAN1 TRUE +#define STM32_HAS_FDCAN2 FALSE +#define STM32_HAS_FDCAN3 FALSE +#define STM32_FDCAN_FLS_NBR 28U +#define STM32_FDCAN_FLE_NBR 8U +#define STM32_FDCAN_RF0_NBR 3U +#define STM32_FDCAN_RF1_NBR 3U +#define STM32_FDCAN_RB_NBR 0U +#define STM32_FDCAN_TEF_NBR 3U +#define STM32_FDCAN_TB_NBR 3U +#define STM32_FDCAN_TM_NBR 0U + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE +#define STM32_HAS_DAC3_CH1 TRUE +#define STM32_HAS_DAC3_CH2 TRUE +#define STM32_HAS_DAC4_CH1 FALSE +#define STM32_HAS_DAC4_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE +#define STM32_DMA1_NUM_CHANNELS 6 +#define STM32_DMA2_NUM_CHANNELS 6 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_HAS_CR FALSE +#define STM32_EXTI_SEPARATE_RF FALSE +#define STM32_EXTI_NUM_LINES 44 +#define STM32_EXTI_IMR1_MASK 0x1F840000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU + +/* Flash attributes.*/ +#define STM32_FLASH_NUMBER_OF_BANKS 2 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ + RCC_AHB2ENR_GPIOBEN | \ + RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | \ + RCC_AHB2ENR_GPIOEEN | \ + RCC_AHB2ENR_GPIOFEN | \ + RCC_AHB2ENR_GPIOGEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 TRUE +#define STM32_HAS_I2C4 FALSE + +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE +#define STM32_HAS_OCTOSPI2 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* OTG/USB attributes.*/ +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 1024 +#define STM32_USB_HAS_BCDR TRUE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE + +/* DCMI attributes.*/ +#define STM32_HAS_DCMI FALSE + +#endif /* defined(STM32G431xx) || defined(STM32G441xx) */ + +/** @} */ + +#endif /* STM32_REGISTRY_H */ + +/** @} */ diff --git a/readme.txt b/readme.txt index 8dcacd5c1..5f60ec17d 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,7 @@ ***************************************************************************** *** Next *** +- NEW: Added EFL driver implementation for STM32G4xx. - NEW: Function chCoreGetStatusX() changed to return a memory region object instead of a simple size. - NEW: RT and NIL upgraded to support the enhanced OSLIB.