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ChibiOS
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F7 scatter files improvements. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8276 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2015-09-04 11:40:50 +00:00
parent 9ce1341931
commit 8b7eab2521
3 changed files with 26 additions and 16 deletions
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7
os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
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@ -49,10 +49,13 @@ REGION_ALIAS("DATA_RAM", ram0);
/* RAM region to be used for BSS segment.*/ /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0); REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for NOCACHE segment.*/ /* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3); REGION_ALIAS("NOCACHE_RAM", ram3);
/* RAM region to be used for ETH segment.*/ /* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3); REGION_ALIAS("ETH_RAM", ram3);
INCLUDE ld/rules_STM32F7xx.ld INCLUDE ld/rules_STM32F7xx.ld

7
os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld
View File

@ -48,10 +48,13 @@ REGION_ALIAS("DATA_RAM", ram1);
/* RAM region to be used for BSS segment.*/ /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram1); REGION_ALIAS("BSS_RAM", ram1);
/* RAM region to be used for NOCACHE segment.*/ /* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram1);
/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3); REGION_ALIAS("NOCACHE_RAM", ram3);
/* RAM region to be used for ETH segment.*/ /* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram2); REGION_ALIAS("ETH_RAM", ram2);
INCLUDE rules_dma.ld INCLUDE rules_dma.ld

28
os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
View File

@ -112,7 +112,7 @@ SECTIONS
/* Special section for non cache-able areas.*/ /* Special section for non cache-able areas.*/
.nocache (NOLOAD) : ALIGN(4) .nocache (NOLOAD) : ALIGN(4)
{ {
__nocache_start__ = .; __nocache_base__ = .;
*(.nocache) *(.nocache)
*(.nocache.*) *(.nocache.*)
*(.bss.__nocache_*) *(.bss.__nocache_*)
@ -121,14 +121,14 @@ SECTIONS
} > NOCACHE_RAM } > NOCACHE_RAM
/* Special section for Ethernet DMA non cache-able areas.*/ /* Special section for Ethernet DMA non cache-able areas.*/
.ethram (NOLOAD) : ALIGN(4) .eth (NOLOAD) : ALIGN(4)
{ {
__ethram_start__ = .; __eth_base__ = .;
*(.ethram) *(.eth)
*(.ethram.*) *(.eth.*)
*(.bss.__ethram_*) *(.bss.__eth_*)
. = ALIGN(4); . = ALIGN(4);
__ethram_end__ = .; __eth_end__ = .;
} > ETH_RAM } > ETH_RAM
.mstack : .mstack :
@ -256,9 +256,13 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
__ram7_free__ = .; __ram7_free__ = .;
} > ram7 } > ram7
}
/* Heap default boundaries, it is defaulted to be the non-used part /* The default heap uses the (statically) unused part of a RAM section.*/
of ram0 region.*/ .heap (NOLOAD) :
__heap_base__ = __ram0_free__; {
__heap_end__ = __ram0_end__; . = ALIGN(8);
__heap_base__ = .;
. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
__heap_end__ = .;
} > HEAP_RAM
}