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ChibiOS
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UART driver now compiles on G0. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12893 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-07-10 08:43:29 +00:00
parent 9544a26cd5
commit 8c335fdcf7
5 changed files with 49 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/halconf.h
View File

@ -177,7 +177,7 @@
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#define HAL_USE_UART TRUE
#endif
/**

6
demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h
View File

@ -181,10 +181,10 @@
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART1 TRUE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_USART3 TRUE
#define STM32_UART_USE_UART4 TRUE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY

84
os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
View File

@ -348,40 +348,6 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
_uart_tx1_isr_code(uartp);
}
/**
* @brief USART common service routine.
*
* @param[in] uartp pointer to the @p UARTDriver object
*/
static void serve_usart_irq(UARTDriver *uartp) {
uint32_t isr;
USART_TypeDef *u = uartp->usart;
uint32_t cr1 = u->CR1;
/* Reading and clearing status.*/
isr = u->ISR;
u->ICR = isr;
if (isr & (USART_ISR_LBDF | USART_ISR_ORE | USART_ISR_NE |
USART_ISR_FE | USART_ISR_PE)) {
_uart_rx_error_isr_code(uartp, translate_errors(isr));
}
if ((isr & USART_ISR_TC) && (cr1 & USART_CR1_TCIE)) {
/* TC interrupt disabled.*/
u->CR1 = cr1 & ~USART_CR1_TCIE;
/* End of transmission, a callback is generated.*/
_uart_tx2_isr_code(uartp);
}
/* Timeout interrupt sources are only checked if enabled in CR1.*/
if (((cr1 & USART_CR1_IDLEIE) && (isr & USART_ISR_IDLE)) ||
((cr1 & USART_CR1_RTOIE) && (isr & USART_ISR_RTOF))) {
_uart_timeout_isr_code(uartp);
}
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@ -400,7 +366,7 @@ OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD1);
uart_lld_serve_interrupt(&UARTD1);
OSAL_IRQ_EPILOGUE();
}
@ -421,7 +387,7 @@ OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD2);
uart_lld_serve_interrupt(&UARTD2);
OSAL_IRQ_EPILOGUE();
}
@ -442,7 +408,7 @@ OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD3);
uart_lld_serve_interrupt(&UARTD3);
OSAL_IRQ_EPILOGUE();
}
@ -463,7 +429,7 @@ OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD4);
uart_lld_serve_interrupt(&UARTD4);
OSAL_IRQ_EPILOGUE();
}
@ -484,7 +450,7 @@ OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD5);
uart_lld_serve_interrupt(&UARTD5);
OSAL_IRQ_EPILOGUE();
}
@ -505,7 +471,7 @@ OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD6);
uart_lld_serve_interrupt(&UARTD6);
OSAL_IRQ_EPILOGUE();
}
@ -526,7 +492,7 @@ OSAL_IRQ_HANDLER(STM32_UART7_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD7);
uart_lld_serve_interrupt(&UARTD7);
OSAL_IRQ_EPILOGUE();
}
@ -547,7 +513,7 @@ OSAL_IRQ_HANDLER(STM32_UART8_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD8);
uart_lld_serve_interrupt(&UARTD8);
OSAL_IRQ_EPILOGUE();
}
@ -1044,6 +1010,40 @@ size_t uart_lld_stop_receive(UARTDriver *uartp) {
return n;
}
/**
* @brief USART common service routine.
*
* @param[in] uartp pointer to the @p UARTDriver object
*/
void uart_lld_serve_interrupt(UARTDriver *uartp) {
uint32_t isr;
USART_TypeDef *u = uartp->usart;
uint32_t cr1 = u->CR1;
/* Reading and clearing status.*/
isr = u->ISR;
u->ICR = isr;
if (isr & (USART_ISR_LBDF | USART_ISR_ORE | USART_ISR_NE |
USART_ISR_FE | USART_ISR_PE)) {
_uart_rx_error_isr_code(uartp, translate_errors(isr));
}
if ((isr & USART_ISR_TC) && (cr1 & USART_CR1_TCIE)) {
/* TC interrupt disabled.*/
u->CR1 = cr1 & ~USART_CR1_TCIE;
/* End of transmission, a callback is generated.*/
_uart_tx2_isr_code(uartp);
}
/* Timeout interrupt sources are only checked if enabled in CR1.*/
if (((cr1 & USART_CR1_IDLEIE) && (isr & USART_ISR_IDLE)) ||
((cr1 & USART_CR1_RTOIE) && (isr & USART_ISR_RTOF))) {
_uart_timeout_isr_code(uartp);
}
}
#endif /* HAL_USE_UART */
/** @} */

1
os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h
View File

@ -826,6 +826,7 @@ extern "C" {
size_t uart_lld_stop_send(UARTDriver *uartp);
void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
size_t uart_lld_stop_receive(UARTDriver *uartp);
void uart_lld_serve_interrupt(UARTDriver *uartp);
#ifdef __cplusplus
}
#endif

2
os/hal/ports/STM32/STM32G0xx/stm32_dmamux.h
View File

@ -90,6 +90,8 @@
#define STM32_DMAMUX1_USART3_TX 55
#define STM32_DMAMUX1_USART4_RX 56
#define STM32_DMAMUX1_USART4_TX 57
#define STM32_DMAMUX1_UART4_RX STM32_DMAMUX1_USART4_RX /* Legacy. */
#define STM32_DMAMUX1_UART4_TX STM32_DMAMUX1_USART4_TX /* Legacy. */
#define STM32_DMAMUX1_UCPD1_RX 58
#define STM32_DMAMUX1_UCPD1_TX 59
#define STM32_DMAMUX1_UCPD2_RX 60