RTC. Minor documentation improvements.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3378 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -109,13 +109,15 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
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* @brief Enable access to registers and initialize RTC if BKP domain
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* @brief Enable access to registers and initialize RTC if BKP domain
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* was previously reseted.
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* was previously reseted.
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*
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*
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* @note: Cold start time of LSE oscillator on STM32 platform
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* takes about 3 seconds.
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*
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* @notapi
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* @notapi
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*/
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*/
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void rtc_lld_init(void){
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void rtc_lld_init(void){
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uint32_t preload = 0;
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uint32_t preload = 0;
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rccEnableBKPInterface(FALSE);
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rccEnableBKPInterface(FALSE);
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//RCC->APB1ENR |= (RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN);
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/* enable access to BKP registers */
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/* enable access to BKP registers */
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PWR->CR |= PWR_CR_DBP;
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PWR->CR |= PWR_CR_DBP;
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@ -124,8 +126,7 @@ void rtc_lld_init(void){
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#if STM32_RTC == STM32_RTC_LSE
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#if STM32_RTC == STM32_RTC_LSE
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if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){
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if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){
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RCC->BDCR |= RCC_BDCR_LSEON;
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RCC->BDCR |= RCC_BDCR_LSEON;
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/* Note: cold start time of LSE oscillator on STM32 is about 3 seconds. */
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while(!(RCC->BDCR & RCC_BDCR_LSERDY))
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while(!(RCC->BDCR & RCC_BDCR_LSERDY))
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;
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;
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RCC->BDCR |= RCC_BDCR_RTCEN;
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RCC->BDCR |= RCC_BDCR_RTCEN;
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