Fixed bug #818.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10116 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -726,7 +726,7 @@ void sd_lld_init(void) {
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#endif
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#if STM32_SERIAL_USE_LPUART1
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sdObjectInit(&LPSD1, NULL, notifylp1);
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sdObjectInit(&LPSD1);
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iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1);
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oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1);
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LPSD1.usart = LPUART1;
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@ -156,7 +156,11 @@ void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* PWR clock enable.*/
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RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
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#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
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RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
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#else
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RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
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#endif
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/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
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always enabled because it is the fall back clock when PLL the fails.
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@ -72,7 +72,7 @@
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* @{
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*/
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#define STM32_HSI16CLK 16000000 /**< High speed internal clock. */
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#define STM32_LSICLK 38000 /**< Low speed internal clock. */
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#define STM32_LSICLK 32000 /**< Low speed internal clock. */
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/** @} */
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/**
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@ -157,6 +157,7 @@
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- RT: Merged RT4.
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- NIL: Merged NIL2.
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- NIL: Added STM32F7 demo.
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- HAL: Fixed STM32L432 bringup issues (bug #818)(backported to 16.1.8).
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- HAL: Fixed DAC driver problem with API signature (bug #817)(backported
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to 16.1.8).
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- HAL: Fixed STM32 OTGv1 driver not serving interrupts for endpoints > 5
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