Fixed bug #818.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10116 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c

@@ -726,7 +726,7 @@ void sd_lld_init(void) {
 #endif
 
 #if STM32_SERIAL_USE_LPUART1
-  sdObjectInit(&LPSD1, NULL, notifylp1);
+  sdObjectInit(&LPSD1);
   iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1);
   oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1);
   LPSD1.usart = LPUART1;

os/hal/ports/STM32/STM32L4xx/hal_lld.c

@@ -156,7 +156,11 @@ void stm32_clock_init(void) {
 
 #if !STM32_NO_INIT
   /* PWR clock enable.*/
-  RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
+#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
+  RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
+#else
+  RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
+#endif
 
   /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
      always enabled because it is the fall back clock when PLL the fails.

os/hal/ports/STM32/STM32L4xx/hal_lld.h

@@ -72,7 +72,7 @@
  * @{
  */
 #define STM32_HSI16CLK          16000000    /**< High speed internal clock. */
-#define STM32_LSICLK            38000       /**< Low speed internal clock.  */
+#define STM32_LSICLK            32000       /**< Low speed internal clock.  */
 /** @} */
 
 /**

readme.txt

@@ -157,6 +157,7 @@
 - RT:  Merged RT4.
 - NIL: Merged NIL2.
 - NIL: Added STM32F7 demo.
+- HAL: Fixed STM32L432 bringup issues (bug #818)(backported to 16.1.8).
 - HAL: Fixed DAC driver problem with API signature (bug #817)(backported
        to 16.1.8).
 - HAL: Fixed STM32 OTGv1 driver not serving interrupts for endpoints > 5