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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5129 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-02-07 14:41:44 +00:00
parent 46ccb5a5f2
commit 8e5c02f32c
4 changed files with 16 additions and 28 deletions
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2
os/hal/platforms/SPC560BCxx/hal_lld.c
View File

@ -214,7 +214,7 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
*
* @notapi
*/
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
uint32_t mode;
ME.PCTL[n].R = pctl;

2
os/hal/platforms/SPC560Pxx/hal_lld.c
View File

@ -210,7 +210,7 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
*
* @notapi
*/
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
uint32_t mode;
ME.PCTL[n].R = pctl;

2
os/hal/platforms/SPC56ELxx/hal_lld.c
View File

@ -209,7 +209,7 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
*
* @notapi
*/
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
uint32_t mode;
ME.PCTL[n].R = pctl;

38
os/hal/platforms/SPC56ELxx/hal_lld.h
View File

@ -105,23 +105,11 @@
/** @} */
/**
* @name MC_CGM_AC3_SC register bits definitions
* @name FMPLLs register bits definitions
* @{
*/
#define SPC5_GCM_AC3_SC_SELCTL_MASK (15U << 24)
#define SPC5_GCM_AC3_SC_SELCTL(n) ((n) << 24)
#define SPC5_GCM_AC3_SC_SELCTL_IRC SPC5_GCM_AC3_SC_SELCTL(0)
#define SPC5_GCM_AC3_SC_SELCTL_XOSC SPC5_GCM_AC3_SC_SELCTL(1)
/** @} */
/**
* @name MC_CGM_AC4_SC register bits definitions
* @{
*/
#define SPC5_GCM_AC4_SC_SELCTL_MASK (15U << 24)
#define SPC5_GCM_AC4_SC_SELCTL(n) ((n) << 24)
#define SPC5_GCM_AC4_SC_SELCTL_IRC SPC5_GCM_AC4_SC_SELCTL(0)
#define SPC5_GCM_AC4_SC_SELCTL_XOSC SPC5_GCM_AC4_SC_SELCTL(1)
#define SPC5_FMPLL_SRC_IRC (0 << 24)
#define SPC5_FMPLL_SRC_XOSC (1 << 24)
/** @} */
/**
@ -251,8 +239,8 @@
/**
* @brief FMPLL0 Clock source.
*/
#if !defined(SPC5_FMPLL0_CLOCK_SOURCE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_CLOCK_SOURCE SPC5_GCM_AC3_SC_SELCTL_XOSC
#if !defined(SPC5_FMPLL0_CLK_SRC) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
#endif
/**
@ -282,8 +270,8 @@
/**
* @brief FMPLL1 Clock source.
*/
#if !defined(SPC5_FMPLL1_CLOCK_SOURCE) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_CLOCK_SOURCE SPC5_GCM_AC4_SC_SELCTL_XOSC
#if !defined(SPC5_FMPLL1_CLK_SRC) || defined(__DOXYGEN__)
#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC
#endif
/**
@ -619,12 +607,12 @@
#endif
/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/
#if SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_IRC
#if SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_IRC
#define SPC5_FMPLL0_INPUT_CLK SPC5_IRC_CLK
#elif SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_XOSC
#elif SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_XOSC
#define SPC5_FMPLL0_INPUT_CLK SPC5_XOSC_CLK
#else
#error "invalid SPC5_FMPLL0_CLOCK_SOURCE value specified"
#error "invalid SPC5_FMPLL0_CLK_SRC value specified"
#endif
/* Check on SPC5_FMPLL0_IDF_VALUE.*/
@ -674,12 +662,12 @@
#endif
/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/
#if SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_IRC
#if SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_IRC
#define SPC5_FMPLL1_INPUT_CLK SPC5_IRC_CLK
#elif SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_XOSC
#elif SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_XOSC
#define SPC5_FMPLL1_INPUT_CLK SPC5_XOSC_CLK
#else
#error "invalid SPC5_FMPLL1_CLOCK_SOURCE value specified"
#error "invalid SPC5_FMPLL1_CLK_SRC value specified"
#endif
/* Check on SPC5_FMPLL1_IDF_VALUE.*/