From 8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 14 Jun 2013 14:25:39 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5849 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC560P-GCC/mcuconf.h | 91 +++++++++++ demos/PPC-SPC563M-GCC/mcuconf.h | 4 - demos/PPC-SPC564A-GCC/Makefile | 2 +- demos/PPC-SPC564A-GCC/mcuconf.h | 36 +++-- demos/PPC-SPC56EL-GCC/mcuconf.h | 150 +++++++++++++++--- os/hal/platforms/SPC560Pxx/spc560p_registry.h | 15 ++ os/hal/platforms/SPC564Axx/spc564a_registry.h | 18 +-- os/hal/platforms/SPC56ELxx/spc56el_registry.h | 9 ++ testhal/SPC560Dxx/SPI/UDE/debug .wsx | 4 +- testhal/SPC560Dxx/SPI/main.c | 2 +- testhal/SPC560Pxx/PWM-ICU/mcuconf.h | 92 ++++++++++- testhal/SPC560Pxx/SPI/mcuconf.h | 22 ++- testhal/SPC563Mxx/ADC/mcuconf.h | 4 - testhal/SPC563Mxx/SPI/mcuconf.h | 4 - testhal/SPC564Axx/SPI/mcuconf.h | 30 ++-- testhal/SPC56ELxx/PWM-ICU/mcuconf.h | 63 +++++++- testhal/SPC56ELxx/SPI/main.c | 2 +- testhal/SPC56ELxx/SPI/mcuconf.h | 18 ++- 18 files changed, 485 insertions(+), 81 deletions(-) diff --git a/demos/PPC-SPC560P-GCC/mcuconf.h b/demos/PPC-SPC560P-GCC/mcuconf.h index f5e52b7f7..f30b63d8a 100644 --- a/demos/PPC-SPC560P-GCC/mcuconf.h +++ b/demos/PPC-SPC560P-GCC/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC560Pxx_MCUCONF @@ -147,6 +149,15 @@ #define SPC5_PIT0_IRQ_PRIORITY 4 #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * SERIAL driver system settings. */ @@ -162,3 +173,83 @@ SPC5_ME_PCTL_LP(2)) #define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 TRUE +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_USE_DSPI3 TRUE +#define SPC5_SPI_USE_DSPI4 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/demos/PPC-SPC563M-GCC/mcuconf.h b/demos/PPC-SPC563M-GCC/mcuconf.h index 28a5790f5..76898ad35 100644 --- a/demos/PPC-SPC563M-GCC/mcuconf.h +++ b/demos/PPC-SPC563M-GCC/mcuconf.h @@ -58,10 +58,6 @@ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 #define SPC5_EDMA_GROUP1_PRIORITIES \ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define SPC5_EDMA_GROUP2_PRIORITIES \ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define SPC5_EDMA_GROUP3_PRIORITIES \ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 #define SPC5_EDMA_ERROR_IRQ_PRIO 2 #define SPC5_EDMA_ERROR_HANDLER() chSysHalt() diff --git a/demos/PPC-SPC564A-GCC/Makefile b/demos/PPC-SPC564A-GCC/Makefile index d79a29ab1..9b51a6845 100644 --- a/demos/PPC-SPC564A-GCC/Makefile +++ b/demos/PPC-SPC564A-GCC/Makefile @@ -59,7 +59,7 @@ include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/SPC564A80.ld +LDSCRIPT= $(PORTLD)/SPC564A70.ld # C sources here. CSRC = $(PORTSRC) \ diff --git a/demos/PPC-SPC564A-GCC/mcuconf.h b/demos/PPC-SPC564A-GCC/mcuconf.h index 0683912f9..dc54d3d88 100644 --- a/demos/PPC-SPC564A-GCC/mcuconf.h +++ b/demos/PPC-SPC564A-GCC/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC564Axx_MCUCONF @@ -44,6 +46,25 @@ BIUCR_PFLIM_ON_MISS | \ BIUCR_BFEN) +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * ADC driver settings. */ @@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE #define SPC5_ADC_USE_ADC1_Q4 FALSE #define SPC5_ADC_USE_ADC1_Q5 FALSE -#define SPC5_ADC_FIFO0_DMA_PRIO 12 -#define SPC5_ADC_FIFO1_DMA_PRIO 12 -#define SPC5_ADC_FIFO2_DMA_PRIO 12 -#define SPC5_ADC_FIFO3_DMA_PRIO 12 -#define SPC5_ADC_FIFO4_DMA_PRIO 12 -#define SPC5_ADC_FIFO5_DMA_PRIO 12 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 @@ -88,9 +103,9 @@ /* * SPI driver system settings. */ -#define SPC5_SPI_USE_DSPI1 TRUE -#define SPC5_SPI_USE_DSPI2 TRUE -#define SPC5_SPI_USE_DSPI3 TRUE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_USE_DSPI3 FALSE #define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ SPC5_MCR_PCSIS1 | \ SPC5_MCR_PCSIS2 | \ @@ -115,9 +130,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 -#define SPC5_SPI_DSPI3_DMA_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 diff --git a/demos/PPC-SPC56EL-GCC/mcuconf.h b/demos/PPC-SPC56EL-GCC/mcuconf.h index 96f8c6b86..f90a80578 100644 --- a/demos/PPC-SPC56EL-GCC/mcuconf.h +++ b/demos/PPC-SPC56EL-GCC/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC56ELxx_MCUCONF @@ -41,9 +43,9 @@ #define SPC5_FMPLL1_IDF_VALUE 5 #define SPC5_FMPLL1_NDIV_VALUE 60 #define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 -#define SPC5_SYSCLK_DIVIDER_VALUE 1 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 #define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 -#define SPC5_MCONTROL_DIVIDER_VALUE 2 +#define SPC5_MCONTROL_DIVIDER_VALUE 15 #define SPC5_SWG_DIVIDER_VALUE 2 #define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 #define SPC5_FLEXRAY_DIVIDER_VALUE 2 @@ -104,18 +106,6 @@ SPC5_ME_MC_PLL1ON | \ SPC5_ME_MC_FLAON_NORMAL | \ SPC5_ME_MC_MVRON) -#define SPC5_ME_RUN_PC0_BITS 0 -#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \ - SPC5_ME_RUN_PC_DRUN | \ - SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) -#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ - SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) #define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ SPC5_ME_RUN_PC_RUN1 | \ SPC5_ME_RUN_PC_RUN2 | \ @@ -136,11 +126,6 @@ SPC5_ME_RUN_PC_RUN1 | \ SPC5_ME_RUN_PC_RUN2 | \ SPC5_ME_RUN_PC_RUN3) -#define SPC5_ME_LP_PC0_BITS 0 -#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ - SPC5_ME_LP_PC_STOP0) -#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) -#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) #define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ SPC5_ME_LP_PC_STOP0) #define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ @@ -151,6 +136,15 @@ SPC5_ME_LP_PC_STOP0) #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * SERIAL driver system settings. */ @@ -166,3 +160,121 @@ SPC5_ME_PCTL_LP(2)) #define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ SPC5_ME_PCTL_LP(0)) + +/* + * PWM driver system settings. + */ +#define SPC5_PWM_USE_SMOD0 FALSE +#define SPC5_PWM_USE_SMOD1 FALSE +#define SPC5_PWM_USE_SMOD2 FALSE +#define SPC5_PWM_USE_SMOD3 FALSE +#define SPC5_PWM_SMOD0_PRIORITY 7 +#define SPC5_PWM_SMOD1_PRIORITY 7 +#define SPC5_PWM_SMOD2_PRIORITY 7 +#define SPC5_PWM_SMOD3_PRIORITY 7 +#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_PWM_USE_SMOD4 FALSE +#define SPC5_PWM_USE_SMOD5 FALSE +#define SPC5_PWM_USE_SMOD6 FALSE +#define SPC5_PWM_USE_SMOD7 FALSE +#define SPC5_PWM_SMOD4_PRIORITY 7 +#define SPC5_PWM_SMOD5_PRIORITY 7 +#define SPC5_PWM_SMOD6_PRIORITY 7 +#define SPC5_PWM_SMOD7_PRIORITY 7 +#define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * ICU driver system settings. + */ +#define SPC5_ICU_USE_SMOD0 FALSE +#define SPC5_ICU_USE_SMOD1 FALSE +#define SPC5_ICU_USE_SMOD2 FALSE +#define SPC5_ICU_USE_SMOD3 FALSE +#define SPC5_ICU_USE_SMOD4 FALSE +#define SPC5_ICU_USE_SMOD5 FALSE +#define SPC5_ICU_ETIMER0_PRIORITY 7 +#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD6 FALSE +#define SPC5_ICU_USE_SMOD7 FALSE +#define SPC5_ICU_USE_SMOD8 FALSE +#define SPC5_ICU_USE_SMOD9 FALSE +#define SPC5_ICU_USE_SMOD10 FALSE +#define SPC5_ICU_USE_SMOD11 FALSE +#define SPC5_ICU_ETIMER1_PRIORITY 7 +#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_SMOD12 FALSE +#define SPC5_ICU_USE_SMOD13 FALSE +#define SPC5_ICU_USE_SMOD14 FALSE +#define SPC5_ICU_USE_SMOD15 FALSE +#define SPC5_ICU_USE_SMOD16 FALSE +#define SPC5_ICU_USE_SMOD17 FALSE +#define SPC5_ICU_ETIMER2_PRIORITY 7 +#define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 54d38e0f6..4f528056e 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -93,6 +93,15 @@ #define SPC5_DSPI0_PCTL 4 #define SPC5_DSPI1_PCTL 5 #define SPC5_DSPI2_PCTL 6 +#define SPC5_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_DSPI1_RX_DMA_CH_ID 9 +#define SPC5_DSPI2_TX1_DMA_CH_ID 10 +#define SPC5_DSPI2_TX2_DMA_CH_ID 11 +#define SPC5_DSPI2_RX_DMA_CH_ID 12 #define SPC5_DSPI0_TX1_DMA_DEV_ID 1 #define SPC5_DSPI0_TX2_DMA_DEV_ID 0 #define SPC5_DSPI0_RX_DMA_DEV_ID 2 @@ -124,6 +133,9 @@ #if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_) #define SPC5_HAS_DSPI3 TRUE #define SPC5_DSPI3_PCTL 7 +#define SPC5_DSPI3_TX1_DMA_CH_ID 13 +#define SPC5_DSPI3_TX2_DMA_CH_ID 14 +#define SPC5_DSPI3_RX_DMA_CH_ID 15 #define SPC5_DSPI3_TX1_DMA_DEV_ID 7 #define SPC5_DSPI3_TX2_DMA_DEV_ID 0 #define SPC5_DSPI3_RX_DMA_DEV_ID 8 @@ -140,6 +152,9 @@ #if defined(_SPC560PXX_LARGE_) #define SPC5_HAS_DSPI4 TRUE #define SPC5_DSPI4_PCTL 8 +#define SPC5_DSPI4_TX1_DMA_CH_ID 1 +#define SPC5_DSPI4_TX2_DMA_CH_ID 2 +#define SPC5_DSPI4_RX_DMA_CH_ID 3 #define SPC5_DSPI4_TX1_DMA_DEV_ID 15 #define SPC5_DSPI4_TX2_DMA_DEV_ID 0 #define SPC5_DSPI4_RX_DMA_DEV_ID 21 diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index bcdd6753b..ec584abdf 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -54,15 +54,15 @@ #define SPC5_HAS_DSPI3 TRUE #define SPC5_HAS_DSPI4 FALSE #define SPC5_DSPI_FIFO_DEPTH 16 -#define SPC5_DSPI1_TX1_DMA_DEV_ID 12 -#define SPC5_DSPI1_TX2_DMA_DEV_ID 24 -#define SPC5_DSPI1_RX_DMA_DEV_ID 13 -#define SPC5_DSPI2_TX1_DMA_DEV_ID 14 -#define SPC5_DSPI2_TX2_DMA_DEV_ID 25 -#define SPC5_DSPI2_RX_DMA_DEV_ID 15 -#define SPC5_DSPI3_TX1_DMA_DEV_ID 16 -#define SPC5_DSPI3_TX2_DMA_DEV_ID 26 -#define SPC5_DSPI3_RX_DMA_DEV_ID 17 +#define SPC5_DSPI1_TX1_DMA_CH_ID 12 +#define SPC5_DSPI1_TX2_DMA_CH_ID 24 +#define SPC5_DSPI1_RX_DMA_CH_ID 13 +#define SPC5_DSPI2_TX1_DMA_CH_ID 14 +#define SPC5_DSPI2_TX2_DMA_CH_ID 25 +#define SPC5_DSPI2_RX_DMA_CH_ID 15 +#define SPC5_DSPI3_TX1_DMA_CH_ID 16 +#define SPC5_DSPI3_TX2_DMA_CH_ID 26 +#define SPC5_DSPI3_RX_DMA_CH_ID 17 #define SPC5_DSPI1_EOQF_HANDLER vector132 #define SPC5_DSPI1_EOQF_NUMBER 132 #define SPC5_DSPI1_TFFF_HANDLER vector133 diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h index 83fdab87c..6ab0ae2e2 100644 --- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -48,6 +48,15 @@ #define SPC5_DSPI0_PCTL 4 #define SPC5_DSPI1_PCTL 5 #define SPC5_DSPI2_PCTL 6 +#define SPC5_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_DSPI1_RX_DMA_CH_ID 9 +#define SPC5_DSPI2_TX1_DMA_CH_ID 10 +#define SPC5_DSPI2_TX2_DMA_CH_ID 11 +#define SPC5_DSPI2_RX_DMA_CH_ID 12 #define SPC5_DSPI0_TX1_DMA_DEV_ID 1 #define SPC5_DSPI0_TX2_DMA_DEV_ID 0 #define SPC5_DSPI0_RX_DMA_DEV_ID 2 diff --git a/testhal/SPC560Dxx/SPI/UDE/debug .wsx b/testhal/SPC560Dxx/SPI/UDE/debug .wsx index b85ffdc0a..8a1dc048c 100644 --- a/testhal/SPC560Dxx/SPI/UDE/debug .wsx +++ b/testhal/SPC560Dxx/SPI/UDE/debug .wsx @@ -1,6 +1,6 @@ - debug .wsx001vQTv/gAAAQAXAAIA6AkIAAAABAAAAAAAPwAAAAAAAAAEAAAAAgAAAAAAAAAAAAAAAAAAAA==4.019.11.2012 16:18:08:999MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPHHAAAAAAPBAAAAAADGFAAAAABCDAAAAAFalseTrue1416801050593930FalseFalse1000000000000000UDEStatusBarFor Help, press F10594191105964705939959398593975940359401594065940200FalseFalse0000000000CUDEDockBar05942230911000FalseFalse0000000000CUDEDockBar05942030910000FalseFalse0000000000CUDEDockBar059647381True59419-1-11251268196-21474836480908FalseFalse1000000381271252277651106144014947UDEMDIMenuBarMenu bar0Menu barBAAAAAAIAACAAAAAAIAADAAAAAAIAAEAAAAAAIAAFAAAAAAIAAGAAAAAAIAAHAAAAAAIAAIAAAAAAIAAJAAAAAAIAAKAAAAAAIAA5939850326True050326614568196-21474836480780FalseFalse1562500111300006144014946CUdeCustomToolBarEdit0Edit2DCBOAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAACCBOAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAFCBOAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAIABOAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAA5939761426True061426794568196-21474836480780FalseFalse1562500180300006144014946CUdeCustomToolBarFile0File3AHHBAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAABHHBAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAACHHBAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAADHHBAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAEHHBAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAFHHBAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAOKHBAAAAAABAAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAA5940379426True079426928568196-21474836481181049967780FalseFalse3125000134300006144014946CUdeCustomToolBarConfig0Config2GJHBAAAAAADAAAAAAADBGGJPINFFOGHPIEPKKCPFOMBDBNDAKPAAAAAAAAPPPPPPPPAAAAAAAAMMHBAAAAAAOPAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAANMHBAAAAAAAABAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAAFNHBAAAAAAGAAAAAAAKBDLFIMBFCNFHJBEGJFDMJNFCMOIPKHNAAAAAAAAPPPPPPPPAAAAAAAAINHBAAAAAACBAAAAAADBGGJPINFFOGHPIEPKKCPFOMBDBNDAKPAAAAAAAAPPPPPPPPAAAAAAAA5940192826True0928261407568196-2147483648151587341780FalseFalse6250000479300006144014946CUdeCustomToolBarViews0Views6JJHBAAAAAAFBAAAAAADBGGJPINFFOGHPIEPKKCPFOMBDBNDAKPAAAAAAAAPPPPPPPPAAAAAAAAKJHBAAAAAAPAAAAAAADBGGJPINFFOGHPIEPKKCPFOMBDBNDAKPAAAAAAAAPPPPPPPPAAAAAAAAMJHBAAAAAAGBAAAAAADBGGJPINFFOGHPIEPKKCPFOMBDBNDAKPAAAAAAAAPPPPPPPPAAAAAAAANKHBAAAAAAAAAAAAAAAGKBFNONHLAOENBBBJCBAABADAJECGGLAAAAAAAAPPPPPPPPAAAAAAAAALHBAAAAAAKAAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAACLHBAAAAAAMFAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAADLHBAAAAAAKFAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAAFLHBAAAAAANCAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAAGLHBAAAAAAMDAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAAHLHBAAAAAAGEAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAAAMHBAAAAAAKAAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAABMHBAAAAAAEBAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAACMHBAAAAAAJBAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAADMHBAAAAAALBAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAAEMHBAAAAAAAFAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAAFMHBAAAAAAICAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAAHMHBAAAAAANEEAAAAAJEOEILFFBLMIPBEEPLLMEDEOPKHPBGJHAAAAAAAAPPPPPPPPAAAAAAAAIMHBAAAAAAGFEAAAAAJEOEILFFBLMIPBEEPLLMEDEOPKHPBGJHAAAAAAAAPPPPPPPPAAAAAAAAJMHBAAAAAAAGEAAAAAJEOEILFFBLMIPBEEPLLMEDEOPKHPBGJHAAAAAAAAPPPPPPPPAAAAAAAALMHBAAAAAAGEAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAA59406140726True01407261653568196-21474836480780FalseFalse12500000246300006144014946CUdeCustomToolBarMacro0Macro2DKHBAAAAAALDAAAAAAGDHJMPFPDOOJLAGELLAIHGBMMEFJBIPLAAAAAAAAPPPPPPPPAAAAAAAAEKHBAAAAAAAEAAAAAAGDHJMPFPDOOJLAGELLAIHGBMMEFJBIPLAAAAAAAAPPPPPPPPAAAAAAAAGKHBAAAAAAMDAAAAAAGDHJMPFPDOOJLAGELLAIHGBMMEFJBIPLAAAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAMKHBAAAACAGJAAAAAAAAAANMAJBFNENHHACJPEILAJFEFEECLCDPKCBAAAAAAAKAAAAAAANAAAAAAAFFEEFEHFPGCHLGDHAHBGDGFGAA5939926504True59419-126503568196-21474836480780FalseFalse25000050430504301239006144014946CUdeCustomToolBarDebug0Debug5BLHBAAAAAAIBAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAAELHBAAAAAAOFAAAAAALGLJALHCJPMBOILEPIDADGENFBIDFOCNAAAAAAAAPPPPPPPPAAAAAAAAILHBAAAAAAHAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAJLHBAAAAAAJAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAKLHBAAAAAAKAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAALLHBAAAAAALAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAMLHBAAAAAAIAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAANLHBAAAAAABCDAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAOLHBAAAAAANAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAPLHBAAAAAAMAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAANHBAAAAAADAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAABNHBAAAAAAGAAAAAAABINLNCJGPDKECNBBCLNMAAAKECHFPLPAAAAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPPPPPPPPAAAAAAAACNHBAAAACAKKAAAAAAAAAADHHMLHLPEKIIOMOEJLGLBHJIBGLAHAFDBAAAAAAADAAAAAAAFAAAAAAADEPGCHFGAAENHBAAAAAADAAAAAAAKBDLFIMBFCNFHJBEGJFDMJNFCMOIPKHNAAAAAAAAPPPPPPPPAAAAAAAA59402165326True01653261795568196-21474836480780FalseFalse50000000142300006144014946CUdeCustomToolBarTools0ToolsDNHBAAAACAEGAAAAAAAAAAGEAOMHHDMDCIFAKEIIICDBCMNFEDNFHHBAAAAAAAGAAAAAAAFAAAAAAADEPGCHFGAAHNHBAAAAAABOAAAAAAKEMNADOLNFNPBMHEJJNEMIOMIMCHOAOGAAAAAAAAPPPPPPPPAAAAAAAA911015True594221512521554-214748364803889FalseFalse1000000300180125115030018006144014948CTabWndControlBarTab Window Bar 00-1FalseUDEDesktop Standard BarsTab Window Bar 0UDEDesktop0015019100False00True000004-214748364803889FalseFalse100000030018030018015018006144014948CUdeProjectWspBarProject Workspace Bar0-1FalseUDEDesktop Standard BarsProject Workspace BarUDEDesktop0001TrueTrueFalse21.11.2012 14:43:52:278487782411WorkspaceManager11019.11.2012 16:28:52:057MgAAAA==AQAAAA==ZAAAAA==AQAAAA==lgAAAA==AQAAAA==6AMAAA==AQAAAA==139011201WorkspaceManager110000110010\\napnt002.nap.st.com\NAPPRT0001000WorkspaceManagerWorkspaceManager01Core1Target0.Controller0.CoreTarget0.Controller0.Core102200701438312957781279740NormalfalseTop1271falseBottom0000falsefalse00DockPaneltrue417falseLeft0000falsefalse00DockPanelfalse417falseLeft0000falsefalse10DockPanelfalse0falseTop0000falsefalse0-1TabbedDocumenttrue417falseLeft0000falsefalse20DockPaneltrue417falseLeft0000falsefalse30DockPanelfalsetrue556false200false200true200true100truetrue0012797400127924Platform Main Menufalsetrue4249525Edit ToolbarfalsetrueUDE_Workspace_0x1779trueCutImagetrueUDE_Workspace_0x177AtrueCopyImagetrueUDE_Workspace_0x177BtruePasteImagetrue992427625Macro ToolbarfalsetrueUDE_0x3B_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueRun MacroImagetrueUDE_0x40_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueDebug MacroImagetrueUDE_0x3_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueBreak MacroImagetrueUDE_0x3C_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueReload MacroImagetrueUDE_Ctrl_{4D5190CD-077D-4F92-B890-4545242BF32A}_UDEWorkspacetrueImageAndTextfalse3752421025File ToolbarfalsetrueUDE_Workspace_0x1770trueNew WorkspaceImagetrueUDE_Workspace_0x1771trueOpen workspaceImagetrueUDE_Workspace_0x1772trueSave workspace asImagetrueUDE_Workspace_0x1773trueSave workspaceImagetrueUDE_Workspace_0x1774trueClose workspaceImagetrueUDE_Workspace_0x177FtrueExport view contentImagetrueUDE_Workspace_0x1778truePrintImagetrueUDE_0x1_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueLoad ProgramImagetrue5852444025Views ToolbarfalsetrueUDE_0x4_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget BrowserImagetrueUDE_0x15_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueDiagnostic Message ViewerImagetrueUDE_0xF_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueConsoleImagetrueUDE_0x0_{DED51A60-E0B7-11D4-9112-0001034962B6}trueCPU WindowImagetrueUDE_0x1E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueExplore SymbolsImagetrueUDE_0xA_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueProgramImagetrueUDE_0x5C_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueSingle Program WindowImagetrueUDE_0x5A_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueDisassembly WindowImagetrueUDE_0x2D_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow Special Function RegisterImagetrueUDE_0x3C_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueLocalsImagetrueUDE_0x46_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueWatchImagetrueUDE_0xA_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueSimulated I/OImagetrueUDE_0x14_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueUDE HTMLImagetrueUDE_0x19_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueArray ChartImagetrueUDE_0x1B_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueTime Traced Signal ChartImagetrueUDE_0x50_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueIP Trace ProfilingImagetrueUDE_0x28_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueMemoryImagetrueUDE_0x46_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueCall StackImagetrue34950925Debug ToolbarfalsetrueUDE_0x18_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow IPImagetrueUDE_0x5E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow program codeImagetrueUDE_0x7_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStart ProgramImagetrueUDE_0x9_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep OverImagetrueUDE_0xA_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep IntoImagetrueUDE_0xB_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep OutImagetrueUDE_0x8_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRun CursorImagetrueUDE_0x321_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreak ProgramImagetrueUDE_0xD_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueResetImagetrueUDE_0xC_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRestart ProgramImagetrueUDE_0x3_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreakpointsImagetrueUDE_0x6_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueToggle BreakImagetrueUDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_CoretrueImageAndTextfalseUDE_0x3_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueTrigger setupImagetrue5124914125Config ToolbarfalsetrueUDE_0x3_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget ConfigurationImagetrueUDE_0xFE_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueConnect TargetImagetrueUDE_0x100_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueDisconnect TargetImagetrueUDE_0x6_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueSetup Target InterfaceImagetrueUDE_0x12_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueMCU Run ControlImagetrue6534915125Tools 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ProgramImagetrueUDE_0xD_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueResetImagetrueUDE_0xC_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRestart ProgramImagetrueUDE_0x3_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreakpointsImagetrueUDE_0x6_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueToggle BreakImagetrueUDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_CoretrueImageAndTextfalseUDE_0x3_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueTrigger setupImagetrue5124914125Config ToolbarfalsetrueUDE_0x3_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget ConfigurationImagetrueUDE_0xFE_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueConnect TargetImagetrueUDE_0x100_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueDisconnect TargetImagetrueUDE_0x6_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueSetup Target InterfaceImagetrueUDE_0x12_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueMCU Run ControlImagetrue6534915125Tools ToolbarfalsetrueUDE_Ctrl_{377CE046-823C-4A05-8828-13C25D345D77}_CoretrueImageAndTextfalseUDE_0xE1_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueExecution Time SetupImagetrue01002625Show Toolbarfalsefalse02002625Window Toolbarfalsefalse02252625Workspace Toolbarfalsefalse02752625Help Toolbarfalsefalse071712792300127923Platform Status Barfalsetrue07406431279740643..\..\..\..\..\Program Files\pls\UDE 4.0\StdLibrary.mso{866f82d3-fac5-43cd-8a82-0af01e46e2c5}669,1006,350,6610..\..\..\..\..\Documents and Settings\disiriog\My Documents\pls\UDE 4.0The script contains a collection of macros to save memory content into different file formats and fill target memory rangesV:\UDE\AddOns\Macro\MacroLibrary\StdMacros1.dsm' ' $Header: /Ude/AddOns/Macro/MacroLibrary/StdMacros.dsm 3 30.04.04 9:34 Weisses $ '_______________________________________________________ @@ -270,4 +270,4 @@ Sub FillDWord(ParameterObj) debugger.Write Address,udearrayobj Next -End Sub63VBScript24.11.2006 14:43:20:0001WS_CORE_DUOMacro_14_06_13_14_33_25_010Execute UnAss ..Macro UnAssExecute macro UnAss0210Execute SaveHEX ..Macro SaveHEXExecute macro SaveHEX0210Execute FillByte ..Macro FillByteExecute macro FillByte0110Execute FillWord ..Macro FillWordExecute macro FillWord0110Execute FillDWord ..Macro FillDWordExecute macro FillDWord0150121.11.2012 14:17:23:6457782750Target0.Controller0.Core1020.11.2012 16:19:48:3447782640Target0.Controller0.Core11021.11.2012 12:22:49:573..\main.c1,0,0,353,10940017372830Target0.Controller0.Core1114.06.2013 14:25:28:960..\..\..\os\hal\src\hal.c1,49,63,402,11570017372860Target0.Controller0.Core110214.06.2013 14:27:53:872..\..\..\os\hal\platforms\SPC5xx\SIUL_v1\pal_lld.c7372880Target0.Controller0.Core1121.11.2012 14:44:22:506..\..\..\os\kernel\src\chsys.c7372860Target0.Controller0.Core13121.11.2012 14:14:46:537AwAAAA==AQAAAA==kAAAAA==YAAAAA==TgAAAA==jQAAAA==TgAAAA==jQAAAA==TgAAAA==jgAAAA==AAAAAA==AAAAAA==AAAAAA==AAAAAA==7782520Target0.Controller0.Core10021.11.2012 14:10:10:4245380360007372850Target0.Controller0.Core10000000013.06.2013 16:10:26:035000013.06.2013 16:20:21:757<_ExtentX type="bin" size="8">UEoAAA==<_ExtentY type="bin" size="8">gysAAA==<_StockProps type="bin" size="8">AAAAAA==AgAAAA==UABDAAAAUABDAAAAAAAAAA==YAAAAA==RgB1AG4AYwB0AGkAbwBuAAAARgB1AG4AYwB0AGkAbwBuAAAAAAAAAA==QAYAAA==7372890Target0.Controller0.Core1OFF0..\build11..\build\ch.elf<Section>C:\ChibiStudio\chibios\os\kernel\src\chevents.c1Software;enabled;0;disabled;'main {C:\ChibiStudio\chibios\demos\PPC-SPC560D-GCC\main.c} .164';main.c;1;0;;$disabled; ;disabled; ;100111100verify.txt0000000004..\..\..\..\os\ports\GCC\PPC\chcore.c..\..\..\..\os\kernel\src\chsys.c..\..\..\..\os\hal\platforms\SPC5xx\DSPI_v1\spi_lld.c..\main.cstm_xpc560b_spc560d40_minimodule_debug_jtag.cfg14.06.2013 14:33:24:999 +End Sub63VBScript24.11.2006 14:43:20:0001WS_CORE_DUOMacro_14_06_13_14_48_10_010Execute UnAss ..Macro UnAssExecute macro UnAss0210Execute SaveHEX ..Macro SaveHEXExecute macro SaveHEX0210Execute FillByte ..Macro FillByteExecute macro FillByte0110Execute FillWord ..Macro FillWordExecute macro FillWord0110Execute FillDWord ..Macro FillDWordExecute macro FillDWord0150121.11.2012 14:17:23:6457782750Target0.Controller0.Core1020.11.2012 16:19:48:3447782640Target0.Controller0.Core11021.11.2012 12:22:49:573..\main.c1,0,0,353,10940017372830Target0.Controller0.Core1114.06.2013 14:25:28:960..\..\..\os\hal\src\hal.c1,49,63,402,11570017372860Target0.Controller0.Core110214.06.2013 14:27:53:872..\..\..\os\hal\platforms\SPC5xx\SIUL_v1\pal_lld.c7372880Target0.Controller0.Core1121.11.2012 14:44:22:506..\..\..\os\kernel\src\chsys.c7372860Target0.Controller0.Core13121.11.2012 14:14:46:537AwAAAA==AQAAAA==kAAAAA==YAAAAA==TgAAAA==jQAAAA==TgAAAA==jQAAAA==TgAAAA==jgAAAA==AAAAAA==AAAAAA==AAAAAA==AAAAAA==7782520Target0.Controller0.Core10021.11.2012 14:10:10:4245380360007372850Target0.Controller0.Core10000000013.06.2013 16:10:26:035000013.06.2013 16:20:21:757<_ExtentX type="bin" size="8">UEoAAA==<_ExtentY type="bin" size="8">gysAAA==<_StockProps type="bin" size="8">AAAAAA==AgAAAA==UABDAAAAUABDAAAAAAAAAA==YAAAAA==RgB1AG4AYwB0AGkAbwBuAAAARgB1AG4AYwB0AGkAbwBuAAAAAAAAAA==QAYAAA==7372890Target0.Controller0.Core1OFF0..\build11..\build\ch.elf<Section>C:\ChibiStudio\chibios\os\kernel\src\chevents.c1Software;enabled;0;disabled;'main {C:\ChibiStudio\chibios\demos\PPC-SPC560D-GCC\main.c} .164';main.c;1;0;;$disabled; ;disabled; ;100111100verify.txt0000000004..\..\..\..\os\ports\GCC\PPC\chcore.c..\..\..\..\os\kernel\src\chsys.c..\..\..\..\os\hal\platforms\SPC5xx\DSPI_v1\spi_lld.c..\main.cstm_xpc560b_spc560d40_minimodule_debug_jtag.cfg14.06.2013 14:48:09:999 diff --git a/testhal/SPC560Dxx/SPI/main.c b/testhal/SPC560Dxx/SPI/main.c index 3aa7f2d7a..f6aa96abe 100644 --- a/testhal/SPC560Dxx/SPI/main.c +++ b/testhal/SPC560Dxx/SPI/main.c @@ -116,7 +116,7 @@ int main(void) { SIU.PCR[14].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ SIU.PCR[13].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ SIU.PCR[15].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */ - SIU.PCR[35].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[1] */ + SIU.PCR[28].R = PAL_MODE_OUTPUT_ALTERNATE(3); /* CS[1] */ /* Testing sending and receiving at the same time.*/ spiExchange(&SPID1, 4, txbuf, rxbuf); diff --git a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h index b396aece5..ae770ef86 100644 --- a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h +++ b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC560Pxx_MCUCONF @@ -148,7 +150,16 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() /* - * PWM driver system settings. + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * Serial driver system settings. */ #define SPC5_SERIAL_USE_LINFLEX0 TRUE #define SPC5_SERIAL_USE_LINFLEX1 TRUE @@ -206,3 +217,82 @@ #define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ SPC5_ME_PCTL_LP(0)) +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_USE_DSPI3 FALSE +#define SPC5_SPI_USE_DSPI4 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Pxx/SPI/mcuconf.h b/testhal/SPC560Pxx/SPI/mcuconf.h index 940185854..ba5720366 100644 --- a/testhal/SPC560Pxx/SPI/mcuconf.h +++ b/testhal/SPC560Pxx/SPI/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC560Pxx_MCUCONF @@ -148,7 +150,16 @@ #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() /* - * PWM driver system settings. + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * Serial driver system settings. */ #define SPC5_SERIAL_USE_LINFLEX0 TRUE #define SPC5_SERIAL_USE_LINFLEX1 TRUE @@ -166,7 +177,7 @@ /* * PWM driver system settings. */ -#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD0 FALSE #define SPC5_PWM_USE_SMOD1 FALSE #define SPC5_PWM_USE_SMOD2 FALSE #define SPC5_PWM_USE_SMOD3 FALSE @@ -182,7 +193,7 @@ /* * ICU driver system settings. */ -#define SPC5_ICU_USE_SMOD0 TRUE +#define SPC5_ICU_USE_SMOD0 FALSE #define SPC5_ICU_USE_SMOD1 FALSE #define SPC5_ICU_USE_SMOD2 FALSE #define SPC5_ICU_USE_SMOD3 FALSE @@ -254,11 +265,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI0_DMA_PRIO 10 -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 -#define SPC5_SPI_DSPI3_DMA_PRIO 10 -#define SPC5_SPI_DSPI4_DMA_PRIO 10 #define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h index db7cfabb1..18cc088ac 100644 --- a/testhal/SPC563Mxx/ADC/mcuconf.h +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -58,10 +58,6 @@ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 #define SPC5_EDMA_GROUP1_PRIORITIES \ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define SPC5_EDMA_GROUP2_PRIORITIES \ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define SPC5_EDMA_GROUP3_PRIORITIES \ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 #define SPC5_EDMA_ERROR_IRQ_PRIO 2 #define SPC5_EDMA_ERROR_HANDLER() chSysHalt() diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h index a06df4fdc..6affa7878 100644 --- a/testhal/SPC563Mxx/SPI/mcuconf.h +++ b/testhal/SPC563Mxx/SPI/mcuconf.h @@ -58,10 +58,6 @@ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 #define SPC5_EDMA_GROUP1_PRIORITIES \ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define SPC5_EDMA_GROUP2_PRIORITIES \ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -#define SPC5_EDMA_GROUP3_PRIORITIES \ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 #define SPC5_EDMA_ERROR_IRQ_PRIO 2 #define SPC5_EDMA_ERROR_HANDLER() chSysHalt() diff --git a/testhal/SPC564Axx/SPI/mcuconf.h b/testhal/SPC564Axx/SPI/mcuconf.h index 0683912f9..2fccca076 100644 --- a/testhal/SPC564Axx/SPI/mcuconf.h +++ b/testhal/SPC564Axx/SPI/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC564Axx_MCUCONF @@ -44,6 +46,25 @@ BIUCR_PFLIM_ON_MISS | \ BIUCR_BFEN) +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * ADC driver settings. */ @@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE #define SPC5_ADC_USE_ADC1_Q4 FALSE #define SPC5_ADC_USE_ADC1_Q5 FALSE -#define SPC5_ADC_FIFO0_DMA_PRIO 12 -#define SPC5_ADC_FIFO1_DMA_PRIO 12 -#define SPC5_ADC_FIFO2_DMA_PRIO 12 -#define SPC5_ADC_FIFO3_DMA_PRIO 12 -#define SPC5_ADC_FIFO4_DMA_PRIO 12 -#define SPC5_ADC_FIFO5_DMA_PRIO 12 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 @@ -115,9 +130,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 -#define SPC5_SPI_DSPI3_DMA_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 diff --git a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h index 435c18e86..221ad245e 100644 --- a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h +++ b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC56ELxx_MCUCONF @@ -41,7 +43,7 @@ #define SPC5_FMPLL1_IDF_VALUE 5 #define SPC5_FMPLL1_NDIV_VALUE 60 #define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 -#define SPC5_SYSCLK_DIVIDER_VALUE 1 +#define SPC5_SYSCLK_DIVIDER_VALUE 2 #define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 #define SPC5_MCONTROL_DIVIDER_VALUE 15 #define SPC5_SWG_DIVIDER_VALUE 2 @@ -134,6 +136,15 @@ SPC5_ME_LP_PC_STOP0) #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * SERIAL driver system settings. */ @@ -217,3 +228,53 @@ SPC5_ME_PCTL_LP(2)) #define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC56ELxx/SPI/main.c b/testhal/SPC56ELxx/SPI/main.c index cdabc06b9..ef283f656 100644 --- a/testhal/SPC56ELxx/SPI/main.c +++ b/testhal/SPC56ELxx/SPI/main.c @@ -30,7 +30,7 @@ static const SPIConfig hs_spicfg = { }; /* - * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first). + * Low speed SPI configuration. */ static const SPIConfig ls_spicfg = { NULL, diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h index 384741bdd..322a9be56 100644 --- a/testhal/SPC56ELxx/SPI/mcuconf.h +++ b/testhal/SPC56ELxx/SPI/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC56ELxx_MCUCONF @@ -134,6 +136,15 @@ SPC5_ME_LP_PC_STOP0) #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * SERIAL driver system settings. */ @@ -153,7 +164,7 @@ /* * PWM driver system settings. */ -#define SPC5_PWM_USE_SMOD0 TRUE +#define SPC5_PWM_USE_SMOD0 FALSE #define SPC5_PWM_USE_SMOD1 FALSE #define SPC5_PWM_USE_SMOD2 FALSE #define SPC5_PWM_USE_SMOD3 FALSE @@ -182,7 +193,7 @@ /* * ICU driver system settings. */ -#define SPC5_ICU_USE_SMOD0 TRUE +#define SPC5_ICU_USE_SMOD0 FALSE #define SPC5_ICU_USE_SMOD1 FALSE #define SPC5_ICU_USE_SMOD2 FALSE #define SPC5_ICU_USE_SMOD3 FALSE @@ -248,9 +259,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI0_DMA_PRIO 10 -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 #define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10