From 8eaf1c10d7f7e30d819f62e90c2e72a3c9e3a06c Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 31 May 2020 07:20:15 +0000 Subject: [PATCH] Fixed bug #1101. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13670 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.c | 4 +-- os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h | 22 ++++++++------- os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c | 28 +++++++++---------- os/hal/ports/STM32/STM32G0xx/stm32_registry.h | 6 ++-- os/hal/ports/STM32/STM32G4xx/stm32_registry.h | 6 ++-- readme.txt | 1 + 6 files changed, 37 insertions(+), 30 deletions(-) diff --git a/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.c b/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.c index 356bfa9e8..e2877cfe2 100644 --- a/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.c +++ b/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.c @@ -72,7 +72,7 @@ void extiEnableGroup1(uint32_t mask, extimode_t mode) { EXTI->EMR1 &= ~mask; EXTI->RTSR1 &= ~mask; EXTI->FTSR1 &= ~mask; -#if STM32_EXTI_TYPE == 0 +#if STM32_EXTI_SEPARATE_RF == FALSE EXTI->PR1 = mask; #else EXTI->RPR1 = mask; @@ -126,7 +126,7 @@ void extiEnableGroup2(uint32_t mask, extimode_t mode) { EXTI->EMR2 &= ~mask; EXTI->RTSR2 &= ~mask; EXTI->FTSR2 &= ~mask; -#if STM32_EXTI_TYPE == 0 +#if STM32_EXTI_SEPARATE_RF == FALSE EXTI->PR2 = mask; #else EXTI->RPR2 = mask; diff --git a/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h b/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h index 4a1dcbb13..dadc58c50 100644 --- a/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h +++ b/os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h @@ -77,14 +77,16 @@ #endif #endif /* !defined(STM32_EXTI_HAS_GROUP2) */ -/* If not defined then it is a classic EXTI (without EXTICR and separate PR - registers for raising and falling edges.*/ -#if !defined(STM32_EXTI_TYPE) -#define STM32_EXTI_TYPE 0 +/* Determines if EXTI has dedicated CR register or if it is done in + SYSCFG (old style).*/ +#if !defined(STM32_EXTI_HAS_CR) +#define STM32_EXTI_HAS_CR FALSE #endif -#if (STM32_EXTI_TYPE < 0) || (STM32_EXTI_TYPE > 1) -#error "invalid STM32_EXTI_TYPE" +/* Determines if EXTI has dedicated separate registers for raising and + falling edges.*/ +#if !defined(STM32_EXTI_SEPARATE_RF) +#define STM32_EXTI_SEPARATE_RF FALSE #endif #if (STM32_EXTI_NUM_LINES < 0) || (STM32_EXTI_NUM_LINES > 63) @@ -140,7 +142,7 @@ typedef uint32_t extimode_t; * * @special */ -#if (STM32_EXTI_TYPE == 0) || defined(__DOXYGEN__) +#if (STM32_EXTI_SEPARATE_RF == FALSE) || defined(__DOXYGEN__) #define extiClearGroup1(mask) do { \ osalDbgAssert(((mask) & STM32_EXTI_IMR1_MASK) == 0U, "fixed lines"); \ EXTI->PR1 = (uint32_t)(mask); \ @@ -161,7 +163,7 @@ typedef uint32_t extimode_t; * * @special */ -#if (STM32_EXTI_TYPE == 0) || defined(__DOXYGEN__) +#if (STM32_EXTI_SEPARATE_RF == FALSE) || defined(__DOXYGEN__) #define extiClearGroup2(mask) do { \ osalDbgAssert(((mask) & STM32_EXTI_IMR2_MASK) == 0U, "fixed lines"); \ EXTI->PR2 = (uint32_t)(mask); \ @@ -183,7 +185,7 @@ typedef uint32_t extimode_t; * * @special */ -#if (STM32_EXTI_TYPE == 0) || defined(__DOXYGEN__) +#if (STM32_EXTI_SEPARATE_RF == FALSE) || defined(__DOXYGEN__) #define extiGetAndClearGroup1(mask, out) do { \ uint32_t pr1; \ \ @@ -212,7 +214,7 @@ typedef uint32_t extimode_t; * * @special */ -#if (STM32_EXTI_TYPE == 0) || defined(__DOXYGEN__) +#if (STM32_EXTI_SEPARATE_RF == FALSE) || defined(__DOXYGEN__) #define extiGetAndClearGroup2(mask, out) do { \ uint32_t pr2; \ \ diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c index fb7be0ae3..ef2fb9a16 100644 --- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c @@ -163,19 +163,19 @@ void _pal_lld_enablepadevent(ioportid_t port, osalDbgAssert(((EXTI->RTSR1 & padmask) == 0U) && ((EXTI->FTSR1 & padmask) == 0U), "channel already in use"); - /* Index and mask of the SYSCFG CR register to be used.*/ - cridx = (uint32_t)pad >> 2U; - croff = ((uint32_t)pad & 3U) * 4U; - crmask = ~(0xFU << croff); - /* Port index is obtained assuming that GPIO ports are placed at regular 0x400 intervals in memory space. So far this is true for all devices.*/ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; - /* Port selection in SYSCFG.*/ -#if STM32_EXTI_TYPE == 0 + /* Index and mask of the CR register to be used.*/ + cridx = (uint32_t)pad >> 2U; +#if STM32_EXTI_HAS_CR == FALSE + croff = ((uint32_t)pad & 3U) * 4U; + crmask = ~(0xFU << croff); SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff); #else + croff = ((uint32_t)pad & 3U) * 8U; + crmask = ~(0xFFU << croff); EXTI->EXTICR[cridx] = (EXTI->EXTICR[cridx] & crmask) | (portidx << croff); #endif @@ -221,18 +221,18 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { if (((rtsr1 | ftsr1) & padmask) != 0U) { uint32_t cridx, croff, crport, portidx; - /* Index and mask of the SYSCFG CR register to be used.*/ - cridx = (uint32_t)pad >> 2U; - croff = ((uint32_t)pad & 3U) * 4U; - /* Port index is obtained assuming that GPIO ports are placed at regular 0x400 intervals in memory space. So far this is true for all devices.*/ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; -#if STM32_EXTI_TYPE == 0 + /* Index and mask of the CR register to be used.*/ + cridx = (uint32_t)pad >> 2U; +#if STM32_EXTI_HAS_CR == FALSE + croff = ((uint32_t)pad & 3U) * 4U; crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU; #else - crport = (EXTI->EXTICR[cridx] >> croff) & 0xFU; + croff = ((uint32_t)pad & 3U) * 8U; + crport = (EXTI->EXTICR[cridx] >> croff) & 0xFFU; #endif osalDbgAssert(crport == portidx, "channel mapped on different port"); @@ -250,7 +250,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { EXTI->EMR1 &= ~padmask; EXTI->RTSR1 = rtsr1 & ~padmask; EXTI->FTSR1 = ftsr1 & ~padmask; -#if STM32_EXTI_TYPE == 0 +#if STM32_EXTI_SEPARATE_RF == FALSE EXTI->PR1 = padmask; #else EXTI->RPR1 = padmask; diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h index 87ce36ed6..fe70551e0 100644 --- a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h @@ -121,7 +121,8 @@ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_TYPE 1 +#define STM32_EXTI_HAS_CR TRUE +#define STM32_EXTI_SEPARATE_RF TRUE #define STM32_EXTI_HAS_GROUP2 FALSE #define STM32_EXTI_NUM_LINES 16 #define STM32_EXTI_IMR1_MASK 0xFFF80000U @@ -300,7 +301,8 @@ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_TYPE 1 +#define STM32_EXTI_HAS_CR TRUE +#define STM32_EXTI_SEPARATE_RF TRUE #define STM32_EXTI_HAS_GROUP2 FALSE #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0xFFF80000U diff --git a/os/hal/ports/STM32/STM32G4xx/stm32_registry.h b/os/hal/ports/STM32/STM32G4xx/stm32_registry.h index 8b2c19f39..e8ed3270c 100644 --- a/os/hal/ports/STM32/STM32G4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32G4xx/stm32_registry.h @@ -143,7 +143,8 @@ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_TYPE 0 +#define STM32_EXTI_HAS_CR FALSE +#define STM32_EXTI_SEPARATE_RF TRUE #define STM32_EXTI_NUM_LINES 41 #define STM32_EXTI_IMR1_MASK 0x1F840000U #define STM32_EXTI_IMR2_MASK 0xFFFFFCF3U @@ -357,7 +358,8 @@ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_TYPE 0 +#define STM32_EXTI_HAS_CR FALSE +#define STM32_EXTI_SEPARATE_RF TRUE #define STM32_EXTI_NUM_LINES 41 #define STM32_EXTI_IMR1_MASK 0x1F840000U #define STM32_EXTI_IMR2_MASK 0xFFFFFCF3U diff --git a/readme.txt b/readme.txt index 8dbe59129..440c17ffa 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,7 @@ ***************************************************************************** *** 20.3.2 *** +- FIX: Fixed differences in STM32 EXTI (bug #1101). - FIX: Fixed STM32 DACv1 driver regressed because DMA changes (bug #1100). - FIX: Fixed STM32L0 missing LPUART IRQ initialization (bug #1099). - FIX: Fixed invalid EXTI definitions for STM32L0xx (bug #1098).