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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@675 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2009-01-24 17:59:51 +00:00
parent f29ada23c5
commit 8fa109243e
24 changed files with 121 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
demos/ARM7-AT91SAM7X-GCC/board.c
View File

@ -44,9 +44,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) {
if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
(void) AT91C_BASE_PITC->PITC_PIVR;
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
}
AT91C_BASE_AIC->AIC_EOICR = 0;

4
demos/ARM7-AT91SAM7X-WEB-GCC/board.c
View File

@ -45,9 +45,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) {
if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
(void) AT91C_BASE_PITC->PITC_PIVR;
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
}
AT91C_BASE_AIC->AIC_EOICR = 0;

4
demos/ARM7-LPC214x-G++/board.c
View File

@ -49,9 +49,9 @@ static CH_IRQ_HANDLER(T0IrqHandler) {
CH_IRQ_PROLOGUE();
T0IR = 1; /* Clear interrupt on match MR0. */
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
VICVectAddr = 0;
CH_IRQ_EPILOGUE();

4
demos/ARM7-LPC214x-GCC-minimal/board.c
View File

@ -49,9 +49,9 @@ static CH_IRQ_HANDLER(T0IrqHandler) {
CH_IRQ_PROLOGUE();
T0IR = 1; /* Clear interrupt on match MR0. */
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
VICVectAddr = 0;
CH_IRQ_EPILOGUE();

4
demos/ARM7-LPC214x-GCC/board.c
View File

@ -49,9 +49,9 @@ static CH_IRQ_HANDLER(T0IrqHandler) {
CH_IRQ_PROLOGUE();
T0IR = 1; /* Clear interrupt on match MR0. */
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
VICVectAddr = 0;
CH_IRQ_EPILOGUE();

4
demos/AVR-AT90CANx-GCC/board.c
View File

@ -26,9 +26,9 @@ CH_IRQ_HANDLER(TIMER0_COMP_vect) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}

4
demos/AVR-ATmega128-GCC/board.c
View File

@ -26,9 +26,9 @@ CH_IRQ_HANDLER(TIMER0_COMP_vect) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}

4
demos/MSP430-MSP430x1611-GCC/board.c
View File

@ -89,9 +89,9 @@ CH_IRQ_HANDLER(TIMERA0_VECTOR) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}

8
docs/ch.txt
View File

@ -127,8 +127,8 @@
* - <b>I-Locked</b>. Kernel locked and regular interrupt sources disabled.
* I-Class APIs are invokable from this state.
* - <b>Serving Regular Interrupt</b>. No system APIs are accessible but it is
* possible to switch to the I-Locked state using @p chSysLockI() and then
* invoke any I-Class API. Interrupt handlers can be preemptable on some
* possible to switch to the I-Locked state using @p chSysLockFromIsr() and
* then invoke any I-Class API. Interrupt handlers can be preemptable on some
* architectures thus is important to switch to I-Locked state before
* invoking system APIs.
* - <b>Serving Fast Interrupt</b>. System APIs are not accessible.
@ -167,8 +167,8 @@
slock -> ilock [label="Context Switch", dir="both"];
norm -> sri [label="Regular IRQ", style="dotted"];
sri -> norm [label="Regular IRQ return", fontname=Helvetica, fontsize=8];
sri -> ilock [label="chSysLockI()", constraint=false];
ilock -> sri [label="chSysUnlockI()", fontsize=8];
sri -> ilock [label="chSysLockFromIsr()", constraint=false];
ilock -> sri [label="chSysUnlockFromIsr()", fontsize=8];
norm -> sleep [label="Idle Thread"];
sleep -> sri [label="Regular IRQ", style="dotted"];
}

4
docs/src/interrupts.dox
View File

@ -11,9 +11,9 @@ CH_IRQ_HANDLER(myIRQ) {
// IRQ handling code, preemptable if the architecture supports it.
chSysLockI();
chSysLockFromIsr();
// Invocation of some I-Class system APIs, never preemptable.
chSysUnlockI().
chSysUnlockFromIsr().
// More IRQ handling code, again preemptable.

8
ports/ARM7-AT91SAM7X/sam7x_emac.c
View File

@ -106,18 +106,18 @@ static void ServeInterrupt(void) {
if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) {
if (rsr & AT91C_EMAC_REC) {
// received++;
chSysLockI();
chSysLockFromIsr();
chEvtBroadcastI(&EMACFrameReceived);
chSysUnlockI();
chSysUnlockFromIsr();
}
AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS;
}
if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) {
if (tsr & AT91C_EMAC_COMP) {
chSysLockI();
chSysLockFromIsr();
chEvtBroadcastI(&EMACFrameTransmitted);
chSysUnlockI();
chSysUnlockFromIsr();
}
AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS;
}

34
ports/ARM7-AT91SAM7X/sam7x_serial.c
View File

@ -42,9 +42,9 @@ static void SetError(AT91_REG csr, FullDuplexDriver *com) {
sts |= SD_FRAMING_ERROR;
if (csr & AT91C_US_RXBRK)
sts |= SD_BREAK_DETECTED;
chSysLockI();
chSysLockFromIsr();
chFDDAddFlagsI(com, sts);
chSysUnlockI();
chSysUnlockFromIsr();
}
/*
@ -54,14 +54,14 @@ __attribute__((noinline))
static void ServeInterrupt(AT91PS_USART u, FullDuplexDriver *com) {
if (u->US_CSR & AT91C_US_RXRDY) {
chSysLockI();
chSysLockFromIsr();
chFDDIncomingDataI(com, u->US_RHR);
chSysUnlockI();
chSysUnlockFromIsr();
}
if (u->US_CSR & AT91C_US_TXRDY) {
chSysLockI();
chSysLockFromIsr();
msg_t b = chFDDRequestDataI(com);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
u->US_IDR = AT91C_US_TXRDY;
else
@ -114,7 +114,7 @@ static void OutNotify2(void) {
* USART setup, must be invoked with interrupts disabled.
* NOTE: Does not reset I/O queues.
*/
void SetUSARTI(AT91PS_USART u, int speed, int mode) {
void SetUSART(AT91PS_USART u, int speed, int mode) {
/* Disables IRQ sources and stop operations.*/
u->US_IDR = 0xFFFFFFFF;
@ -169,14 +169,14 @@ void InitSerial(int prio0, int prio1) {
USART1IrqHandler);
AIC_EnableIT(AT91C_ID_US1);
SetUSARTI(AT91C_BASE_US0, 38400, AT91C_US_USMODE_NORMAL |
AT91C_US_CLKS_CLOCK |
AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE |
AT91C_US_NBSTOP_1_BIT);
SetUSARTI(AT91C_BASE_US1, 38400, AT91C_US_USMODE_NORMAL |
AT91C_US_CLKS_CLOCK |
AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE |
AT91C_US_NBSTOP_1_BIT);
SetUSART(AT91C_BASE_US0, 38400, AT91C_US_USMODE_NORMAL |
AT91C_US_CLKS_CLOCK |
AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE |
AT91C_US_NBSTOP_1_BIT);
SetUSART(AT91C_BASE_US1, 38400, AT91C_US_USMODE_NORMAL |
AT91C_US_CLKS_CLOCK |
AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE |
AT91C_US_NBSTOP_1_BIT);
}

2
ports/ARM7-AT91SAM7X/sam7x_serial.h
View File

@ -30,7 +30,7 @@
extern "C" {
#endif
void InitSerial(int prio0, int prio1);
void SetUSARTI(AT91PS_USART u, int speed, int mode);
void SetUSART(AT91PS_USART u, int speed, int mode);
CH_IRQ_HANDLER(UART0IrqHandler);
CH_IRQ_HANDLER(UART1IrqHandler);
#ifdef __cplusplus

42
ports/ARM7-LPC214x/lpc214x_serial.c
View File

@ -43,9 +43,9 @@ static void SetError(IOREG32 err, FullDuplexDriver *com) {
sts |= SD_FRAMING_ERROR;
if (err & LSR_BREAK)
sts |= SD_BREAK_DETECTED;
chSysLockI();
chSysLockFromIsr();
chFDDAddFlagsI(com, sts);
chSysUnlockI();
chSysUnlockFromIsr();
}
/*
@ -66,36 +66,36 @@ static void ServeInterrupt(UART *u, FullDuplexDriver *com) {
case IIR_SRC_TIMEOUT:
case IIR_SRC_RX:
while (u->UART_LSR & LSR_RBR_FULL) {
chSysLockI();
chSysLockFromIsr();
if (chIQPutI(&com->sd_iqueue, u->UART_RBR) < Q_OK)
chFDDAddFlagsI(com, SD_OVERRUN_ERROR);
chSysUnlockI();
chSysUnlockFromIsr();
}
chSysLockI();
chSysLockFromIsr();
chEvtBroadcastI(&com->sd_ievent);
chSysUnlockI();
chSysUnlockFromIsr();
break;
case IIR_SRC_TX:
{
#ifdef FIFO_PRELOAD
int i = FIFO_PRELOAD;
do {
chSysLockI();
chSysLockFromIsr();
msg_t b = chOQGetI(&com->sd_oqueue);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK) {
u->UART_IER &= ~IER_THRE;
chSysLockI();
chSysLockFromIsr();
chEvtBroadcastI(&com->sd_oevent);
chSysUnlockI();
chSysUnlockFromIsr();
break;
}
u->UART_THR = b;
} while (--i);
#else
chSysLockI();
chSysLockFromIsr();
msg_t b = chFDDRequestDataI(com);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
u->UART_IER &= ~IER_THRE;
else
@ -135,13 +135,13 @@ static void preload(UART *u, FullDuplexDriver *com) {
if (u->UART_LSR & LSR_THRE) {
int i = FIFO_PRELOAD;
do {
chSysLockI();
chSysLockFromIsr();
msg_t b = chOQGetI(&com->sd_oqueue);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK) {
chSysLockI();
chSysLockFromIsr();
chEvtBroadcastI(&com->sd_oevent);
chSysUnlockI();
chSysUnlockFromIsr();
return;
}
u->UART_THR = b;
@ -163,9 +163,9 @@ static void OutNotify1(void) {
UART *u = U0Base;
if (u->UART_LSR & LSR_THRE) {
chSysLockI();
chSysLockFromIsr();
u->UART_THR = chOQGetI(&COM1.sd_oqueue);
chSysUnlockI();
chSysUnlockFromIsr();
}
u->UART_IER |= IER_THRE;
#endif
@ -191,7 +191,7 @@ static void OutNotify2(void) {
/*
* UART setup, must be invoked with interrupts disabled.
*/
void SetUARTI(UART *u, int speed, int lcr, int fcr) {
void SetUART(UART *u, int speed, int lcr, int fcr) {
int div = PCLK / (speed << 4);
u->UART_LCR = lcr | LCR_DLAB;
@ -216,10 +216,10 @@ void InitSerial(int vector1, int vector2) {
PCONP = (PCONP & PCALL) | PCUART0 | PCUART1;
chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
SetUARTI(U0Base, 38400, LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, FCR_TRIGGER0);
SetUART(U0Base, 38400, LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, FCR_TRIGGER0);
chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
SetUARTI(U1Base, 38400, LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, FCR_TRIGGER0);
SetUART(U1Base, 38400, LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, FCR_TRIGGER0);
VICIntEnable = INTMASK(SOURCE_UART0) | INTMASK(SOURCE_UART1);
}

2
ports/ARM7-LPC214x/lpc214x_serial.h
View File

@ -41,7 +41,7 @@
extern "C" {
#endif
void InitSerial(int vector1, int vector2);
void SetUARTI(UART *u, int speed, int lcr, int fcr);
void SetUART(UART *u, int speed, int lcr, int fcr);
CH_IRQ_HANDLER(UART0IrqHandler);
CH_IRQ_HANDLER(UART1IrqHandler);
#ifdef __cplusplus

22
ports/ARMCM3-STM32F103/stm32_serial.c
View File

@ -55,9 +55,9 @@ static void SetError(uint16_t sr, FullDuplexDriver *com) {
sts |= SD_FRAMING_ERROR;
if (sr & SR_LBD)
sts |= SD_BREAK_DETECTED;
chSysLockI();
chSysLockFromIsr();
chFDDAddFlagsI(com, sts);
chSysUnlockI();
chSysUnlockFromIsr();
}
static void ServeInterrupt(USART_TypeDef *u, FullDuplexDriver *com) {
@ -66,14 +66,14 @@ static void ServeInterrupt(USART_TypeDef *u, FullDuplexDriver *com) {
if (sr & (SR_ORE | SR_FE | SR_PE | SR_LBD))
SetError(sr, com);
if (sr & SR_RXNE) {
chSysLockI();
chSysLockFromIsr();
chFDDIncomingDataI(com, u->DR);
chSysUnlockI();
chSysUnlockFromIsr();
}
if (sr & SR_TXE) {
chSysLockI();
chSysLockFromIsr();
msg_t b = chFDDRequestDataI(com);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
u->CR1 &= ~CR1_TXEIE;
else
@ -154,8 +154,8 @@ static void OutNotify3(void) {
* USART setup, must be invoked with interrupts disabled.
* NOTE: Does not reset I/O queues.
*/
void SetUSARTI(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
uint16_t cr2, uint16_t cr3) {
void SetUSART(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
uint16_t cr2, uint16_t cr3) {
/*
* Baud rate setting.
@ -183,7 +183,7 @@ void InitSerial(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
#ifdef USE_USART1
chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
RCC->APB2ENR |= 0x00004000;
SetUSARTI(USART1, USART_BITRATE, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
SetUSART(USART1, USART_BITRATE, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
GPIOA->CRH = (GPIOA->CRH & 0xFFFFF00F) | 0x000004B0;
NVICEnableVector(USART1_IRQChannel, prio1);
#endif
@ -191,7 +191,7 @@ void InitSerial(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
#ifdef USE_USART2
chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
RCC->APB1ENR |= 0x00020000;
SetUSARTI(USART2, USART_BITRATE, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
SetUSART(USART2, USART_BITRATE, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
GPIOA->CRL = (GPIOA->CRL & 0xFFFF00FF) | 0x00004B00;
NVICEnableVector(USART2_IRQChannel, prio2);
#endif
@ -199,7 +199,7 @@ void InitSerial(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
#ifdef USE_USART3
chFDDInit(&COM3, ib3, sizeof ib3, NULL, ob3, sizeof ob3, OutNotify3);
RCC->APB1ENR |= 0x00040000;
SetUSARTI(USART3, USART_BITRATE, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
SetUSART(USART3, USART_BITRATE, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
GPIOB->CRH = (GPIOB->CRH & 0xFFFF00FF) | 0x00004B00;
NVICEnableVector(USART3_IRQChannel, prio3);
#endif

4
ports/ARMCM3-STM32F103/stm32_serial.h
View File

@ -99,8 +99,8 @@ extern FullDuplexDriver COM3;
extern "C" {
#endif
void InitSerial(uint32_t prio1, uint32_t prio2, uint32_t prio3);
void SetUSARTI(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
uint16_t cr2, uint16_t cr3);
void SetUSART(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
uint16_t cr2, uint16_t cr3);
#ifdef __cplusplus
}
#endif

8
ports/ARMCM3/chcore.c
View File

@ -75,9 +75,9 @@ CH_IRQ_HANDLER(SysTickVector) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
@ -163,10 +163,10 @@ void PendSVVector(void) {
Thread *otp;
register struct intctx *sp_thd asm("r12");
chSysLockI();
chSysLockFromIsr();
asm volatile ("push {lr}");
if (!chSchRescRequiredI()) {
chSysUnlockI();
chSysUnlockFromIsr();
asm volatile ("pop {pc}");
}
asm volatile ("pop {lr}");

26
ports/AVR/avr_serial.c
View File

@ -30,9 +30,9 @@ static void SetError(uint8_t sra, FullDuplexDriver *com) {
sts |= SD_PARITY_ERROR;
if (sra & (1 << FE))
sts |= SD_FRAMING_ERROR;
chSysLockI();
chSysLockFromIsr();
chFDDAddFlagsI(com, sts);
chSysUnlockI();
chSysUnlockFromIsr();
}
#ifdef USE_AVR_USART0
@ -48,9 +48,9 @@ CH_IRQ_HANDLER(USART0_RX_vect) {
sra = UCSR0A;
if (sra & ((1 << DOR) | (1 << UPE) | (1 << FE)))
SetError(sra, &SER1);
chSysLockI();
chSysLockFromIsr();
chFDDIncomingDataI(&SER1, UDR0);
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
@ -60,9 +60,9 @@ CH_IRQ_HANDLER(USART0_UDRE_vect) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
b = chFDDRequestDataI(&SER1);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
UCSR0B &= ~(1 << UDRIE);
else
@ -107,9 +107,9 @@ CH_IRQ_HANDLER(USART1_RX_vect) {
sra = UCSR1A;
if (sra & ((1 << DOR) | (1 << UPE) | (1 << FE)))
SetError(sra, &SER2);
chSysLockI();
chSysLockFromIsr();
chFDDIncomingDataI(&SER2, UDR1);
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
@ -119,9 +119,9 @@ CH_IRQ_HANDLER(USART1_UDRE_vect) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
b = chFDDRequestDataI(&SER2);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
UCSR1B &= ~(1 << UDRIE);
else
@ -143,7 +143,7 @@ static void OutNotify2(void) {
* USART setup, must be invoked with interrupts disabled.
* NOTE: Does not reset I/O queues.
*/
void SetUSART1I(uint16_t brr, uint8_t csrc) {
void SetUSART1(uint16_t brr, uint8_t csrc) {
UBRR1L = brr;
UBRR1H = brr >> 8;
@ -158,11 +158,11 @@ void InitSerial(void) {
#ifdef USE_AVR_USART0
/* I/O queues setup.*/
chFDDInit(&SER1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
SetUSART0I(UBRR(38400), (1 << UCSZ1) | (1 << UCSZ0));
SetUSART0(UBRR(38400), (1 << UCSZ1) | (1 << UCSZ0));
#endif
#ifdef USE_AVR_USART1
chFDDInit(&SER2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
SetUSART1I(UBRR(38400), (1 << UCSZ1) | (1 << UCSZ0));
SetUSART1(UBRR(38400), (1 << UCSZ1) | (1 << UCSZ0));
#endif
}

4
ports/AVR/avr_serial.h
View File

@ -38,8 +38,8 @@
extern "C" {
#endif
void InitSerial(void);
void SetUSART0I(uint16_t brr, uint8_t csrc);
void SetUSART1I(uint16_t brr, uint8_t csrc);
void SetUSART0(uint16_t brr, uint8_t csrc);
void SetUSART1(uint16_t brr, uint8_t csrc);
#ifdef __cplusplus
}
#endif

32
ports/MSP430/msp430_serial.c
View File

@ -34,9 +34,9 @@ static void SetError(uint8_t urctl, FullDuplexDriver *com) {
sts |= SD_FRAMING_ERROR;
if (urctl & BRK)
sts |= SD_BREAK_DETECTED;
chSysLockI();
chSysLockFromIsr();
chFDDAddFlagsI(com, sts);
chSysUnlockI();
chSysUnlockFromIsr();
}
#ifdef USE_MSP430_USART0
@ -49,9 +49,9 @@ CH_IRQ_HANDLER(USART0TX_VECTOR) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
b = chFDDRequestDataI(&COM1);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
U0IE &= ~UTXIE0;
else
@ -67,9 +67,9 @@ CH_IRQ_HANDLER(USART0RX_VECTOR) {
if ((urctl = U0RCTL) & RXERR)
SetError(urctl, &COM1);
chSysLockI();
chSysLockFromIsr();
chFDDIncomingDataI(&COM1, U0RXBUF);
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
@ -81,9 +81,9 @@ CH_IRQ_HANDLER(USART0RX_VECTOR) {
static void OutNotify1(void) {
if (!(U0IE & UTXIE0)) {
chSysLockI();
chSysLockFromIsr();
U0TXBUF = (uint8_t)chFDDRequestDataI(&COM1);
chSysUnlockI();
chSysUnlockFromIsr();
U0IE |= UTXIE0;
}
}
@ -92,7 +92,7 @@ static void OutNotify1(void) {
* USART setup, must be invoked with interrupts disabled.
* NOTE: Does not reset I/O queues.
*/
void SetUSART0I(uint16_t div, uint8_t mod, uint8_t ctl) {
void SetUSART0(uint16_t div, uint8_t mod, uint8_t ctl) {
U0CTL = SWRST; /* Resets the USART, it should already be */
/* USART init */
@ -121,9 +121,9 @@ CH_IRQ_HANDLER(USART1TX_VECTOR) {
CH_IRQ_PROLOGUE();
chSysLockI();
chSysLockFromIsr();
b = chFDDRequestDataI(&COM2);
chSysUnlockI();
chSysUnlockFromIsr();
if (b < Q_OK)
U1IE &= ~UTXIE1;
else
@ -139,9 +139,9 @@ CH_IRQ_HANDLER(USART1RX_VECTOR) {
if ((urctl = U1RCTL) & RXERR)
SetError(urctl, &COM2);
chSysLockI();
chSysLockFromIsr();
chFDDIncomingDataI(&COM2, U1RXBUF);
chSysUnlockI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
@ -162,7 +162,7 @@ static void OutNotify2(void) {
* USART setup, must be invoked with interrupts disabled.
* NOTE: Does not reset I/O queues.
*/
void SetUSART1I(uint16_t div, uint8_t mod, uint8_t ctl) {
void SetUSART1(uint16_t div, uint8_t mod, uint8_t ctl) {
U1CTL = SWRST; /* Resets the USART, it should already be */
/* USART init */
@ -186,11 +186,11 @@ void InitSerial(void) {
/* I/O queues setup.*/
#ifdef USE_MSP430_USART0
chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
SetUSART0I(UBR(38400), 0, CHAR);
SetUSART0(UBR(38400), 0, CHAR);
#endif
#ifdef USE_MSP430_USART1
chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
SetUSART1I(UBR(38400), 0, CHAR);
SetUSART1(UBR(38400), 0, CHAR);
#endif
}

4
ports/MSP430/msp430_serial.h
View File

@ -38,8 +38,8 @@
extern "C" {
#endif
void InitSerial(void);
void SetUSART0I(uint16_t div, uint8_t mod, uint8_t ctl);
void SetUSART1I(uint16_t div, uint8_t mod, uint8_t ctl);
void SetUSART0(uint16_t div, uint8_t mod, uint8_t ctl);
void SetUSART1(uint16_t div, uint8_t mod, uint8_t ctl);
#ifdef __cplusplus
}
#endif

4
readme.txt
View File

@ -78,7 +78,9 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
Port functions/macros are no more directly exposed as APIs to the user code.
- NEW: Added a configuration option to enable nested system locks/unlocks.
- NEW: Improved the interrupt handlers related code. Now interrupts are
handled in a very similar way in every architecture.
handled in a very similar way in every architecture. See the "Concepts"
section and the "Writing interrupt handlers under ChibiOS/RT" article in the
documentation.
- OPT: Improved ARM7 thumb port code, thanks to some GCC tricks involving
registers usage now the kernel is much smaller, faster and most OS APIs
use less RAM in stack frames (note, this is an ARM7 thumb mode specific

8
src/include/sys.h
View File

@ -134,7 +134,7 @@
* syscall from an interrupt handler.
* @note This API must be invoked exclusively from interrupt handlers.
*/
#define chSysLockI() port_lock_from_isr()
#define chSysLockFromIsr() port_lock_from_isr()
/**
* @brief Leaves the kernel lock mode from within an interrupt handler.
@ -147,7 +147,7 @@
* syscall from an interrupt handler.
* @note This API must be invoked exclusively from interrupt handlers.
*/
#define chSysUnlockI() port_unlock_from_isr()
#define chSysUnlockFromIsr() port_unlock_from_isr()
/**
* @brief IRQ handler enter code.
@ -179,10 +179,6 @@ extern "C" {
#endif
void chSysInit(void);
void chSysTimerHandlerI(void);
#if !defined(CH_OPTIMIZE_SPEED)
void chSysLock(void);
void chSysUnlock(void);
#endif /* !defined(CH_OPTIMIZE_SPEED) */
#ifdef __cplusplus
}
#endif