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Better checks on wait states. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14401 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-20 12:10:17 +00:00
parent a029c535cd
commit 9001637856
4 changed files with 205 additions and 92 deletions
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12
os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc
View File

@ -70,6 +70,18 @@ __STATIC_INLINE void hsi16_disable(void) {
RCC->CR &= ~RCC_CR_HSION;
}
__STATIC_INLINE void hsi16_reset(void) {
/* Making sure HSI is active and ready.*/
hsi16_enable();
/* Clocking from HSI, in case HSI was not the default source.*/
RCC->CFGR = RCC_CFGR_SW_HSI;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
/* Wait until HSI is selected.*/
}
}
__STATIC_INLINE void hsi16_init(void) {
#if STM32_HSI16_ENABLED

2
os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc
View File

@ -180,7 +180,7 @@ __STATIC_INLINE void msi_reset(void) {
RCC->CR = (RCC->CR & ~RCC_CR_MSIRANGE_Msk) | RCC_CR_MSIRANGE_6;
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = 0U;
RCC->CFGR = RCC_CFGR_SW_MSI;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) {
/* Wait until MSI is selected.*/
}

130
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -31,7 +31,7 @@
/**
* @brief Number of thresholds in the wait states array.
*/
#define STM32_WS_THRESHOLDS 9
#define STM32_WS_THRESHOLDS 5
/*===========================================================================*/
/* Driver exported variables. */
@ -57,8 +57,9 @@ const halclkcfg_t hal_clkcfg_reset = {
.rcc_cr = RCC_CR_HSIKERON | RCC_CR_HSION,
.rcc_cfgr = RCC_CFGR_SW_HSI,
.rcc_pllcfgr = 0U,
.rcc_crrcr = 0U,
.flash_acr = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN |
FLASH_ACR_ICEN | FLASH_ACR_LATENCY_1WS
FLASH_ACR_ICEN | FLASH_ACR_LATENCY_0WS
};
/**
@ -89,6 +90,11 @@ const halclkcfg_t hal_clkcfg_default = {
STM32_PLLQEN | STM32_PLLP |
STM32_PLLPEN | STM32_PLLN |
STM32_PLLM | STM32_PLLSRC,
#if STM32_HSI48_ENABLED
.rcc_crrcr = RCC_CRRCR_HSI48ON,
#else
.rcc_crrcr = 0U,
#endif
.flash_acr = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN |
FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_FLASHBITS
@ -120,8 +126,7 @@ static halfreq_t clock_points[CLK_ARRAY_SIZE] = {
* @brief Type of a structure representing system limits.
*/
typedef struct {
halfreq_t sysclk_max_boost;
halfreq_t sysclk_max_noboost;
halfreq_t sysclk_max;
halfreq_t pllin_max;
halfreq_t pllin_min;
halfreq_t pllvco_max;
@ -136,11 +141,30 @@ typedef struct {
} system_limits_t;
/**
* @brief System limits for VOS RANGE1.
* @brief System limits for VOS range 1 with boost.
*/
static const system_limits_t vos_range1 = {
.sysclk_max_boost = STM32_VOS1_SYSCLK_MAX,
.sysclk_max_noboost = STM32_VOS1_SYSCLK_MAX_NOBOOST,
static const system_limits_t vos_range1_boost = {
.sysclk_max = STM32_BOOST_SYSCLK_MAX,
.pllin_max = STM32_BOOST_PLLIN_MAX,
.pllin_min = STM32_BOOST_PLLIN_MIN,
.pllvco_max = STM32_BOOST_PLLVCO_MAX,
.pllvco_min = STM32_BOOST_PLLVCO_MIN,
.pllp_max = STM32_BOOST_PLLP_MAX,
.pllp_min = STM32_BOOST_PLLP_MIN,
.pllq_max = STM32_BOOST_PLLQ_MAX,
.pllq_min = STM32_BOOST_PLLQ_MIN,
.pllr_max = STM32_BOOST_PLLR_MAX,
.pllr_min = STM32_BOOST_PLLR_MIN,
.flash_thresholds = {STM32_BOOST_0WS_THRESHOLD, STM32_BOOST_1WS_THRESHOLD,
STM32_BOOST_2WS_THRESHOLD, STM32_BOOST_3WS_THRESHOLD,
STM32_BOOST_4WS_THRESHOLD}
};
/**
* @brief System limits for VOS range 1 without boost.
*/
static const system_limits_t vos_range1_noboost = {
.sysclk_max = STM32_VOS1_SYSCLK_MAX,
.pllin_max = STM32_VOS1_PLLIN_MAX,
.pllin_min = STM32_VOS1_PLLIN_MIN,
.pllvco_max = STM32_VOS1_PLLVCO_MAX,
@ -153,17 +177,14 @@ static const system_limits_t vos_range1 = {
.pllr_min = STM32_VOS1_PLLR_MIN,
.flash_thresholds = {STM32_VOS1_0WS_THRESHOLD, STM32_VOS1_1WS_THRESHOLD,
STM32_VOS1_2WS_THRESHOLD, STM32_VOS1_3WS_THRESHOLD,
STM32_VOS1_4WS_THRESHOLD, STM32_VOS1_5WS_THRESHOLD,
STM32_VOS1_6WS_THRESHOLD, STM32_VOS1_7WS_THRESHOLD,
STM32_VOS1_8WS_THRESHOLD}
STM32_VOS1_4WS_THRESHOLD}
};
/**
* @brief System limits for VOS RANGE2.
*/
static const system_limits_t vos_range2 = {
.sysclk_max_boost = STM32_VOS2_SYSCLK_MAX,
.sysclk_max_noboost = STM32_VOS2_SYSCLK_MAX_NOBOOST,
.sysclk_max = STM32_VOS2_SYSCLK_MAX,
.pllin_max = STM32_VOS2_PLLIN_MAX,
.pllin_min = STM32_VOS2_PLLIN_MIN,
.pllvco_max = STM32_VOS2_PLLVCO_MAX,
@ -176,9 +197,7 @@ static const system_limits_t vos_range2 = {
.pllr_min = STM32_VOS2_PLLR_MIN,
.flash_thresholds = {STM32_VOS2_0WS_THRESHOLD, STM32_VOS2_1WS_THRESHOLD,
STM32_VOS2_2WS_THRESHOLD, STM32_VOS2_3WS_THRESHOLD,
STM32_VOS2_4WS_THRESHOLD, STM32_VOS2_5WS_THRESHOLD,
STM32_VOS2_6WS_THRESHOLD, STM32_VOS2_7WS_THRESHOLD,
STM32_VOS2_8WS_THRESHOLD}
STM32_VOS2_4WS_THRESHOLD}
};
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
@ -211,10 +230,18 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* System limits based on desired VOS settings.*/
if ((ccp->pwr_cr1 & PWR_CR1_VOS_Msk) == PWR_CR1_VOS_1) {
if ((ccp->pwr_cr1 & PWR_CR5_R1MODE) != 0U) {
return true;
}
slp = &vos_range2;
}
else if ((ccp->pwr_cr1 & PWR_CR1_VOS_Msk) == PWR_CR1_VOS_0) {
slp = &vos_range1;
if ((ccp->pwr_cr1 & PWR_CR5_R1MODE) != 0U) {
slp = &vos_range1_boost;
}
else {
slp = &vos_range1_noboost;
}
}
else {
return true;
@ -320,15 +347,8 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
sysclk = 0U;
}
if ((ccp->pwr_cr5 & PWR_CR5_R1MODE) == 0U) {
if (sysclk > slp->sysclk_max_boost) {
return true;
}
}
else {
if (sysclk > slp->sysclk_max_noboost) {
return true;
}
if (sysclk > slp->sysclk_max) {
return true;
}
/* HCLK frequency.*/
@ -425,9 +445,6 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
/* Restoring default PWR settings related clocks and sleep modes.*/
PWR->CR1 = PWR_CR1_VOS_0;
PWR->CR2 = 0U;
PWR->CR3 = PWR_CR3_EIWF;
PWR->CR4 = 0U;
/* Waiting for all regulator status bits to be cleared, this means that
power levels are stable.*/
@ -435,35 +452,49 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
/* Waiting for the regulator to be ready.*/
}
/* Making sure HSI16 is activated.*/
hsi16_enable();
/* If the clock source is not HSI then we switch to HSI and reset some
other relevant registers to their default value.*/
if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
/* Disabling boost mode.*/
PWR->CR5 = PWR_CR5_R1MODE;
/* Making sure HSI is activated and in use.*/
hsi16_reset();
/* Switching to the HSI oscillator.*/
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | RCC_CFGR_SW_HSI;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
/* Waiting for clock switch.*/
/* Resetting flash ACR settings to the default value.*/
FLASH->ACR = 0x00040600U;
/* Resetting all other clock sources and PLLs.*/
RCC->CRRCR = 0U;
RCC->CR = 0x00000063U;
while ((RCC->CR & RCC_CR_HSERDY) != 0U) {
/* Waiting for oscillators to shut down.*/
}
/* Disabling boost mode.*/
PWR->CR5 = PWR_CR5_R1MODE;
}
/* Resetting flash ACR settings to the default value.*/
FLASH->ACR = 0x00040601U;
/* HSE setup, if required, before starting the PLL.*/
if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) {
hse_enable();
}
/* HSI48 setup, if required, before starting the PLL.*/
if ((ccp->rcc_crrcr & RCC_CRRCR_HSI48ON) != 0U) {
hsi48_enable();
}
/* PLL setup.*/
RCC->PLLCFGR = ccp->rcc_pllcfgr;
/* HSI, HSE, PLL enabled if specified.*/
/* PLLs enabled if specified.*/
RCC->CR = ccp->rcc_cr;
/* PLL activation polling if required.*/
if ((ccp->rcc_cr & RCC_CR_PLLON) != 0U) {
pll_wait_lock();
while (true) {
if (((ccp->rcc_cr & RCC_CR_PLLON) != 0U) && pll_not_locked()) {
continue;
}
break;
}
/* MCO and bus dividers first.*/
@ -479,10 +510,19 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
PWR->CR4 = ccp->pwr_cr4;
PWR->CR5 = ccp->pwr_cr5;
/* Wait on LPR bit clear.*/
/* Waiting for the correct regulator state.*/
if ((ccp->pwr_cr1 & PWR_CR1_LPR) == 0U) {
/* Main mode selected.*/
while ((PWR->SR2 & PWR_SR2_REGLPF) != 0U) {
/* Waiting for the regulator to be ready.*/
/* Waiting for the regulator to be in main mode.*/
}
}
else {
/* Low power mode selected.*/
while ((PWR->SR2 & PWR_SR2_REGLPF) == 0U) {
/* Waiting for the regulator to be in low power mode.*/
}
}

153
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -300,6 +300,14 @@
#define STM32_VOS STM32_VOS_RANGE1
#endif
/**
* @brief Core voltage boost.
* @note The boost can only be used when STM32_VOS==STM32_VOS_RANGE1.
*/
#if !defined(STM32_PWR_BOOST) || defined(__DOXYGEN__)
#define STM32_PWR_BOOST TRUE
#endif
/**
* @brief PWR CR2 register initialization value.
*/
@ -619,6 +627,11 @@
#define HAL_LLD_USE_CLOCK_MANAGEMENT
#endif
/* Boost mode checks.*/
#if STM32_PWR_BOOST && (STM32_VOS != STM32_VOS_RANGE1)
#error "STM32_PWR_BOOST requires STM32_VOS_RANGE1"
#endif
/*
* Configuration-related checks.
*/
@ -653,11 +666,44 @@
#endif
/**
* @name System Limits for VOS range 1
* @name System Limits for VOS range 1 with boost
* @{
*/
#define STM32_VOS1_SYSCLK_MAX 170000000
#define STM32_VOS1_SYSCLK_MAX_NOBOOST 150000000
#define STM32_BOOST_SYSCLK_MAX 170000000
#define STM32_BOOST_HSECLK_MAX 48000000
#define STM32_BOOST_HSECLK_BYP_MAX 48000000
#define STM32_BOOST_HSECLK_MIN 8000000
#define STM32_BOOST_HSECLK_BYP_MIN 8000000
#define STM32_BOOST_LSECLK_MAX 32768
#define STM32_BOOST_LSECLK_BYP_MAX 1000000
#define STM32_BOOST_LSECLK_MIN 32768
#define STM32_BOOST_LSECLK_BYP_MIN 32768
#define STM32_BOOST_PLLIN_MAX 16000000
#define STM32_BOOST_PLLIN_MIN 2660000
#define STM32_BOOST_PLLVCO_MAX 344000000
#define STM32_BOOST_PLLVCO_MIN 96000000
#define STM32_BOOST_PLLP_MAX 170000000
#define STM32_BOOST_PLLP_MIN 2064500
#define STM32_BOOST_PLLQ_MAX 170000000
#define STM32_BOOST_PLLQ_MIN 8000000
#define STM32_BOOST_PLLR_MAX 170000000
#define STM32_BOOST_PLLR_MIN 8000000
#define STM32_BOOST_PCLK1_MAX 170000000
#define STM32_BOOST_PCLK2_MAX 170000000
#define STM32_BOOST_ADCCLK_MAX 60000000
#define STM32_BOOST_0WS_THRESHOLD 34000000
#define STM32_BOOST_1WS_THRESHOLD 68000000
#define STM32_BOOST_2WS_THRESHOLD 102000000
#define STM32_BOOST_3WS_THRESHOLD 136000000
#define STM32_BOOST_4WS_THRESHOLD 170000000
/** @} */
/**
* @name System Limits for VOS range 1 without boost
* @{
*/
#define STM32_VOS1_SYSCLK_MAX 150000000
#define STM32_VOS1_HSECLK_MAX 48000000
#define STM32_VOS1_HSECLK_BYP_MAX 48000000
#define STM32_VOS1_HSECLK_MIN 8000000
@ -670,25 +716,21 @@
#define STM32_VOS1_PLLIN_MIN 2660000
#define STM32_VOS1_PLLVCO_MAX 344000000
#define STM32_VOS1_PLLVCO_MIN 96000000
#define STM32_VOS1_PLLP_MAX 170000000
#define STM32_VOS1_PLLP_MAX 150000000
#define STM32_VOS1_PLLP_MIN 2064500
#define STM32_VOS1_PLLQ_MAX 170000000
#define STM32_VOS1_PLLQ_MAX 150000000
#define STM32_VOS1_PLLQ_MIN 8000000
#define STM32_VOS1_PLLR_MAX 170000000
#define STM32_VOS1_PLLR_MAX 150000000
#define STM32_VOS1_PLLR_MIN 8000000
#define STM32_VOS1_PCLK1_MAX 170000000
#define STM32_VOS1_PCLK2_MAX 170000000
#define STM32_VOS1_PCLK1_MAX 150000000
#define STM32_VOS1_PCLK2_MAX 150000000
#define STM32_VOS1_ADCCLK_MAX 60000000
#define STM32_VOS1_0WS_THRESHOLD 20000000
#define STM32_VOS1_1WS_THRESHOLD 40000000
#define STM32_VOS1_2WS_THRESHOLD 60000000
#define STM32_VOS1_3WS_THRESHOLD 80000000
#define STM32_VOS1_4WS_THRESHOLD 100000000
#define STM32_VOS1_5WS_THRESHOLD 120000000
#define STM32_VOS1_6WS_THRESHOLD 140000000
#define STM32_VOS1_7WS_THRESHOLD 160000000
#define STM32_VOS1_8WS_THRESHOLD 170000000
#define STM32_VOS1_0WS_THRESHOLD 30000000
#define STM32_VOS1_1WS_THRESHOLD 60000000
#define STM32_VOS1_2WS_THRESHOLD 90000000
#define STM32_VOS1_3WS_THRESHOLD 120000000
#define STM32_VOS1_4WS_THRESHOLD 150000000
/** @} */
/**
@ -696,7 +738,6 @@
* @{
*/
#define STM32_VOS2_SYSCLK_MAX 26000000
#define STM32_VOS2_SYSCLK_MAX_NOBOOST 26000000
#define STM32_VOS2_HSECLK_MAX 26000000
#define STM32_VOS2_HSECLK_BYP_MAX 26000000
#define STM32_VOS2_HSECLK_MIN 8000000
@ -719,21 +760,51 @@
#define STM32_VOS2_PCLK2_MAX 26000000
#define STM32_VOS2_ADCCLK_MAX 26000000
#define STM32_VOS2_0WS_THRESHOLD 8000000
#define STM32_VOS2_1WS_THRESHOLD 16000000
#define STM32_VOS2_0WS_THRESHOLD 12000000
#define STM32_VOS2_1WS_THRESHOLD 24000000
#define STM32_VOS2_2WS_THRESHOLD 26000000
#define STM32_VOS2_3WS_THRESHOLD 0
#define STM32_VOS2_4WS_THRESHOLD 0
#define STM32_VOS2_5WS_THRESHOLD 0
#define STM32_VOS2_6WS_THRESHOLD 0
#define STM32_VOS2_7WS_THRESHOLD 0
#define STM32_VOS2_8WS_THRESHOLD 0
/** @} */
/* Voltage related limits.*/
#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX STM32_VOS1_SYSCLK_MAX
#define STM32_SYSCLK_MAX_NOBOOST STM32_VOS1_SYSCLK_MAX_NOBOOST
#if STM32_PWR_BOOST || defined(__DOXYGEN__)
#define STM32_SYSCLK_MAX STM32_BOOST_SYSCLK_MAX
#define STM32_HSECLK_MAX STM32_BOOST_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_BOOST_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_BOOST_HSECLK_MIN
#define STM32_HSECLK_BYP_MIN STM32_BOOST_HSECLK_BYP_MIN
#define STM32_LSECLK_MAX STM32_BOOST_LSECLK_MAX
#define STM32_LSECLK_BYP_MAX STM32_BOOST_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_BOOST_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_BOOST_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_BOOST_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_BOOST_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_BOOST_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_BOOST_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_BOOST_PLLP_MAX
#define STM32_PLLP_MIN STM32_BOOST_PLLP_MIN
#define STM32_PLLQ_MAX STM32_BOOST_PLLQ_MAX
#define STM32_PLLQ_MIN STM32_BOOST_PLLQ_MIN
#define STM32_PLLR_MAX STM32_BOOST_PLLR_MAX
#define STM32_PLLR_MIN STM32_BOOST_PLLR_MIN
#define STM32_PCLK1_MAX STM32_BOOST_PCLK1_MAX
#define STM32_PCLK2_MAX STM32_BOOST_PCLK2_MAX
#define STM32_ADCCLK_MAX STM32_BOOST_ADCCLK_MAX
#define STM32_0WS_THRESHOLD STM32_BOOST_0WS_THRESHOLD
#define STM32_1WS_THRESHOLD STM32_BOOST_1WS_THRESHOLD
#define STM32_2WS_THRESHOLD STM32_BOOST_2WS_THRESHOLD
#define STM32_3WS_THRESHOLD STM32_BOOST_3WS_THRESHOLD
#define STM32_4WS_THRESHOLD STM32_BOOST_4WS_THRESHOLD
#define STM32_5WS_THRESHOLD STM32_BOOST_5WS_THRESHOLD
#define STM32_6WS_THRESHOLD STM32_BOOST_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_BOOST_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_BOOST_8WS_THRESHOLD
#else /* !STM32_PWR_BOOST */
#define STM32_SYSCLK_MAX STM32_VOS1_SYSCLK_MAX_NOBOOST
#define STM32_HSECLK_MAX STM32_VOS1_HSECLK_MAX
#define STM32_HSECLK_BYP_MAX STM32_VOS1_HSECLK_BYP_MAX
#define STM32_HSECLK_MIN STM32_VOS1_HSECLK_MIN
@ -765,6 +836,7 @@
#define STM32_6WS_THRESHOLD STM32_VOS1_6WS_THRESHOLD
#define STM32_7WS_THRESHOLD STM32_VOS1_7WS_THRESHOLD
#define STM32_8WS_THRESHOLD STM32_VOS1_8WS_THRESHOLD
#endif /* !STM32_PWR_BOOST */
#elif STM32_VOS == STM32_VOS_RANGE2
#define STM32_SYSCLK_MAX STM32_VOS2_SYSCLK_MAX
@ -1477,44 +1549,32 @@
/**
* @brief Voltage boost settings.
*/
#if (STM32_SYSCLK > STM32_SYSCLK_MAX_NOBOOST) || defined(__DOXYGEN__)
#define STM32_CR5BITS 0
#else
#if STM32_PWR_BOOST || defined(__DOXYGEN__)
#define STM32_CR5BITS PWR_CR5_R1MODE
#else
#define STM32_CR5BITS 0U
#endif
/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0
#elif STM32_HCLK <= STM32_1WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
#elif STM32_HCLK <= STM32_2WS_THRESHOLD
#elif STM32_HCLK <= STM32_1WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
#elif STM32_HCLK <= STM32_3WS_THRESHOLD
#elif STM32_HCLK <= STM32_2WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
#elif STM32_HCLK <= STM32_4WS_THRESHOLD
#elif STM32_HCLK <= STM32_3WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
#elif STM32_HCLK <= STM32_5WS_THRESHOLD
#elif STM32_HCLK <= STM32_4WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
#elif STM32_HCLK <= STM32_6WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_5WS
#elif STM32_HCLK <= STM32_7WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_6WS
#elif STM32_HCLK <= STM32_8WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_7WS
#else
#define STM32_FLASHBITS FLASH_ACR_LATENCY_8WS
#define STM32_FLASHBITS FLASH_ACR_LATENCY_5WS
#endif
/*===========================================================================*/
@ -1545,6 +1605,7 @@ typedef struct {
uint32_t rcc_cfgr;
uint32_t rcc_pllcfgr;
uint32_t flash_acr;
uint32_t rcc_crrcr;
} halclkcfg_t;
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */