Merged LTDC DMA2D code in STM32F4xx HAL.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8052 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
c798558914
commit
90527794f0
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@ -63,8 +63,8 @@
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#define GPIOA_LCD_G2 6U
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#define GPIOA_ACP_RST 7U
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#define GPIOA_I2C3_SCL 8U
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#define GPIOA_PIN9 9U
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#define GPIOA_PIN10 10U
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#define GPIOA_UART_TX 9U
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#define GPIOA_UART_RX 10U
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#define GPIOA_LCD_R4 11U
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#define GPIOA_LCD_R5 12U
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#define GPIOA_SWDIO 13U
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@ -241,8 +241,8 @@
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* PA6 - LCD_G2 (alternate 14).
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* PA7 - ACP_RST (input pullup).
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* PA8 - I2C3_SCL (alternate 4).
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* PA9 - PIN9 (input pullup).
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* PA10 - PIN10 (input pullup).
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* PA9 - UART_TX (alternate 7).
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* PA10 - UART_RX (alternate 7).
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* PA11 - LCD_R4 (alternate 14).
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* PA12 - LCD_R5 (alternate 14).
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* PA13 - SWDIO (alternate 0).
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@ -258,8 +258,8 @@
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PIN_MODE_ALTERNATE(GPIOA_LCD_G2) | \
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PIN_MODE_INPUT(GPIOA_ACP_RST) | \
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PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) | \
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PIN_MODE_INPUT(GPIOA_PIN9) | \
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PIN_MODE_INPUT(GPIOA_PIN10) | \
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PIN_MODE_ALTERNATE(GPIOA_UART_TX) | \
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PIN_MODE_ALTERNATE(GPIOA_UART_RX) | \
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PIN_MODE_ALTERNATE(GPIOA_LCD_R4) | \
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PIN_MODE_ALTERNATE(GPIOA_LCD_R5) | \
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PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
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@ -274,8 +274,8 @@
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PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) | \
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PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) | \
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PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
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PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
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PIN_OTYPE_PUSHPULL(GPIOA_UART_TX) | \
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PIN_OTYPE_PUSHPULL(GPIOA_UART_RX) | \
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PIN_OTYPE_PUSHPULL(GPIOA_LCD_R4) | \
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PIN_OTYPE_PUSHPULL(GPIOA_LCD_R5) | \
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PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
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@ -290,8 +290,8 @@
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PIN_OSPEED_100M(GPIOA_LCD_G2) | \
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PIN_OSPEED_2M(GPIOA_ACP_RST) | \
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PIN_OSPEED_100M(GPIOA_I2C3_SCL) | \
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PIN_OSPEED_2M(GPIOA_PIN9) | \
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PIN_OSPEED_2M(GPIOA_PIN10) | \
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PIN_OSPEED_2M(GPIOA_UART_TX) | \
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PIN_OSPEED_2M(GPIOA_UART_RX) | \
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PIN_OSPEED_100M(GPIOA_LCD_R4) | \
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PIN_OSPEED_100M(GPIOA_LCD_R5) | \
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PIN_OSPEED_100M(GPIOA_SWDIO) | \
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@ -306,8 +306,8 @@
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PIN_PUPDR_FLOATING(GPIOA_LCD_G2) | \
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PIN_PUPDR_PULLUP(GPIOA_ACP_RST) | \
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PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) | \
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PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
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PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
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PIN_PUPDR_PULLUP(GPIOA_UART_TX) | \
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PIN_PUPDR_PULLUP(GPIOA_UART_RX) | \
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PIN_PUPDR_FLOATING(GPIOA_LCD_R4) | \
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PIN_PUPDR_FLOATING(GPIOA_LCD_R5) | \
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PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
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@ -322,8 +322,8 @@
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PIN_ODR_HIGH(GPIOA_LCD_G2) | \
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PIN_ODR_HIGH(GPIOA_ACP_RST) | \
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PIN_ODR_HIGH(GPIOA_I2C3_SCL) | \
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PIN_ODR_HIGH(GPIOA_PIN9) | \
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PIN_ODR_HIGH(GPIOA_PIN10) | \
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PIN_ODR_HIGH(GPIOA_UART_TX) | \
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PIN_ODR_HIGH(GPIOA_UART_RX) | \
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PIN_ODR_HIGH(GPIOA_LCD_R4) | \
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PIN_ODR_HIGH(GPIOA_LCD_R5) | \
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PIN_ODR_HIGH(GPIOA_SWDIO) | \
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@ -338,8 +338,8 @@
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PIN_AFIO_AF(GPIOA_LCD_G2, 14) | \
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PIN_AFIO_AF(GPIOA_ACP_RST, 0))
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#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4) | \
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PIN_AFIO_AF(GPIOA_PIN9, 0) | \
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PIN_AFIO_AF(GPIOA_PIN10, 0) | \
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PIN_AFIO_AF(GPIOA_UART_TX, 7) | \
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PIN_AFIO_AF(GPIOA_UART_RX, 7) | \
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PIN_AFIO_AF(GPIOA_LCD_R4, 14) | \
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PIN_AFIO_AF(GPIOA_LCD_R5, 14) | \
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PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
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@ -824,10 +824,10 @@
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* PF4 - FMC_A4 (alternate 12).
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* PF5 - FMC_A5 (alternate 12).
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* PF6 - PIN6 (input pullup).
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* PF7 - LCD_DCX (output pushpull maximum).
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* PF7 - LCD_DCX (alternate 5).
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* PF8 - SPI5_MISO (alternate 5).
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* PF9 - SPI5_MOSI (alternate 5).
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* PF10 - LCD_DE (output pushpull maximum).
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* PF10 - LCD_DE (alternate 14).
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* PF11 - FMC_SDNRAS (alternate 12).
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* PF12 - FMC_A6 (alternate 12).
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* PF13 - FMC_A7 (alternate 12).
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@ -841,10 +841,10 @@
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PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \
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PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \
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PIN_MODE_INPUT(GPIOF_PIN6) | \
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PIN_MODE_OUTPUT(GPIOF_LCD_DCX) | \
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PIN_MODE_ALTERNATE(GPIOF_LCD_DCX) | \
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PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \
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PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \
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PIN_MODE_OUTPUT(GPIOF_LCD_DE) | \
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PIN_MODE_ALTERNATE(GPIOF_LCD_DE) | \
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PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \
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PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \
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PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \
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@ -921,10 +921,10 @@
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PIN_AFIO_AF(GPIOF_FMC_A4, 12) | \
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PIN_AFIO_AF(GPIOF_FMC_A5, 12) | \
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PIN_AFIO_AF(GPIOF_PIN6, 0) | \
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PIN_AFIO_AF(GPIOF_LCD_DCX, 0))
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PIN_AFIO_AF(GPIOF_LCD_DCX, 5))
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#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5) | \
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PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5) | \
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PIN_AFIO_AF(GPIOF_LCD_DE, 0) | \
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PIN_AFIO_AF(GPIOF_LCD_DE, 14) | \
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PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12) | \
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PIN_AFIO_AF(GPIOF_FMC_A6, 12) | \
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PIN_AFIO_AF(GPIOF_FMC_A7, 12) | \
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@ -93,21 +93,21 @@
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Mode="Alternate"
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Alternate="4" />
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<pin9
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ID=""
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ID="UART_TX"
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Type="PushPull"
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Speed="Minimum"
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Resistor="PullUp"
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Level="High"
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Mode="Input"
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Alternate="0" />
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Mode="Alternate"
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Alternate="7" />
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<pin10
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ID=""
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ID="UART_RX"
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Type="PushPull"
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Speed="Minimum"
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Resistor="PullUp"
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Level="High"
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Mode="Input"
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Alternate="0" />
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Mode="Alternate"
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Alternate="7" />
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<pin11
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ID="LCD_R4"
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Type="PushPull"
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@ -732,8 +732,8 @@
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Speed="Maximum"
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Resistor="Floating"
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Level="High"
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Mode="Output"
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Alternate="0" />
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Mode="Alternate"
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Alternate="5" />
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<pin8
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ID="SPI5_MISO"
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Type="PushPull"
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@ -756,8 +756,8 @@
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Speed="Maximum"
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Resistor="Floating"
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Level="High"
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Mode="Output"
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Alternate="0" />
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Mode="Alternate"
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Alternate="14" />
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<pin11
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ID="FMC_SDNRAS"
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Type="PushPull"
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@ -190,6 +190,15 @@
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/*===========================================================================*/
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/* STM32F071xB, STM32F072xB, STM32F078xx. */
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/*===========================================================================*/
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@ -362,6 +371,15 @@
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/*===========================================================================*/
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/* STM32F048xx. */
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/*===========================================================================*/
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@ -505,6 +523,15 @@
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/*===========================================================================*/
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/* STM32F031x6, STM32F038xx. */
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/*===========================================================================*/
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@ -646,6 +673,15 @@
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/*===========================================================================*/
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/* STM32F042x6. */
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/*===========================================================================*/
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@ -785,6 +821,15 @@
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/*===========================================================================*/
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/* STM32F030x6, STM32F030x8. */
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/*===========================================================================*/
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@ -935,6 +980,15 @@
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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#else
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#error "STM32F0xx device not specified"
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#endif
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@ -173,6 +173,15 @@
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_LD_VL) */
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@ -332,6 +341,15 @@
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_MD_VL) */
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@ -460,6 +478,15 @@
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_LD) */
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@ -603,6 +630,15 @@
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#define STM32_USB_HAS_BCDR FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_MD) */
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@ -786,6 +822,15 @@
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#define STM32_USB_HAS_BCDR FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_HD) */
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@ -969,6 +1014,15 @@
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#define STM32_USB_HAS_BCDR FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_XL) */
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@ -1129,6 +1183,15 @@
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 TRUE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/** @} */
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#endif /* defined(STM32F10X_CL) */
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@ -219,6 +219,15 @@
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#define STM32_USB_HAS_BCDR FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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#endif /* defined(STM32F373xC) */
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/*===========================================================================*/
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@ -406,6 +415,15 @@
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#define STM32_USB_PMA_SIZE 512
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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#endif /* defined(STM32F378xx) */
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/** @} */
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@ -216,6 +216,15 @@
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#define STM32_USB_HAS_BCDR FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F303xC) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -376,6 +385,15 @@
|
|||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F303x8) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -531,6 +549,15 @@
|
|||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F301x8) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -689,6 +716,15 @@
|
|||
#define STM32_USB_HAS_BCDR FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F302x8) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -859,6 +895,15 @@
|
|||
#define STM32_USB_HAS_BCDR FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F302xC) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -1013,6 +1058,15 @@
|
|||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F318x8) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -1170,6 +1224,15 @@
|
|||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F328x8) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -1342,6 +1405,15 @@
|
|||
#define STM32_USB_HAS_BCDR FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F358xC) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -1499,6 +1571,15 @@
|
|||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F334x8) */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -232,6 +232,17 @@ void stm32_clock_init(void) {
|
|||
;
|
||||
#endif
|
||||
|
||||
#if STM32_ACTIVATE_PLLSAI
|
||||
/* PLLSAI activation.*/
|
||||
RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
|
||||
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
|
||||
RCC->CR |= RCC_CR_PLLSAION;
|
||||
|
||||
/* Waiting for PLL lock.*/
|
||||
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
|
||||
;
|
||||
#endif
|
||||
|
||||
/* Other clock-related settings (dividers, MCO etc).*/
|
||||
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
|
||||
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
|
|
|||
|
|
@ -362,6 +362,13 @@
|
|||
#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
|
||||
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
|
||||
|
||||
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
|
||||
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
|
||||
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
|
||||
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
|
||||
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
|
||||
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
|
||||
|
||||
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
|
||||
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
|
||||
#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
|
||||
|
|
@ -1278,6 +1285,52 @@
|
|||
#error "invalid STM32_PLLI2SR_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLLSAI enable check.
|
||||
*/
|
||||
#if !defined(STM32_SAISRC)
|
||||
#define STM32_SAISRC STM32_SAISRC_NOCLOCK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL activation flag.
|
||||
*/
|
||||
#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)
|
||||
#define STM32_ACTIVATE_PLLSAI TRUE
|
||||
#else
|
||||
#define STM32_ACTIVATE_PLLSAI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLSAIN field.
|
||||
*/
|
||||
#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
|
||||
#else
|
||||
#error "invalid STM32_PLLSAIN_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLSAIQ field.
|
||||
*/
|
||||
#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
|
||||
#else
|
||||
#error "invalid STM32_PLLSAIR_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLSAIR field.
|
||||
*/
|
||||
#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
|
||||
#else
|
||||
#error "invalid STM32_PLLSAIR_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL VCO frequency.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -158,6 +158,22 @@
|
|||
|
||||
#define STM32_FSMC_NUMBER 48
|
||||
|
||||
/*
|
||||
* LTDC
|
||||
*/
|
||||
#define STM32_LTDC_EV_HANDLER Vector1A0
|
||||
#define STM32_LTDC_ER_HANDLER Vector1A4
|
||||
|
||||
#define STM32_LTDC_EV_NUMBER 88
|
||||
#define STM32_LTDC_ER_NUMBER 89
|
||||
|
||||
/*
|
||||
* DMA2D
|
||||
*/
|
||||
#define STM32_DMA2D_HANDLER Vector1A8
|
||||
|
||||
#define STM32_DMA2D_NUMBER 90
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
|
|
@ -1467,6 +1467,36 @@
|
|||
*/
|
||||
#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
|
||||
|
||||
/**
|
||||
* @name DMA2D peripheral specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the DMA2D peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the DMA2D peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the DMA2D peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name FSMC peripherals specific RCC operations
|
||||
* @{
|
||||
|
|
|
|||
|
|
@ -322,6 +322,12 @@
|
|||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC TRUE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D TRUE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_IS_FMC TRUE
|
||||
|
|
@ -334,6 +340,7 @@
|
|||
STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
|
||||
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -591,6 +598,12 @@
|
|||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
|
|
@ -602,6 +615,7 @@
|
|||
STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
|
||||
#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -815,8 +829,15 @@
|
|||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
#endif /* defined(STM32F401xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -1029,8 +1050,15 @@
|
|||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
|
|
|
|||
|
|
@ -190,6 +190,15 @@
|
|||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
#else /* STM32L1XX_HD */
|
||||
|
||||
/* ADC attributes.*/
|
||||
|
|
@ -355,6 +364,15 @@
|
|||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
#endif /* STM32L1XX_HD */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
Loading…
Reference in New Issue