git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4896 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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dcf8830c45
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90d2c48354
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@ -31,6 +31,12 @@
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#define BOARD_ATMEL_SAM4L_EK
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#define BOARD_NAME "Atmel SAM4L-EK"
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/*
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* Clock sources.
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*/
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#define SAM_OSC32K_CLK 32768
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#define SAM_OSC0_CLK 12000000
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/*
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* Device identifier.
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*/
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@ -121,6 +121,23 @@ void sam_clock_init(void) {
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SAM_PM_UNLOCK((uint32_t)&PM->PM_PBDSEL);
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PM->PM_PBDSEL = SAM_PBDSEL;
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/* Switching to the selected clock source, enabling it if necessary.*/
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RCSYS
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/* Nothing to do, already running from SYSIRC.*/
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_OSC0
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_PLL
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_DFLL
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RC80M
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RCFAST
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#endif
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#if SAM_MCCTRL_MCSEL == SAM_MCSEL_RC1M
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#endif
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#endif /* SAM_NO_INIT */
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}
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@ -21,6 +21,13 @@
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/**
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* @file templates/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SAM_OSC32K_CLK.
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* - SAM_OSC32K_MODE_EXT (optional)
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* - SAM_OSC0_CLK.
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* - SAM_OSC0_MODE_EXT (optional)
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* .
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*
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* @addtogroup HAL
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* @{
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@ -45,6 +52,19 @@
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*/
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#define PLATFORM_NAME "SAM4L Series"
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/**
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* @name Internal clock sources
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* @{
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*/
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#define SAM_RC32K_CLK 32768
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#define SAM_RCSYS_CLK 115000
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#define SAM_RC1M_CLK 1000000
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#define SAM_RCFAST0_CLK 4000000
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#define SAM_RCFAST1_CLK 8000000
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#define SAM_RCFAST2_CLK 12000000
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#define SAM_RC80M_CLK 80000000
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/** @} */
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/**
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* @name BUS IDs
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* @{
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@ -185,6 +205,23 @@
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#define SAM_PBDIV (1 << 7) /**< PBDIV bit. */
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/** @} */
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/**
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* @name RCFASTCFG registers bits definitions
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* @{
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*/
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#define SAM_RCFASTCFG_FRANGE_4M 0x00000000
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#define SAM_RCFASTCFG_FRANGE_8M 0x00000100
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#define SAM_RCFASTCFG_FRANGE_12M 0x00000200
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/** @} */
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/**
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* @name PMCON registers bits definitions
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* @{
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*/
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#define SAM_PMCON_PS0 (0 << 0)
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#define SAM_PMCON_PS1 (1 << 0)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -200,6 +237,13 @@
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#define SAM_NO_INIT FALSE
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#endif
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/**
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* @brief Power mode.
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*/
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#if !defined(SAM_PMCON_PS) || defined(__DOXYGEN__)
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#define SAM_PMCON_PS SAM_PMCON_PS0
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#endif
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/**
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* @brief MCCTRL register settings.
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*/
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@ -242,12 +286,225 @@
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#define SAM_PBDSEL SAM_PBSEL_DIV1
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#endif
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/**
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* @brief PBDSEL register settings.
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*/
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#if !defined(SAM_PBDSEL) || defined(__DOXYGEN__)
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#define SAM_RCFAST_FRANGE SAM_RCFASTCFG_FRANGE_4M
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/**
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* @name Clock limits depending on power scaling mode
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* @{
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*/
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#if (SAM_PMCON_PS == SAM_PMCON_PS0)|| defined(__DOXYGEN__)
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#define SAM_CPUCLK_MAX 50000000
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#define SAM_PBACLK_MAX 50000000
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#define SAM_PBBCLK_MAX 50000000
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#define SAM_PBCCLK_MAX 50000000
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#define SAM_PBDCLK_MAX 50000000
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#elif SAM_PMCON_PS == SAM_PMCON_PS1
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#define SAM_CPUCLK_MAX 12000000
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#define SAM_PBACLK_MAX 12000000
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#define SAM_PBBCLK_MAX 12000000
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#define SAM_PBCCLK_MAX 12000000
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#define SAM_PBDCLK_MAX 12000000
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#else
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#error "invalid SAM_PMCON_PS value specified"
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#endif
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/** @} */
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/**
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* @brief Selected RCFAST clock frequency.
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*/
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#if (SAM_RCFAST_FRANGE == SAM_RCFASTCFG_FRANGE_4M)|| defined(__DOXYGEN__)
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#define SAM_RCFAST_CLK SAM_RCFAST0_CLK
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#elif SAM_RCFAST_FRANGE == SAM_RCFASTCFG_FRANGE_8M
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#define SAM_RCFAST_CLK SAM_RCFAST1_CLK
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#elif SAM_RCFAST_FRANGE == SAM_RCFASTCFG_FRANGE_12M
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#define SAM_RCFAST_CLK SAM_RCFAST2_CLK
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#else
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#error "invalid SAM_RCFAST_FRANGE value specified"
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#endif
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/**
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* @brief Selected main clock frequency.
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*/
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#if (SAM_MCCTRL_MCSEL == SAM_MCSEL_RCSYS) || defined(__DOXYGEN__)
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#define SAM_MAIN_CLK SAM_RCSYS_CLK
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#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_OSC0
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#define SAM_MAIN_CLK SAM_OSC0_CLK
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#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_PLL
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#define SAM_MAIN_CLK 0
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#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_DFLL
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#define SAM_MAIN_CLK 0
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#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_RC80M
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#define SAM_MAIN_CLK SAM_RC80M_CLK
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#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_RCFAST
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#define SAM_MAIN_CLK SAM_RCFAST_CLK
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#elif SAM_MCCTRL_MCSEL == SAM_MCSEL_RC1M
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#define SAM_MAIN_CLK SAM_RC1M_CLK
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#else
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#error "invalid SAM_MCCTRL_MCSEL value specified"
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#endif
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/**
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* @brief CPU clock.
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*/
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#if (SAM_CPUSEL == SAM_CPUSEL_DIV1) || defined(__DOXYGEN__)
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 1)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV2
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 2)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV4
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 4)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV8
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 8)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV16
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 16)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV32
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 32)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV64
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 64)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV128
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 128)
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#elif SAM_CPUSEL == SAM_CPUSEL_DIV256
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#define SAM_CPU_CLK (SAM_MAIN_CLK / 256)
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#else
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#error "invalid SAM_CPUSEL value specified"
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#endif
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/* CPU clock check.*/
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#if SAM_CPU_CLK > SAM_CPUCLK_MAX
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#error "SAM_CPU_CLK above maximum rated frequency (SAM_CPUCLK_MAX)"
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#endif
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/**
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* @brief PBA clock.
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*/
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#if (SAM_PBASEL == SAM_PBASEL_DIV1) || defined(__DOXYGEN__)
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 1)
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#elif SAM_PBASEL == SAM_PBASEL_DIV2
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 2)
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#elif SAM_PBASEL == SAM_PBASEL_DIV4
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 4)
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#elif SAM_PBASEL == SAM_PBASEL_DIV8
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 8)
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#elif SAM_PBASEL == SAM_PBASEL_DIV16
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 16)
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#elif SAM_PBASEL == SAM_PBASEL_DIV32
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 32)
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#elif SAM_PBASEL == SAM_PBASEL_DIV64
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 64)
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#elif SAM_PBASEL == SAM_PBASEL_DIV128
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 128)
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#elif SAM_PBASEL == SAM_PBASEL_DIV256
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#define SAM_PBA_CLK (SAM_MAIN_CLK / 256)
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#else
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#error "invalid SAM_PBASEL value specified"
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#endif
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/* PBA clock check.*/
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#if SAM_PBA_CLK > SAM_PBACLK_MAX
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#error "SAM_PBA_CLK above maximum rated frequency (SAM_PBACLK_MAX)"
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#endif
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/**
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* @brief PBB clock.
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*/
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#if (SAM_PBBSEL == SAM_PBBSEL_DIV1) || defined(__DOXYGEN__)
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 1)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV2
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 2)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV4
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 4)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV8
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 8)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV16
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 16)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV32
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 32)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV64
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 64)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV128
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 128)
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#elif SAM_PBBSEL == SAM_PBBSEL_DIV256
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#define SAM_PBB_CLK (SAM_MAIN_CLK / 256)
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#else
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#error "invalid SAM_PBBSEL value specified"
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#endif
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/* PBB clock check.*/
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#if SAM_PBB_CLK > SAM_PBBCLK_MAX
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#error "SAM_PBB_CLK above maximum rated frequency (SAM_PBBCLK_MAX)"
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#endif
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/**
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* @brief PBC clock.
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*/
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#if (SAM_PBCSEL == SAM_PBCSEL_DIV1) || defined(__DOXYGEN__)
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 1)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV2
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 2)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV4
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 4)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV8
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 8)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV16
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 16)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV32
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 32)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV64
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 64)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV128
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 128)
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#elif SAM_PBCSEL == SAM_PBCSEL_DIV256
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#define SAM_PBC_CLK (SAM_MAIN_CLK / 256)
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#else
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#error "invalid SAM_PBCSEL value specified"
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#endif
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/* PBC clock check.*/
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#if SAM_PBC_CLK > SAM_PBCCLK_MAX
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#error "SAM_PBC_CLK above maximum rated frequency (SAM_PBCCLK_MAX)"
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#endif
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/**
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* @brief PBD clock.
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*/
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#if (SAM_PBDSEL == SAM_PBDSEL_DIV1) || defined(__DOXYGEN__)
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 1)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV2
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 2)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV4
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 4)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV8
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 8)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV16
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 16)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV32
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 32)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV64
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 64)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV128
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 128)
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#elif SAM_PBDSEL == SAM_PBDSEL_DIV256
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#define SAM_PBD_CLK (SAM_MAIN_CLK / 256)
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#else
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#error "invalid SAM_PBDSEL value specified"
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#endif
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/* PBD clock check.*/
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#if SAM_PBD_CLK > SAM_PBDCLK_MAX
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#error "SAM_PBD_CLK above maximum rated frequency (SAM_PBDCLK_MAX)"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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