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STM32WL port: added CM0+ core support, fixed ADC driver version, fixed typos. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14616 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-07-25 06:48:57 +00:00
parent 54b5383a6d
commit 91e6d923a2
20 changed files with 1281 additions and 347 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
demos/STM32/RT-STM32WL55JC-NUCLEO64/Makefile
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@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb3 -fomit-frame-pointer -falign-functions=16 -fvar-tracking -fvar-tracking-assignments
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -fvar-tracking -fvar-tracking-assignments
endif
# C specific options here (added to USE_OPT).
@ -30,7 +30,7 @@ endif
# Enable this if you want link time optimizations (LTO).
ifeq ($(USE_LTO),)
USE_LTO = no
USE_LTO = yes
endif
# Enable this if you want to see the full log while compiling.

2
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h
View File

@ -38,6 +38,7 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0 | PWR_CR2_PVDE)
#define STM32_PWR_PUCRA (0U)
@ -66,6 +67,7 @@
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI

18
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32wlxx-m0plus.mk Normal file
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@ -0,0 +1,18 @@
# List of the ChibiOS generic STM32WLxx startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32WLxx-M0PLUS \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS)/os/common/ext/ST/STM32WLxx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

94
os/common/startup/ARMCMx/devices/STM32WLxx-M0PLUS/cmparams.h Normal file
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@ -0,0 +1,94 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/cmparams.h
* @brief ARM Cortex-M0+ parameters for the STM32WLxx.
*
* @defgroup ARMCMx_STM32WLxx STM32WLxx Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0+ specific parameters for the
* STM32L4xx platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0U
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/* If the device type is not externally defined, for example from the Makefile,
then a file named board.h is included. This file must contain a device
definition compatible with the vendor include file.*/
#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && \
!defined (STM32WLE5xx) && !defined (STM32WLE4xx)
#include "board.h"
#endif
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/* Define the core to be used.*/
#define CORE_CM0PLUS
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "stm32wlxx.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_HAS_FPU != __FPU_PRESENT
#error "CMSIS __FPU_PRESENT mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

12
os/common/startup/ARMCMx/devices/STM32WLxx/cmparams.h
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@ -16,13 +16,13 @@
*/
/**
* @file STM32L4xx/cmparams.h
* @brief ARM Cortex-M4 parameters for the STM32L4xx.
* @file STM32WLxx/cmparams.h
* @brief ARM Cortex-M4 parameters for the STM32WLxx.
*
* @defgroup ARMCMx_STM32L4xx STM32L4xx Specific Parameters
* @defgroup ARMCMx_STM32WLxx STM32WLxx Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M4 specific parameters for the
* STM32L4xx platform.
* STM32WLxx platform.
* @{
*/
@ -47,8 +47,8 @@
/* If the device type is not externally defined, for example from the Makefile,
then a file named board.h is included. This file must contain a device
definition compatible with the vendor include file.*/
#if !defined(STM32WLE5Cx) && !defined(STM32WLE5Jx) && !defined(STM32WLE5Ux) && \
!defined(STM32WLE4Cx) && !defined(STM32WLE4Jx) && !defined(STM32WLE4Ux)
#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && \
!defined (STM32WLE5xx) && !defined (STM32WLE4xx)
#include "board.h"
#endif

81
os/hal/ports/STM32/LLD/DMAv1/stm32_dma1_ch123.inc Normal file
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@ -0,0 +1,81 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file DMAv1/stm32_dma1_ch123.inc
* @brief Shared DMA1 Channels 1, 2 and 3 handler.
*
* @addtogroup STM32_DMA1_CH123_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Other checks.*/
#if !defined(STM32_DMA1_CH123_HANDLER)
#error "STM32_DMA1_CH123_HANDLER not defined in stm32_isr.h"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief DMA1 streams 1, 2 and 3 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA1_CH123_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 1.*/
dmaServeInterrupt(STM32_DMA1_STREAM2);
/* Check on channel 2.*/
dmaServeInterrupt(STM32_DMA1_STREAM2);
/* Check on channel 3.*/
dmaServeInterrupt(STM32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

93
os/hal/ports/STM32/LLD/DMAv1/stm32_dma2_ch1-7.inc Normal file
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@ -0,0 +1,93 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file DMAv1/stm32_dma2_ch1-7.inc
* @brief Shared DMA2 Channels 1 - 7 handler.
*
* @addtogroup STM32_DMA2_CH1_7_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Other checks.*/
#if !defined(STM32_DMA2_CH1_7_HANDLER)
#error "STM32_DMA2_CH1_7_HANDLER not defined in stm32_isr.h"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief DMA2 streams 1 - 7 shared ISR.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_DMA2_CH1_7_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 1.*/
dmaServeInterrupt(STM32_DMA2_STREAM3);
/* Check on channel 2.*/
dmaServeInterrupt(STM32_DMA2_STREAM3);
/* Check on channel 3.*/
dmaServeInterrupt(STM32_DMA2_STREAM3);
/* Check on channel 4.*/
dmaServeInterrupt(STM32_DMA2_STREAM4);
/* Check on channel 5.*/
dmaServeInterrupt(STM32_DMA2_STREAM5);
/* Check on channel 6.*/
dmaServeInterrupt(STM32_DMA2_STREAM6);
/* Check on channel 7.*/
dmaServeInterrupt(STM32_DMA2_STREAM7);
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

147
os/hal/ports/STM32/LLD/RCCv1/stm32_c2ahb.inc Normal file
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@ -0,0 +1,147 @@
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_c2ahb.inc
* @brief Shared Core 2 AHB clock handler.
*
* @addtogroup STM32_C2AHB_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @name C2HPRE field bits definitions
* @{
*/
#define STM32_C2HPRE_MASK (15U << RCC_EXTCFGR_C2HPRE_Pos)
#define STM32_C2HPRE_FIELD(n) ((n) << RCC_EXTCFGR_C2HPRE_Pos)
#define STM32_C2HPRE_DIV1 STM32_C2HPRE_FIELD(0U)
#define STM32_C2HPRE_DIV2 STM32_C2HPRE_FIELD(8U)
#define STM32_C2HPRE_DIV3 STM32_C2HPRE_FIELD(1U)
#define STM32_C2HPRE_DIV4 STM32_C2HPRE_FIELD(9U)
#define STM32_C2HPRE_DIV5 STM32_C2HPRE_FIELD(2U)
#define STM32_C2HPRE_DIV6 STM32_C2HPRE_FIELD(5U)
#define STM32_C2HPRE_DIV8 STM32_C2HPRE_FIELD(10U)
#define STM32_C2HPRE_DIV10 STM32_C2HPRE_FIELD(6U)
#define STM32_C2HPRE_DIV16 STM32_C2HPRE_FIELD(11U)
#define STM32_C2HPRE_DIV32 STM32_C2HPRE_FIELD(7U)
#define STM32_C2HPRE_DIV64 STM32_C2HPRE_FIELD(12U)
#define STM32_C2HPRE_DIV128 STM32_C2HPRE_FIELD(13U)
#define STM32_C2HPRE_DIV256 STM32_C2HPRE_FIELD(14U)
#define STM32_C2HPRE_DIV512 STM32_C2HPRE_FIELD(15U)
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
/* Checks on configurations.*/
#if !defined(STM32_C2HPRE)
#error "STM32_C2HPRE not defined in mcuconf.h"
#endif
/* Input checks.*/
#if !defined(STM32_SYSCLK_MAX)
#error "STM32_SYSCLK_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_SYSCLK)
#error "STM32_SYSCLK not defined in hal_lld.h"
#endif
/**
* @brief HCLK2 frequency.
*/
#if (STM32_C2HPRE == STM32_C2HPRE_DIV1) || defined(__DOXYGEN__)
#define STM32_HCLK2 (STM32_SYSCLK / 1)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV2
#define STM32_HCLK2 (STM32_SYSCLK / 2)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV4
#define STM32_HCLK2 (STM32_SYSCLK / 3)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV4
#define STM32_HCLK2 (STM32_SYSCLK / 4)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV5
#define STM32_HCLK2 (STM32_SYSCLK / 5)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV6
#define STM32_HCLK2 (STM32_SYSCLK / 6)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV8
#define STM32_HCLK2 (STM32_SYSCLK / 8)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV10
#define STM32_HCLK2 (STM32_SYSCLK / 10)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV16
#define STM32_HCLK2 (STM32_SYSCLK / 16)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV32
#define STM32_HCLK2 (STM32_SYSCLK / 32)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV64
#define STM32_HCLK2 (STM32_SYSCLK / 64)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV128
#define STM32_HCLK2 (STM32_SYSCLK / 128)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV256
#define STM32_HCLK2 (STM32_SYSCLK / 256)
#elif STM32_C2HPRE == STM32_C2HPRE_DIV512
#define STM32_HCLK2 (STM32_SYSCLK / 512)
#else
#error "invalid STM32_C2HPRE value specified"
#endif
/*
* HCLK2 frequency check.
*/
#if STM32_HCLK2 > STM32_SYSCLK_MAX
#error "STM32_HCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

24
os/hal/ports/STM32/LLD/RCCv1/stm32_hse32.inc
View File

@ -29,7 +29,7 @@
/**
* @brief HSE32 clock frequency.
*/
#define STM32_HSE32CLK 32000000
#define STM32_HSE32CLK 32000000U
/*===========================================================================*/
/* Derived constants and error checks. */
@ -53,18 +53,18 @@
#error "STM32_HSE_ENABLED should not be defined in mcuconf.h"
#endif
#if STM32_HSE32_ENABLED
/* HSE clock frequency.*/
#if STM32_HSE32PRE == STM32_HSE32PRE_DIV1
#define STM32_HSECLK STM32_HSE32CLK
#elif STM32_HSE32PRE == STM32_HSE32PRE_DIV2
#define STM32_HSECLK (STM32_HSE32CLK / 2)
#if STM32_HSE32_ENABLED
#if STM32_HSE32PRE == STM32_HSE32PRE_DIV1
#define STM32_HSECLK STM32_HSE32CLK
#elif STM32_HSE32PRE == STM32_HSE32PRE_DIV2
#define STM32_HSECLK (STM32_HSE32CLK / 2U)
#else
#error "invalid STM32_HSE32PRE value specified"
#endif
#else
#error "invalid STM32_HSE32PRE value specified"
#endif
#endif
#define STM32_HSECLK 0U
#endif /* STM32_HSE32_ENABLED */
/*===========================================================================*/
/* Driver exported variables. */
@ -86,7 +86,7 @@ __STATIC_INLINE void hse32_enable(void) {
/* HSE32 activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0) {
while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
/* Wait until HSE32 is stable. */
}
}

132
os/hal/ports/STM32/LLD/TIMv1/stm32_tim1_shared.inc Normal file
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@ -0,0 +1,132 @@
/*
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIMv1/stm32_tim1_shared.inc
* @brief Shared TIM1 shared handler.
*
* @addtogroup STM32_TIM1_SHARED_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM1)
#error "STM32_HAS_TIM1 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM1)
#define STM32_GPT_USE_TIM1 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM1)
#define STM32_ICU_USE_TIM1 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM1)
#define STM32_PWM_USE_TIM1 FALSE
#endif
#if !defined(STM32_ST_USE_TIM1)
#define STM32_ST_USE_TIM1 FALSE
#endif
#if STM32_HAS_TIM1
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM1_PRIORITY)
#error "STM32_IRQ_TIM1_PRIORITY not defined in mcuconf.h"
#endif
#endif /* STM32_HAS_TIM1 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim1_irq_init(void) {
#if defined(STM32_TIM1_IS_USED)
nvicEnableVector(STM32_TIM1_SHARED_NUMBER, STM32_IRQ_TIM1_PRIORITY);
#endif
}
static inline void tim1_irq_deinit(void) {
#if defined(STM32_TIM1_IS_USED)
nvicDisableVector(STM32_TIM1_SHARED_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM1_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM1 shared interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_TIM1_SHARED_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM1
if (0 != (TIM1->SR & TIM_SR_UIF)) {
st_lld_serve_interrupt();
}
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

31
os/hal/ports/STM32/STM32WLxx/hal_lld.c
View File

@ -36,12 +36,12 @@
/**
* @brief FLASH_ACR reset value.
*/
#define STM32_FLASH_ACR_RESET 0x00000600U
#define STM32_FLASH_ACR_RESET 0x00000600UL
/**
* @brief RCC_CR reset value.
*/
#define STM32_RCC_CR_RESET 0x00000061U
#define STM32_RCC_CR_RESET 0x00000061UL
/**
* @brief PWR CR bits safe for fast switch.
@ -105,7 +105,7 @@ const halclkcfg_t hal_clkcfg_default = {
.rcc_cfgr = STM32_MCOPRE | STM32_MCOSEL |
STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE | STM32_SW,
.rcc_extcfgr = STM32_SHDHPRE,
.rcc_extcfgr = STM32_SHDHPRE | STM32_C2HPRE,
.rcc_pllcfgr = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
@ -132,6 +132,7 @@ static halfreq_t clock_points[CLK_ARRAY_SIZE] = {
STM32_HCLK,
STM32_PCLK1,
STM32_TIMP1CLK,
STM32_HCLK2,
STM32_PCLK2,
STM32_TIMP2CLK,
STM32_HCLK3,
@ -201,6 +202,7 @@ static const system_limits_t vos_range2 = {
/* Driver local functions. */
/*===========================================================================*/
#if (STM32_NO_INIT == FALSE || defined(HAL_LLD_USE_CLOCK_MANAGEMENT)) || defined(__DOXYGEN__)
/**
* @brief Safe setting of flash ACR register.
*
@ -213,7 +215,9 @@ static void flash_set_acr(uint32_t acr) {
/* Waiting for flash wait states setup.*/
}
}
#endif /* (STM32_NO_INIT == TRUE || defined(HAL_LLD_USE_CLOCK_MANAGEMENT)) */
#if (STM32_NO_INIT == FALSE) || defined(__DOXYGEN__)
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
@ -243,7 +247,7 @@ static void hal_lld_set_static_clocks(void) {
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->EXTCFGR = STM32_SHDHPRE;
RCC->EXTCFGR = STM32_SHDHPRE | STM32_C2HPRE;
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
@ -254,6 +258,7 @@ static void hal_lld_set_static_clocks(void) {
RCC->CCIPR = ccipr;
}
#endif /* (STM32_NO_INIT == FALSE) */
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
static bool hal_lld_check_pll(const system_limits_t *slp,
@ -358,7 +363,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
halfreq_t hsi16clk = 0U, hseclk = 0U, msiclk = 0U, pllselclk;
halfreq_t pllpclk = 0U, pllqclk = 0U, pllrclk = 0U;
halfreq_t sysclk, hclk, pclk1, pclk2, pclk1tim, pclk2tim, hclk3, mcoclk;
halfreq_t sysclk, hclk, pclk1, pclk2, pclk1tim, pclk2tim, hclk2, hclk3, mcoclk;
uint32_t mcodiv;
uint32_t msiidx, flashws;
@ -436,7 +441,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
}
/* LPRUN sysclk check.*/
if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0) && (sysclk > STM32_LPRUN_SYSCLK_MAX) ) {
if (((ccp->pwr_cr1 & PWR_CR1_LPR_Msk) != 0U) && (sysclk > STM32_LPRUN_SYSCLK_MAX) ) {
return true;
}
@ -461,7 +466,10 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
pclk2tim = pclk2 * 2U;
}
/* HCLK3 frequncy.*/
/* HCLK2 frequency.*/
hclk2 = sysclk / hprediv[(ccp->rcc_extcfgr & RCC_EXTCFGR_C2HPRE_Msk) >> RCC_EXTCFGR_C2HPRE_Pos];
/* HCLK3 frequency.*/
hclk3 = sysclk / hprediv[(ccp->rcc_extcfgr & RCC_EXTCFGR_SHDHPRE_Msk) >> RCC_EXTCFGR_SHDHPRE_Pos];
/* MCO clock.*/
@ -526,6 +534,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
clock_points[CLK_HCLK] = hclk;
clock_points[CLK_PCLK1] = pclk1;
clock_points[CLK_PCLK1TIM] = pclk1tim;
clock_points[CLK_HCLK2] = hclk2;
clock_points[CLK_PCLK2] = pclk2;
clock_points[CLK_PCLK2TIM] = pclk2tim;
clock_points[CLK_HCLK3] = hclk3;
@ -672,14 +681,14 @@ void stm32_clock_init(void) {
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB1(~0UL);
rccResetAHB2(~STM32_GPIO_EN_MASK);
/* Reset all except FLASH.*/
rccResetAHB3(RCC_AHB3RSTR_PKARST | RCC_AHB3RSTR_AESRST |
RCC_AHB3RSTR_RNGRST | RCC_AHB3RSTR_HSEMRST);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
rccResetAPB1R1(~0UL);
rccResetAPB1R2(~0UL);
rccResetAPB2(~0UL);
/* RTC clock enable.*/
#if HAL_USE_RTC

349
os/hal/ports/STM32/STM32WLxx/hal_lld.h
View File

@ -76,29 +76,30 @@
#define CLK_HCLK 4U
#define CLK_PCLK1 5U
#define CLK_PCLK1TIM 6U
#define CLK_PCLK2 7U
#define CLK_PCLK2TIM 8U
#define CLK_HCLK3 9U
#define CLK_MCO 10U
#define CLK_ARRAY_SIZE 11U
#define CLK_HCLK2 7U
#define CLK_PCLK2 8U
#define CLK_PCLK2TIM 9U
#define CLK_HCLK3 10U
#define CLK_MCO 11U
#define CLK_ARRAY_SIZE 12U
/** @} */
/**
* @name HSE32 clock sources
* @{
*/
#define STM32_HSE32_XTAL 0 /**< External crystal. */
#define STM32_HSE32_TCXO 1 /**< TCXO. */
#define STM32_HSE32_EXTS 2 /**< External source. */
#define STM32_HSE32_XTAL 0U /**< External crystal. */
#define STM32_HSE32_TCXO 1U /**< TCXO. */
#define STM32_HSE32_EXTS 2U /**< External source. */
/** @} */
/**
* @name PWR_CR1 register bits definitions
* @{
*/
#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */
#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.2 Volts. */
#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.0 Volts. */
#define STM32_VOS_MASK (3U << 9) /**< Core voltage mask. */
#define STM32_VOS_RANGE1 (1U << 9) /**< Core voltage 1.2 Volts. */
#define STM32_VOS_RANGE2 (2U << 9) /**< Core voltage 1.0 Volts. */
/** @} */
/* Some ST headers do not have this definition.*/
@ -145,55 +146,55 @@
* @name PWR_CR4 register bits definitions
* @{
*/
#define STM32_VBRS_MASK (1 << 9) /**< VBRS field mask. */
#define STM32_VBRS_RES_5K (0 << 9) /**< VBRS 5k resistor. */
#define STM32_VBRS_RES_1K5 (1 << 9) /**< VBRS 1.5k resistor. */
#define STM32_VBE_MASK (1 << 8) /**< VBE field mask. */
#define STM32_VBE_RESET (0 << 8) /**< VBE reset. */
#define STM32_VBE_SET (1 << 8) /**< VBE set. */
#define STM32_VBRS_MASK (1U << 9) /**< VBRS field mask. */
#define STM32_VBRS_RES_5K (0U << 9) /**< VBRS 5k resistor. */
#define STM32_VBRS_RES_1K5 (1U << 9) /**< VBRS 1.5k resistor. */
#define STM32_VBE_MASK (1U << 8) /**< VBE field mask. */
#define STM32_VBE_RESET (0U << 8) /**< VBE reset. */
#define STM32_VBE_SET (1U << 8) /**< VBE set. */
/** @} */
/**
* @name RCC_CR register bits definitions
* @{
*/
#define STM32_HSE32PRE_MASK (1 << 20) /**< HSEPRE field mask. */
#define STM32_HSE32PRE_DIV1 (0 << 20) /**< HSE divided by 1. */
#define STM32_HSE32PRE_DIV2 (1 << 20) /**< HSE divided by 2. */
#define STM32_HSE32PRE_MASK (1U << 20) /**< HSEPRE field mask. */
#define STM32_HSE32PRE_DIV1 (0U << 20) /**< HSE divided by 1. */
#define STM32_HSE32PRE_DIV2 (1U << 20) /**< HSE divided by 2. */
/** @} */
/**
* @name RCC_CFGR register bits definitions
* @{
*/
#define STM32_SW_MASK (3 << 0) /**< SW field mask. */
#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
#define STM32_SW_MASK (3U << 0) /**< SW field mask. */
#define STM32_SW_MSI (0U << 0) /**< SYSCLK source is MSI. */
#define STM32_SW_HSI16 (1U << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (2U << 0) /**< SYSCLK source is HSE. */
#define STM32_SW_PLL (3U << 0) /**< SYSCLK source is PLL. */
#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */
#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
#define STM32_STOPWUCK_MASK (1U << 15) /**< STOPWUCK field mask. */
#define STM32_STOPWUCK_MSI (0U << 15) /**< Wakeup clock is MSI. */
#define STM32_STOPWUCK_HSI16 (1U << 15) /**< Wakeup clock is HSI16. */
#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */
#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */
#define STM32_MCOSEL_HSE32 (4 << 24) /**< HSE32 clock on MCO pin. */
#define STM32_MCOSEL_PLLRCLK (5 << 24) /**< PLLR clock on MCO pin. */
#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
#define STM32_MCOSEL_LSE (8 << 24) /**< LSE clock on MCO pin. */
#define STM32_MCOSEL_PLLPCLK (13 << 24) /**< PLLP clock on MCO pin. */
#define STM32_MCOSEL_PLLQCLK (14 << 24) /**< PLLQ clock on MCO pin. */
#define STM32_MCOSEL_MASK (15U << 24) /**< MCOSEL field mask. */
#define STM32_MCOSEL_NOCLOCK (0U << 24) /**< No clock on MCO pin. */
#define STM32_MCOSEL_SYSCLK (1U << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCOSEL_MSI (2U << 24) /**< MSI clock on MCO pin. */
#define STM32_MCOSEL_HSI16 (3U << 24) /**< HSI16 clock on MCO pin. */
#define STM32_MCOSEL_HSE32 (4U << 24) /**< HSE32 clock on MCO pin. */
#define STM32_MCOSEL_PLLRCLK (5U << 24) /**< PLLR clock on MCO pin. */
#define STM32_MCOSEL_LSI (6U << 24) /**< LSI clock on MCO pin. */
#define STM32_MCOSEL_LSE (8U << 24) /**< LSE clock on MCO pin. */
#define STM32_MCOSEL_PLLPCLK (13U << 24) /**< PLLP clock on MCO pin. */
#define STM32_MCOSEL_PLLQCLK (14U << 24) /**< PLLQ clock on MCO pin. */
#define STM32_MCOPRE_MASK (7 << 28) /**< MCOPRE field mask. */
#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
#define STM32_MCOPRE_MASK (7U << 28) /**< MCOPRE field mask. */
#define STM32_MCOPRE_DIV1 (0U << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV2 (1U << 28) /**< MCO divided by 2. */
#define STM32_MCOPRE_DIV4 (2U << 28) /**< MCO divided by 4. */
#define STM32_MCOPRE_DIV8 (3U << 28) /**< MCO divided by 8. */
#define STM32_MCOPRE_DIV16 (4U << 28) /**< MCO divided by 16. */
/** @} */
/* Some ST headers do not have this definition.*/
@ -240,100 +241,100 @@
* @name RCC_PLLCFGR register bits definitions
* @{
*/
#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
#define STM32_PLLSRC_MSI (1 << 0) /**< PLL clock source is MSI. */
#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
#define STM32_PLLSRC_MASK (3U << 0) /**< PLL clock source mask. */
#define STM32_PLLSRC_NOCLOCK (0U << 0) /**< PLL clock source disabled. */
#define STM32_PLLSRC_MSI (1U << 0) /**< PLL clock source is MSI. */
#define STM32_PLLSRC_HSI16 (2U << 0) /**< PLL clock source is HSI16. */
#define STM32_PLLSRC_HSE (3U << 0) /**< PLL clock source is HSE. */
/** @} */
/**
* @name RCC_CCIPR register bits definitions
* @{
*/
#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 source is HSI16. */
#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
#define STM32_USART1SEL_MASK (3U << 0) /**< USART1SEL mask. */
#define STM32_USART1SEL_PCLK2 (0U << 0) /**< USART1 source is PCLK2. */
#define STM32_USART1SEL_SYSCLK (1U << 0) /**< USART1 source is SYSCLK. */
#define STM32_USART1SEL_HSI16 (2U << 0) /**< USART1 source is HSI16. */
#define STM32_USART1SEL_LSE (3U << 0) /**< USART1 source is LSE. */
#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 source is HSI16. */
#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
#define STM32_USART2SEL_MASK (3U << 2) /**< USART2 mask. */
#define STM32_USART2SEL_PCLK1 (0U << 2) /**< USART2 source is PCLK1. */
#define STM32_USART2SEL_SYSCLK (1U << 2) /**< USART2 source is SYSCLK. */
#define STM32_USART2SEL_HSI16 (2U << 2) /**< USART2 source is HSI16. */
#define STM32_USART2SEL_LSE (3U << 2) /**< USART2 source is LSE. */
#define STM32_SPI2S2SEL_MASK (3 << 8) /**< SPI2S2SEL mask. */
#define STM32_SPI2S2SEL_PLLQCLK (1 << 8) /**< SPI2S2 source is PLLQ. */
#define STM32_SPI2S2SEL_HSI16 (2 << 8) /**< SPI2S2 source is HSI16. */
#define STM32_SPI2S2SEL_CKIN (3 << 8) /**< SPI2S2 source is External Input.*/
#define STM32_SPI2S2SEL_MASK (3U << 8) /**< SPI2S2SEL mask. */
#define STM32_SPI2S2SEL_PLLQCLK (1U << 8) /**< SPI2S2 source is PLLQ. */
#define STM32_SPI2S2SEL_HSI16 (2U << 8) /**< SPI2S2 source is HSI16. */
#define STM32_SPI2S2SEL_CKIN (3U << 8) /**< SPI2S2 source is External Input.*/
#define STM32_LPUART1SEL_MASK (3 << 10) /**< LPUART1 mask. */
#define STM32_LPUART1SEL_PCLK1 (0 << 10) /**< LPUART1 source is PCLK1. */
#define STM32_LPUART1SEL_SYSCLK (1 << 10) /**< LPUART1 source is SYSCLK. */
#define STM32_LPUART1SEL_HSI16 (2 << 10) /**< LPUART1 source is HSI16. */
#define STM32_LPUART1SEL_LSE (3 << 10) /**< LPUART1 source is LSE. */
#define STM32_LPUART1SEL_MASK (3U << 10) /**< LPUART1 mask. */
#define STM32_LPUART1SEL_PCLK1 (0U << 10) /**< LPUART1 source is PCLK1. */
#define STM32_LPUART1SEL_SYSCLK (1U << 10) /**< LPUART1 source is SYSCLK. */
#define STM32_LPUART1SEL_HSI16 (2U << 10) /**< LPUART1 source is HSI16. */
#define STM32_LPUART1SEL_LSE (3U << 10) /**< LPUART1 source is LSE. */
#define STM32_I2C1SEL_MASK (3 << 12) /**< I2C1SEL mask. */
#define STM32_I2C1SEL_PCLK1 (0 << 12) /**< I2C1 source is PCLK1. */
#define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 source is SYSCLK. */
#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 source is HSI16. */
#define STM32_I2C1SEL_MASK (3U << 12) /**< I2C1SEL mask. */
#define STM32_I2C1SEL_PCLK1 (0U << 12) /**< I2C1 source is PCLK1. */
#define STM32_I2C1SEL_SYSCLK (1U << 12) /**< I2C1 source is SYSCLK. */
#define STM32_I2C1SEL_HSI16 (2U << 12) /**< I2C1 source is HSI16. */
#define STM32_I2C2SEL_MASK (3 << 14) /**< I2C2SEL mask. */
#define STM32_I2C2SEL_PCLK1 (0 << 14) /**< I2C2 source is PCLK1. */
#define STM32_I2C2SEL_SYSCLK (1 << 14) /**< I2C2 source is SYSCLK. */
#define STM32_I2C2SEL_HSI16 (2 << 14) /**< I2C2 source is HSI16. */
#define STM32_I2C2SEL_MASK (3U << 14) /**< I2C2SEL mask. */
#define STM32_I2C2SEL_PCLK1 (0U << 14) /**< I2C2 source is PCLK1. */
#define STM32_I2C2SEL_SYSCLK (1U << 14) /**< I2C2 source is SYSCLK. */
#define STM32_I2C2SEL_HSI16 (2U << 14) /**< I2C2 source is HSI16. */
#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3SEL mask. */
#define STM32_I2C3SEL_PCLK1 (0 << 16) /**< I2C3 source is PCLK1. */
#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 source is SYSCLK. */
#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 source is HSI16. */
#define STM32_I2C3SEL_MASK (3U << 16) /**< I2C3SEL mask. */
#define STM32_I2C3SEL_PCLK1 (0U << 16) /**< I2C3 source is PCLK1. */
#define STM32_I2C3SEL_SYSCLK (1U << 16) /**< I2C3 source is SYSCLK. */
#define STM32_I2C3SEL_HSI16 (2U << 16) /**< I2C3 source is HSI16. */
#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1SEL mask. */
#define STM32_LPTIM1SEL_PCLK1 (0 << 18) /**< LPTIM1 source is PCLK1. */
#define STM32_LPTIM1SEL_LSI (1 << 18) /**< LPTIM1 source is LSI. */
#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 source is HSI16. */
#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 source is LSE. */
#define STM32_LPTIM1SEL_MASK (3U << 18) /**< LPTIM1SEL mask. */
#define STM32_LPTIM1SEL_PCLK1 (0U << 18) /**< LPTIM1 source is PCLK1. */
#define STM32_LPTIM1SEL_LSI (1U << 18) /**< LPTIM1 source is LSI. */
#define STM32_LPTIM1SEL_HSI16 (2U << 18) /**< LPTIM1 source is HSI16. */
#define STM32_LPTIM1SEL_LSE (3U << 18) /**< LPTIM1 source is LSE. */
#define STM32_LPTIM2SEL_MASK (3 << 20) /**< LPTIM2SEL mask. */
#define STM32_LPTIM2SEL_PCLK1 (0 << 20) /**< LPTIM2 source is PCLK1. */
#define STM32_LPTIM2SEL_LSI (1 << 20) /**< LPTIM2 source is LSI. */
#define STM32_LPTIM2SEL_HSI16 (2 << 20) /**< LPTIM2 source is HSI16. */
#define STM32_LPTIM2SEL_LSE (3 << 20) /**< LPTIM2 source is LSE. */
#define STM32_LPTIM2SEL_MASK (3U << 20) /**< LPTIM2SEL mask. */
#define STM32_LPTIM2SEL_PCLK1 (0U << 20) /**< LPTIM2 source is PCLK1. */
#define STM32_LPTIM2SEL_LSI (1U << 20) /**< LPTIM2 source is LSI. */
#define STM32_LPTIM2SEL_HSI16 (2U << 20) /**< LPTIM2 source is HSI16. */
#define STM32_LPTIM2SEL_LSE (3U << 20) /**< LPTIM2 source is LSE. */
#define STM32_LPTIM3SEL_MASK (3 << 22) /**< LPTIM2SEL mask. */
#define STM32_LPTIM3SEL_PCLK1 (0 << 22) /**< LPTIM2 source is PCLK1. */
#define STM32_LPTIM3SEL_LSI (1 << 22) /**< LPTIM2 source is LSI. */
#define STM32_LPTIM3SEL_HSI16 (2 << 22) /**< LPTIM2 source is HSI16. */
#define STM32_LPTIM3SEL_LSE (3 << 22) /**< LPTIM2 source is LSE. */
#define STM32_LPTIM3SEL_MASK (3U << 22) /**< LPTIM2SEL mask. */
#define STM32_LPTIM3SEL_PCLK1 (0U << 22) /**< LPTIM2 source is PCLK1. */
#define STM32_LPTIM3SEL_LSI (1U << 22) /**< LPTIM2 source is LSI. */
#define STM32_LPTIM3SEL_HSI16 (2U << 22) /**< LPTIM2 source is HSI16. */
#define STM32_LPTIM3SEL_LSE (3U << 22) /**< LPTIM2 source is LSE. */
#define STM32_ADCSEL_MASK (3 << 28) /**< ADCSEL mask. */
#define STM32_ADCSEL_NOCLK (0 << 28) /**< ADC clock disabled. */
#define STM32_ADCSEL_HSI16 (1 << 28) /**< ADC source is HSI16. */
#define STM32_ADCSEL_PLLPCLK (2 << 28) /**< ADC source is PLL. */
#define STM32_ADCSEL_SYSCLK (3 << 28) /**< ADC source is SYSCLK. */
#define STM32_ADCSEL_MASK (3U << 28) /**< ADCSEL mask. */
#define STM32_ADCSEL_NOCLK (0U << 28) /**< ADC clock disabled. */
#define STM32_ADCSEL_HSI16 (1U << 28) /**< ADC source is HSI16. */
#define STM32_ADCSEL_PLLPCLK (2U << 28) /**< ADC source is PLL. */
#define STM32_ADCSEL_SYSCLK (3U << 28) /**< ADC source is SYSCLK. */
#define STM32_RNGSEL_MASK (3 << 30) /**< RNGSEL mask. */
#define STM32_RNGSEL_PLLQCLK (0 << 30) /**< RNG source is PLL. */
#define STM32_RNGSEL_LSI (1 << 30) /**< RNG source is LSI. */
#define STM32_RNGSEL_LSE (2 << 30) /**< RNG source is LSE. */
#define STM32_RNGSEL_MSI (3 << 30) /**< RNG source is MSI. */
#define STM32_RNGSEL_MASK (3U << 30) /**< RNGSEL mask. */
#define STM32_RNGSEL_PLLQCLK (0U << 30) /**< RNG source is PLL. */
#define STM32_RNGSEL_LSI (1U << 30) /**< RNG source is LSI. */
#define STM32_RNGSEL_LSE (2U << 30) /**< RNG source is LSE. */
#define STM32_RNGSEL_MSI (3U << 30) /**< RNG source is MSI. */
/** @} */
/**
* @name RCC_BDCR register bits definitions
* @{
*/
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
#define STM32_RTCSEL_HSE32DIV (3 << 8) /**< RTC source is HSE divided. */
#define STM32_RTCSEL_MASK (3U << 8) /**< RTC source mask. */
#define STM32_RTCSEL_NOCLOCK (0U << 8) /**< No RTC source. */
#define STM32_RTCSEL_LSE (1U << 8) /**< RTC source is LSE. */
#define STM32_RTCSEL_LSI (2U << 8) /**< RTC source is LSI. */
#define STM32_RTCSEL_HSE32DIV (3U << 8) /**< RTC source is HSE divided. */
#define STM32_LSCOSEL_MASK (3 << 24) /**< LSCO pin clock source. */
#define STM32_LSCOSEL_NOCLOCK (0 << 24) /**< No clock on LSCO pin. */
#define STM32_LSCOSEL_LSI (1 << 24) /**< LSI on LSCO pin. */
#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */
#define STM32_LSCOSEL_MASK (3U << 24) /**< LSCO pin clock source. */
#define STM32_LSCOSEL_NOCLOCK (0U << 24) /**< No clock on LSCO pin. */
#define STM32_LSCOSEL_LSI (1U << 24) /**< LSI on LSCO pin. */
#define STM32_LSCOSEL_LSE (3U << 24) /**< LSE on LSCO pin. */
/** @} */
/**
@ -341,6 +342,16 @@
*/
#define SPI3 SUBGHZSPI
/**
* @brief Mapping ADC on ADC1.
*/
#define ADC1 ADC
/**
* @brief Mapping ADC_COMMON on ADC1_COMMON.
*/
#define ADC1_COMMON ADC_COMMON
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -356,6 +367,14 @@
#define STM32_NO_INIT FALSE
#endif
/**
* @brief Target code for this HAL configuration.
* @note Core 1 is the Cortex-M4, core 2 is the Cortex-M0+.
*/
#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__)
#define STM32_TARGET_CORE 1
#endif
/**
* @brief Enables the dynamic clock handling.
*/
@ -543,7 +562,7 @@
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLM_VALUE 1
#define STM32_PLLM_VALUE 1U
#endif
/**
@ -553,7 +572,7 @@
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLN_VALUE 24
#define STM32_PLLN_VALUE 24U
#endif
/**
@ -563,7 +582,7 @@
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLP_VALUE 2
#define STM32_PLLP_VALUE 2U
#endif
/**
@ -573,7 +592,7 @@
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLQ_VALUE 2
#define STM32_PLLQ_VALUE 2U
#endif
/**
@ -583,7 +602,7 @@
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLR_VALUE 2
#define STM32_PLLR_VALUE 2U
#endif
/**
@ -715,6 +734,23 @@
#error "Using a wrong mcuconf.h file, STM32WLxx_MCUCONF not defined"
#endif
/**
* @brief Target core for this HAL configuration.
* @note Core 1 is the Cortex-M4, core 2 is the Cortex-M0+.
*/
#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__)
#define STM32_TARGET_CORE 1
#endif
#if (STM32_TARGET_CORE == 2) && (STM32_HAS_M0 == FALSE)
#error "Cortex-M0 core not present in the selected device."
#endif
#if (defined(CORE_CM0PLUS) && (STM32_TARGET_CORE == 1)) || \
(!defined(CORE_CM0PLUS) && (STM32_TARGET_CORE == 2))
#error "wrong target core specified"
#endif
/*
* Board files sanity checks.
*/
@ -1049,14 +1085,17 @@
/*
* HSE32 related checks.
*/
#if STM32_HSE32_ENABLED
#if !defined(STM32_HSE32SRC)
#error "STM32_HSE32SRC should be defined in mcuconf.h"
#endif
#if !defined(STM32_HSE32SRC) || \
(STM32_HSE32SRC != STM32_HSE32_XTAL && \
STM32_HSE32SRC != STM32_HSE32_TCXO && \
STM32_HSE32SRC != STM32_HSE32_EXTS)
#error "STM32_HSE32SRC should by defined in mcuconf.h with correct value"
#endif
#if STM32_HSE32SRC != STM32_HSE32_XTAL && \
STM32_HSE32SRC != STM32_HSE32_TCXO && \
STM32_HSE32SRC != STM32_HSE32_EXTS
#error "STM32_HSE32SRC should be defined in mcuconf.h with correct value"
#endif
#if STM32_HSE32_ENABLED
#if STM32_HSE32SRC == STM32_HSE32_TCXO
#error "HSE32 TCXO should be controled using SUBGHZ Radio Driver"
@ -1236,9 +1275,9 @@
#if (STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLPEN (1 << 16)
#define STM32_PLLPEN (1U << 16)
#else
#define STM32_PLLPEN (0 << 16)
#define STM32_PLLPEN (0U << 16)
#endif
/**
@ -1248,9 +1287,9 @@
(STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
(STM32_SPI2S2SEL == STM32_SPI2S2SEL_PLLQCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLQEN (1 << 24)
#define STM32_PLLQEN (1U << 24)
#else
#define STM32_PLLQEN (0 << 24)
#define STM32_PLLQEN (0U << 24)
#endif
/**
@ -1259,9 +1298,9 @@
#if (STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLREN (1 << 28)
#define STM32_PLLREN (1U << 28)
#else
#define STM32_PLLREN (0 << 28)
#define STM32_PLLREN (0U << 28)
#endif
/* Inclusion of PLL-related checks and calculations.*/
@ -1289,12 +1328,51 @@
#error "invalid STM32_SW value specified"
#endif
/*
* CM0+ Core clock related checks.
*/
#if (STM32_HAS_M0 == TRUE)
#if !defined(STM32_C2HPRE)
#error "STM32_C2HPRE not defined in mcuconf.h"
#endif
#else /* (STM32_HAS_M0 == FALSE) */
#if defined(STM32_C2HPRE)
#error "STM32_C2HPRE should not be defined in mcuconf.h"
#else
#define STM32_HCLK2 0U
#define STM32_C2HPRE 0UL
#endif
#endif /* (STM32_HAS_M0 == TRUE) */
/* Bus handlers.*/
#include "stm32_ahb.inc"
#include "stm32_ahb3.inc"
#include "stm32_apb1.inc"
#include "stm32_apb2.inc"
#if (STM32_HAS_M0 == TRUE)
#include "stm32_c2ahb.inc"
#endif
/**
* @brief Core 1 clock.
*/
#define STM32_CORE1_CK STM32_HCLK
/**
* @brief Core 2 clock.
*/
#define STM32_CORE2_CK STM32_HCLK2
#if STM32_TARGET_CORE == 1
#define STM32_CORE_CK STM32_CORE1_CK
#elif STM32_TARGET_CORE == 2
#define STM32_CORE_CK STM32_CORE2_CK
#else
#error "invalid STM32_TARGET_CORE value specified"
#endif
/**
* @brief MCO divider clock frequency.
*/
@ -1513,13 +1591,15 @@
#define STM32_RNGCLK STM32_LSECLK
#elif STM32_RNGSEL == STM32_RNGSEL_MSI
#define STM32_RNGCLK STM32_HSI16CLK
#else
#error "invalid source selected for RNG clock"
#endif
/**
* @brief SPI2S2 clock frequency.
*/
#if (STM32_SPI2S2SEL == STM32_SPI2S2SEL_PLLQCLK) || defined(__DOXYGEN__)
#define STM32_SPI2S2CLK hal_lld_get_clock_point(CLK__PLLQCLK)
#define STM32_SPI2S2CLK hal_lld_get_clock_point(CLK_PLLQCLK)
#elif STM32_SPI2S2SEL == STM32_SPI2S2SEL_HSI16
#define STM32_SPI2S2CLK STM32_HSI16CLK
#elif STM32_SPI2S2SEL == STM32_SPI2S2SEL_CKIN
@ -1647,6 +1727,7 @@ typedef struct {
(clkpt) == CLK_HCLK ? STM32_HCLK : \
(clkpt) == CLK_PCLK1 ? STM32_PCLK1 : \
(clkpt) == CLK_PCLK1TIM ? STM32_TIMP1CLK : \
(clkpt) == CLK_HCLK2 ? STM32_HCLK2 : \
(clkpt) == CLK_PCLK2 ? STM32_PCLK2 : \
(clkpt) == CLK_PCLK2TIM ? STM32_TIMP2CLK : \
(clkpt) == CLK_HCLK3 ? STM32_HCLK3 : \

2
os/hal/ports/STM32/STM32WLxx/platform.mk
View File

@ -26,7 +26,7 @@ else
endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv5/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk

35
os/hal/ports/STM32/STM32WLxx/stm32_isr.c
View File

@ -51,6 +51,8 @@
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_TARGET_CORE == 1
#include "stm32_exti0.inc"
#include "stm32_exti1.inc"
#include "stm32_exti2.inc"
@ -61,11 +63,28 @@
#include "stm32_exti16_34.inc"
#include "stm32_exti45.inc"
#include "stm32_tim1.inc"
#else /* STM32_TARGET_CORE == 2 */
#include "stm32_dma1_ch123.inc"
#include "stm32_dma1_ch4567.inc"
#include "stm32_dma2_ch1-7.inc"
#include "stm32_exti0_1.inc"
#include "stm32_exti2_3.inc"
#include "stm32_exti4_15.inc"
#include "stm32_exti16_34.inc"
#include "stm32_exti45.inc"
#include "stm32_tim1_shared.inc"
#endif /* STM32_TARGET_CORE == 1 */
#include "stm32_usart1.inc"
#include "stm32_usart2.inc"
#include "stm32_lpuart1.inc"
#include "stm32_tim1.inc"
#include "stm32_tim2.inc"
#include "stm32_tim16.inc"
#include "stm32_tim17.inc"
@ -81,6 +100,7 @@
*/
void irqInit(void) {
#if STM32_TARGET_CORE == 1
exti0_irq_init();
exti1_irq_init();
exti2_irq_init();
@ -90,6 +110,13 @@ void irqInit(void) {
exti10_15_irq_init();
exti16_exti34_irq_init();
exti45_irq_init();
#else
exti0_1_irq_init();
exti2_3_irq_init();
exti4_15_irq_init();
exti16_exti34_irq_init();
exti45_irq_init();
#endif /* STM32_TARGET_CORE == 1 */
tim1_irq_init();
tim2_irq_init();
@ -108,6 +135,7 @@ void irqInit(void) {
*/
void irqDeinit(void) {
#if STM32_TARGET_CORE == 1
exti0_irq_deinit();
exti1_irq_deinit();
exti2_irq_deinit();
@ -117,6 +145,11 @@ void irqDeinit(void) {
exti10_15_irq_deinit();
exti16_exti34_irq_deinit();
exti45_irq_deinit();
#else
exti0_1_irq_deinit();
exti2_3_irq_deinit();
exti4_15_irq_deinit();
#endif /* STM32_TARGET_CORE == 1 */
tim1_irq_deinit();
tim2_irq_deinit();

123
os/hal/ports/STM32/STM32WLxx/stm32_isr.h
View File

@ -43,123 +43,12 @@
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector88
#define STM32_ADC1_NUMBER 18
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER Vector6C
#define STM32_DMA1_CH2_HANDLER Vector70
#define STM32_DMA1_CH3_HANDLER Vector74
#define STM32_DMA1_CH4_HANDLER Vector78
#define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA2_CH1_HANDLER Vector118
#define STM32_DMA2_CH2_HANDLER Vector11C
#define STM32_DMA2_CH3_HANDLER Vector120
#define STM32_DMA2_CH4_HANDLER Vector124
#define STM32_DMA2_CH5_HANDLER Vector128
#define STM32_DMA2_CH6_HANDLER Vector12C
#define STM32_DMA2_CH7_HANDLER Vector130
#define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12
#define STM32_DMA1_CH3_NUMBER 13
#define STM32_DMA1_CH4_NUMBER 14
#define STM32_DMA1_CH5_NUMBER 15
#define STM32_DMA1_CH6_NUMBER 16
#define STM32_DMA1_CH7_NUMBER 17
#define STM32_DMA2_CH1_NUMBER 54
#define STM32_DMA2_CH2_NUMBER 55
#define STM32_DMA2_CH3_NUMBER 56
#define STM32_DMA2_CH4_NUMBER 57
#define STM32_DMA2_CH5_NUMBER 58
#define STM32_DMA2_CH6_NUMBER 59
#define STM32_DMA2_CH7_NUMBER 60
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_9_HANDLER Vector98
#define STM32_EXTI10_15_HANDLER VectorE4
#define STM32_EXTI16_34_HANDLER Vector44 /* PVD PVM3 */
#define STM32_EXTI21_22_HANDLER Vector140 /* COMP1..2 */
#define STM32_EXTI45_HANDLER Vector108 /* SG */
#define STM32_EXTI0_NUMBER 6
#define STM32_EXTI1_NUMBER 7
#define STM32_EXTI2_NUMBER 8
#define STM32_EXTI3_NUMBER 9
#define STM32_EXTI4_NUMBER 10
#define STM32_EXTI5_9_NUMBER 22
#define STM32_EXTI10_15_NUMBER 41
#define STM32_EXTI16_34_NUMBER 1
#define STM32_EXTI21_22_NUMBER 21
#define STM32_EXTI45_NUMBER 50
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorB8
#define STM32_I2C1_ERROR_HANDLER VectorBC
#define STM32_I2C2_EVENT_HANDLER VectorC0
#define STM32_I2C2_ERROR_HANDLER VectorC4
#define STM32_I2C3_EVENT_HANDLER Vector100
#define STM32_I2C3_ERROR_HANDLER Vector104
#define STM32_I2C1_EVENT_NUMBER 30
#define STM32_I2C1_ERROR_NUMBER 31
#define STM32_I2C2_EVENT_NUMBER 32
#define STM32_I2C2_ERROR_NUMBER 33
#define STM32_I2C3_EVENT_NUMBER 48
#define STM32_I2C3_ERROR_NUMBER 49
/*
* TIM units.
*/
#define STM32_TIM1_BRK_HANDLER Vector9C
#define STM32_TIM1_UP_HANDLER VectorA0
#define STM32_TIM1_TRGCO_HANDLER VectorA4
#define STM32_TIM1_CC_HANDLER VectorA8
#define STM32_TIM2_HANDLER VectorAC
#define STM32_TIM16_HANDLER VectorB0
#define STM32_TIM17_HANDLER VectorB4
#define STM32_TIM1_BRK_NUMBER 23
#define STM32_TIM1_UP_NUMBER 24
#define STM32_TIM1_TRGCO_TIM17_NUMBER 25
#define STM32_TIM1_CC_NUMBER 26
#define STM32_TIM2_NUMBER 27
#define STM32_TIM16_NUMBER 28
#define STM32_TIM17_NUMBER 29
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorD0
#define STM32_USART2_HANDLER VectorD4
#define STM32_LPUART1_HANDLER VectorD8
#define STM32_USART1_NUMBER 36
#define STM32_USART2_NUMBER 37
#define STM32_LPUART1_NUMBER 38
/** @} */
/* Inclusion of Mx core specific definitions.*/
#if STM32_TARGET_CORE == 1
#include "stm32_isr_m4.inc"
#else
#include "stm32_isr_m0.inc"
#endif
/*===========================================================================*/
/* Driver pre-compile time settings. */

129
os/hal/ports/STM32/STM32WLxx/stm32_isr_m0.inc Normal file
View File

@ -0,0 +1,129 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/stm32_isr_m0.inc
* @brief STM32WLxx M0 core ISR handler header.
*
* @addtogroup SRM32WLxx_ISR
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/**
* @name CM0+ core ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector5C
#define STM32_ADC1_NUMBER 7
/*
* DMA unit.
*/
#define STM32_DMA1_CH123_HANDLER Vector60
#define STM32_DMA1_CH4567_HANDLER Vector64
#define STM32_DMA2_CH1_7_HANDLER Vector68
#define STM32_DMA1_CH123_NUMBER 8
#define STM32_DMA1_CH4567_NUMBER 9
#define STM32_DMA2_CH1_7_NUMBER 10
/*
* EXTI unit.
*/
#define STM32_EXTI0_1_HANDLER Vector50
#define STM32_EXTI2_3_HANDLER Vector54
#define STM32_EXTI4_15_HANDLER Vector58
#define STM32_EXTI16_34_HANDLER Vector44 /* PVD PVM3 */
#define STM32_EXTI21_22_HANDLER Vector5C /* COMP1..2 */
#define STM32_EXTI45_HANDLER VectorBC /* SG */
#define STM32_EXTI0_1_NUMBER 4
#define STM32_EXTI2_3_NUMBER 5
#define STM32_EXTI4_15_NUMBER 6
#define STM32_EXTI16_34_NUMBER 1
#define STM32_EXTI21_22_NUMBER 7
#define STM32_EXTI45_NUMBER 31
/*
* I2C units.
*/
#define STM32_I2C1_GLOBAL_HANDLER Vector98
#define STM32_I2C2_GLOBAL_HANDLER Vector9C
#define STM32_I2C3_GLOBAL_HANDLER VectorA0
#define STM32_I2C1_GLOBAL_NUMBER 22
#define STM32_I2C2_GLOBAL_NUMBER 23
#define STM32_I2C3_GLOBAL_NUMBER 24
/*
* TIM units.
*/
#define STM32_TIM1_SHARED_HANDLER Vector78
#define STM32_TIM2_HANDLER Vector7C
#define STM32_TIM16_HANDLER Vector80
#define STM32_TIM17_HANDLER Vector84
#define STM32_TIM1_NUMBER 14
#define STM32_TIM2_NUMBER 15
#define STM32_TIM16_NUMBER 16
#define STM32_TIM17_NUMBER 17
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
#define STM32_LPUART1_HANDLER VectorB4
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
#define STM32_LPUART1_NUMBER 29
/** @} */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

171
os/hal/ports/STM32/STM32WLxx/stm32_isr_m4.inc Normal file
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@ -0,0 +1,171 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/stm32_irs_m4.inc
* @brief STM32WLxx M4 core ISR handler header.
*
* @addtogroup SRM32WLxx_ISR
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/**
* @name CM4 core ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector88
#define STM32_ADC1_NUMBER 18
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER Vector6C
#define STM32_DMA1_CH2_HANDLER Vector70
#define STM32_DMA1_CH3_HANDLER Vector74
#define STM32_DMA1_CH4_HANDLER Vector78
#define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA2_CH1_HANDLER Vector118
#define STM32_DMA2_CH2_HANDLER Vector11C
#define STM32_DMA2_CH3_HANDLER Vector120
#define STM32_DMA2_CH4_HANDLER Vector124
#define STM32_DMA2_CH5_HANDLER Vector128
#define STM32_DMA2_CH6_HANDLER Vector12C
#define STM32_DMA2_CH7_HANDLER Vector130
#define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12
#define STM32_DMA1_CH3_NUMBER 13
#define STM32_DMA1_CH4_NUMBER 14
#define STM32_DMA1_CH5_NUMBER 15
#define STM32_DMA1_CH6_NUMBER 16
#define STM32_DMA1_CH7_NUMBER 17
#define STM32_DMA2_CH1_NUMBER 54
#define STM32_DMA2_CH2_NUMBER 55
#define STM32_DMA2_CH3_NUMBER 56
#define STM32_DMA2_CH4_NUMBER 57
#define STM32_DMA2_CH5_NUMBER 58
#define STM32_DMA2_CH6_NUMBER 59
#define STM32_DMA2_CH7_NUMBER 60
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_9_HANDLER Vector98
#define STM32_EXTI10_15_HANDLER VectorE4
#define STM32_EXTI16_34_HANDLER Vector44 /* PVD PVM3 */
#define STM32_EXTI21_22_HANDLER Vector140 /* COMP1..2 */
#define STM32_EXTI45_HANDLER Vector108 /* SG */
#define STM32_EXTI0_NUMBER 6
#define STM32_EXTI1_NUMBER 7
#define STM32_EXTI2_NUMBER 8
#define STM32_EXTI3_NUMBER 9
#define STM32_EXTI4_NUMBER 10
#define STM32_EXTI5_9_NUMBER 22
#define STM32_EXTI10_15_NUMBER 41
#define STM32_EXTI16_34_NUMBER 1
#define STM32_EXTI21_22_NUMBER 21
#define STM32_EXTI45_NUMBER 50
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorB8
#define STM32_I2C1_ERROR_HANDLER VectorBC
#define STM32_I2C2_EVENT_HANDLER VectorC0
#define STM32_I2C2_ERROR_HANDLER VectorC4
#define STM32_I2C3_EVENT_HANDLER Vector100
#define STM32_I2C3_ERROR_HANDLER Vector104
#define STM32_I2C1_EVENT_NUMBER 30
#define STM32_I2C1_ERROR_NUMBER 31
#define STM32_I2C2_EVENT_NUMBER 32
#define STM32_I2C2_ERROR_NUMBER 33
#define STM32_I2C3_EVENT_NUMBER 48
#define STM32_I2C3_ERROR_NUMBER 49
/*
* TIM units.
*/
#define STM32_TIM1_BRK_HANDLER Vector9C
#define STM32_TIM1_UP_HANDLER VectorA0
#define STM32_TIM1_TRGCO_HANDLER VectorA4
#define STM32_TIM1_CC_HANDLER VectorA8
#define STM32_TIM2_HANDLER VectorAC
#define STM32_TIM16_HANDLER VectorB0
#define STM32_TIM17_HANDLER VectorB4
#define STM32_TIM1_BRK_NUMBER 23
#define STM32_TIM1_UP_NUMBER 24
#define STM32_TIM1_TRGCO_TIM17_NUMBER 25
#define STM32_TIM1_CC_NUMBER 26
#define STM32_TIM2_NUMBER 27
#define STM32_TIM16_NUMBER 28
#define STM32_TIM17_NUMBER 29
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorD0
#define STM32_USART2_HANDLER VectorD4
#define STM32_LPUART1_HANDLER VectorD8
#define STM32_USART1_NUMBER 36
#define STM32_USART2_NUMBER 37
#define STM32_LPUART1_NUMBER 38
/** @} */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

137
os/hal/ports/STM32/STM32WLxx/stm32_rcc.h
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@ -30,6 +30,39 @@
/* Driver constants. */
/*===========================================================================*/
/* Mapping RCC registers depends on target core.*/
#if STM32_TARGET_CORE == 1
#define STM32_RCC_AHB1ENR RCC->AHB1ENR
#define STM32_RCC_AHB2ENR RCC->AHB2ENR
#define STM32_RCC_AHB3ENR RCC->AHB3ENR
#define STM32_RCC_APB1ENR1 RCC->APB1ENR1
#define STM32_RCC_APB1ENR2 RCC->APB1ENR2
#define STM32_RCC_APB2ENR RCC->APB2ENR
#define STM32_RCC_APB3ENR RCC->APB3ENR
#define STM32_RCC_AHB1SMENR RCC->AHB1SMENR
#define STM32_RCC_AHB2SMENR RCC->AHB2SMENR
#define STM32_RCC_AHB3SMENR RCC->AHB3SMENR
#define STM32_RCC_APB1SMENR1 RCC->APB1SMENR1
#define STM32_RCC_APB1SMENR2 RCC->APB1SMENR2
#define STM32_RCC_APB2SMENR RCC->APB2SMENR
#define STM32_RCC_APB3SMENR RCC->APB3SMENR
#else /* STM32_TARGET_CORE == 2 */
#define STM32_RCC_AHB1ENR RCC->C2AHB1ENR
#define STM32_RCC_AHB2ENR RCC->C2AHB2ENR
#define STM32_RCC_AHB3ENR RCC->C2AHB3ENR
#define STM32_RCC_APB1ENR1 RCC->C2APB1ENR1
#define STM32_RCC_APB1ENR2 RCC->C2APB1ENR2
#define STM32_RCC_APB2ENR RCC->C2APB2ENR
#define STM32_RCC_APB3ENR RCC->C2APB3ENR
#define STM32_RCC_AHB1SMENR RCC->C2AHB1SMENR
#define STM32_RCC_AHB2SMENR RCC->C2AHB2SMENR
#define STM32_RCC_AHB3SMENR RCC->C2AHB3SMENR
#define STM32_RCC_APB1SMENR1 RCC->C2APB1SMENR1
#define STM32_RCC_APB1SMENR2 RCC->C2APB1SMENR2
#define STM32_RCC_APB2SMENR RCC->C2APB2SMENR
#define STM32_RCC_APB3SMENR RCC->C2APB3SMENR
#endif /* STM32_TARGET_CORE == 1 */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -59,12 +92,12 @@
* @api
*/
#define rccEnableAPB1R1(mask, lp) { \
RCC->APB1ENR1 |= (mask); \
STM32_RCC_APB1ENR1 |= (mask); \
if (lp) \
RCC->APB1SMENR1 |= (mask); \
STM32_RCC_APB1SMENR1 |= (mask); \
else \
RCC->APB1SMENR1 &= ~(mask); \
(void)RCC->APB1SMENR1; \
STM32_RCC_APB1SMENR1 &= ~(mask); \
(void)STM32_RCC_APB1SMENR1; \
}
/**
@ -75,9 +108,9 @@
* @api
*/
#define rccDisableAPB1R1(mask) { \
RCC->APB1ENR1 &= ~(mask); \
RCC->APB1SMENR1 &= ~(mask); \
(void)RCC->APB1SMENR1; \
STM32_RCC_APB1ENR1 &= ~(mask); \
STM32_RCC_APB1SMENR1 &= ~(mask); \
(void)STM32_RCC_APB1SMENR1; \
}
/**
@ -102,12 +135,12 @@
* @api
*/
#define rccEnableAPB1R2(mask, lp) { \
RCC->APB1ENR2 |= (mask); \
STM32_RCC_APB1ENR2 |= (mask); \
if (lp) \
RCC->APB1SMENR2 |= (mask); \
STM32_RCC_APB1SMENR2 |= (mask); \
else \
RCC->APB1SMENR2 &= ~(mask); \
(void)RCC->APB1SMENR2; \
STM32_RCC_APB1SMENR2 &= ~(mask); \
(void)STM32_RCC_APB1SMENR2; \
}
/**
@ -118,9 +151,9 @@
* @api
*/
#define rccDisableAPB1R2(mask) { \
RCC->APB1ENR2 &= ~(mask); \
RCC->APB1SMENR2 &= ~(mask); \
(void)RCC->APB1SMENR2; \
STM32_RCC_APB1ENR2 &= ~(mask); \
STM32_RCC_APB1SMENR2 &= ~(mask); \
(void)STM32_RCC_APB1SMENR2; \
}
/**
@ -145,12 +178,12 @@
* @api
*/
#define rccEnableAPB2(mask, lp) { \
RCC->APB2ENR |= (mask); \
STM32_RCC_APB2ENR |= (mask); \
if (lp) \
RCC->APB2SMENR |= (mask); \
STM32_RCC_APB2SMENR |= (mask); \
else \
RCC->APB2SMENR &= ~(mask); \
(void)RCC->APB2SMENR; \
STM32_RCC_APB2SMENR &= ~(mask); \
(void)STM32_RCC_APB2SMENR; \
}
/**
@ -161,9 +194,9 @@
* @api
*/
#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
RCC->APB2SMENR &= ~(mask); \
(void)RCC->APB2SMENR; \
STM32_RCC_APB2ENR &= ~(mask); \
STM32_RCC_APB2SMENR &= ~(mask); \
(void)STM32_RCC_APB2SMENR; \
}
/**
@ -188,12 +221,12 @@
* @api
*/
#define rccEnableAPB3(mask, lp) { \
RCC->APB3ENR |= (mask); \
STM32_RCC_APB3ENR |= (mask); \
if (lp) \
RCC->APB3SMENR |= (mask); \
STM32_RCC_APB3SMENR |= (mask); \
else \
RCC->APB3SMENR &= ~(mask); \
(void)RCC->APB3SMENR; \
STM32_RCC_APB3SMENR &= ~(mask); \
(void)STM32_RCC_APB3SMENR; \
}
/**
@ -204,9 +237,9 @@
* @api
*/
#define rccDisableAPB3(mask) { \
RCC->APB3ENR &= ~(mask); \
RCC->APB3SMENR &= ~(mask); \
(void)RCC->APB3SMENR; \
STM32_RCC_APB3ENR &= ~(mask); \
STM32_RCC_APB3SMENR &= ~(mask); \
(void)STM32_RCC_APB3SMENR; \
}
/**
@ -231,12 +264,12 @@
* @api
*/
#define rccEnableAHB1(mask, lp) { \
RCC->AHB1ENR |= (mask); \
STM32_RCC_AHB1ENR |= (mask); \
if (lp) \
RCC->AHB1SMENR |= (mask); \
STM32_RCC_AHB1SMENR |= (mask); \
else \
RCC->AHB1SMENR &= ~(mask); \
(void)RCC->AHB1SMENR; \
STM32_RCC_AHB1SMENR &= ~(mask); \
(void)STM32_RCC_AHB1SMENR; \
}
/**
@ -247,9 +280,9 @@
* @api
*/
#define rccDisableAHB1(mask) { \
RCC->AHB1ENR &= ~(mask); \
RCC->AHB1SMENR &= ~(mask); \
(void)RCC->AHB1SMENR; \
STM32_RCC_AHB1ENR &= ~(mask); \
STM32_RCC_AHB1SMENR &= ~(mask); \
(void)STM32_RCC_AHB1SMENR; \
}
/**
@ -274,12 +307,12 @@
* @api
*/
#define rccEnableAHB2(mask, lp) { \
RCC->AHB2ENR |= (mask); \
STM32_RCC_AHB2ENR |= (mask); \
if (lp) \
RCC->AHB2SMENR |= (mask); \
STM32_RCC_AHB2SMENR |= (mask); \
else \
RCC->AHB2SMENR &= ~(mask); \
(void)RCC->AHB2SMENR; \
STM32_RCC_AHB2SMENR &= ~(mask); \
(void)STM32_RCC_AHB2SMENR; \
}
/**
@ -290,9 +323,9 @@
* @api
*/
#define rccDisableAHB2(mask) { \
RCC->AHB2ENR &= ~(mask); \
RCC->AHB2SMENR &= ~(mask); \
(void)RCC->AHB2SMENR; \
STM32_RCC_AHB2ENR &= ~(mask); \
STM32_RCC_AHB2SMENR &= ~(mask); \
(void)STM32_RCC_AHB2SMENR; \
}
/**
@ -317,12 +350,12 @@
* @api
*/
#define rccEnableAHB3(mask, lp) { \
RCC->AHB3ENR |= (mask); \
STM32_RCC_AHB3ENR |= (mask); \
if (lp) \
RCC->AHB3SMENR |= (mask); \
STM32_RCC_AHB3SMENR |= (mask); \
else \
RCC->AHB3SMENR &= ~(mask); \
(void)RCC->AHB3SMENR; \
STM32_RCC_AHB3SMENR &= ~(mask); \
(void)STM32_RCC_AHB3SMENR; \
}
/**
@ -333,9 +366,9 @@
* @api
*/
#define rccDisableAHB3(mask) { \
RCC->AHB3ENR &= ~(mask); \
RCC->AHB3SMENR &= ~(mask); \
(void)RCC->AHB3SMENR; \
STM32_RCC_AHB3ENR &= ~(mask); \
STM32_RCC_AHB3SMENR &= ~(mask); \
(void)STM32_RCC_AHB3SMENR; \
}
/**
@ -391,21 +424,21 @@
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DACEN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @api
*/
#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DACEN)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DACRST)
/** @} */
/**

42
os/hal/ports/STM32/STM32WLxx/stm32_registry.h
View File

@ -29,6 +29,15 @@
/* Platform capabilities. */
/*===========================================================================*/
/* Cores.*/
#if defined(STM32WL55xx) || defined(STM32WL54xx)
#define STM32_HAS_M4 TRUE
#define STM32_HAS_M0 TRUE
#else
#define STM32_HAS_M4 TRUE
#define STM32_HAS_M0 FALSE
#endif
/**
* @name STM32WLxx capabilities
* @{
@ -54,19 +63,14 @@
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
#define STM32_ADC_SUPPORTS_PRESCALER TRUE
/* CAN attributes.*/
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
#define STM32_HAS_CAN3 FALSE
/* CPU2 attributes.*/
#if defined(STM32WL55xx) || defined(STM32WL54xx) || defined(__DOXYGEN__)
#define STM32_HAS_CPU2 TRUE
#else
#define STM32_HAS_CPU2 FALSE
#endif /* defined(STM32WL55xx) || defined(STM32WL54xx) */
/* CRC attributes.*/
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
@ -135,8 +139,12 @@
#define STM32_HAS_HASH1 FALSE
/* HSEM attributes.*/
#if defined(STM32WL55xx) || defined(STM32WL54xx) || defined(__DOXYGEN__)
#define STM32_HAS_HSEM TRUE
#define STM32_HSEM_SEMAPHORES 16
#else
#define STM32_HAS_HSEM FALSE
#endif /* defined(STM32WL55xx) || defined(STM32WL54xx) */
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
@ -188,21 +196,33 @@
#define STM32_RTC_HAS_MIXED_MODE TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_STORAGE_SIZE 32
#define STM32_RTC_ALARM_EXTI 17
#define STM32_RTC_TAMP_STAMP_EXTI 19
#define STM32_RTC_WKUP_EXTI 20
#if STM32_TARGET_CORE == 1
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
#define STM32_RTC_WKUP_HANDLER Vector4C
#define STM32_RTC_ALARM_HANDLER VectorE8
#define STM32_RTC_TAMP_STAMP_NUMBER 2
#define STM32_RTC_WKUP_NUMBER 3
#define STM32_RTC_ALARM_NUMBER 42
#define STM32_RTC_ALARM_EXTI 17
#define STM32_RTC_TAMP_STAMP_EXTI 19
#define STM32_RTC_WKUP_EXTI 20
#define STM32_RTC_IRQ_ENABLE() do { \
nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
} while (false)
#else
#define STM32_RTC_COMMON_HANDLER Vector48
#define STM32_RTC_COMMON_NUMBER 2
#define STM32_RTC_IRQ_ENABLE() \
nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
#endif /* STM32_TARGET_CORE == 1 */
/* Enabling RTC-related EXTI lines.*/
#define STM32_RTC_ENABLE_ALL_EXTI() do { \
extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
@ -211,7 +231,7 @@
EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
} while (false)
/* Clearing EXTI interrupts. */
/* Clearing RTC-related EXTI interrupts. */
#define STM32_RTC_CLEAR_ALL_EXTI() do { \
} while (false)

2
testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -38,6 +38,7 @@
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0 | PWR_CR2_PVDE)
#define STM32_PWR_PUCRA (0U)
@ -66,6 +67,7 @@
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI