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Added settings for STM32 OCTOSPIv1 and OCTOSPIv2 TCR bits SSHIFT and DHQC. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16199 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-04-03 08:17:04 +00:00
parent 4f05718d98
commit 92312891c0
4 changed files with 100 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c
View File

@ -168,6 +168,14 @@ void wspi_lld_init(void) {
#if STM32_WSPI_USE_OCTOSPI1
wspiObjectInit(&WSPID1);
WSPID1.extra_tcr = 0U
#if STM32_WSPI_OCTOSPI1_SSHIFT
| OCTOSPI_TCR_SSHIFT
#endif
#if STM32_WSPI_OCTOSPI1_DHQC
| OCTOSPI_TCR_DHQC
#endif
;
WSPID1.ospi = OCTOSPI1;
WSPID1.dma = NULL;
WSPID1.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI1_DMA_STREAM) |
@ -182,6 +190,14 @@ void wspi_lld_init(void) {
#if STM32_WSPI_USE_OCTOSPI2
wspiObjectInit(&WSPID2);
WSPID2.extra_tcr = 0U
#if STM32_WSPI_OCTOSPI2_SSHIFT
| OCTOSPI_TCR_SSHIFT
#endif
#if STM32_WSPI_OCTOSPI1_DHQC
| OCTOSPI_TCR_DHQC
#endif
;
WSPID2.ospi = OCTOSPI2;
WSPID2.dma = NULL;
WSPID2.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI2_DMA_STREAM) |
@ -308,7 +324,7 @@ void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
#endif
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = 0U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
@ -346,7 +362,7 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
@ -386,7 +402,7 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) | OCTOSPI_CR_FMODE_0;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
@ -416,7 +432,7 @@ void wspi_lld_map_flash(WSPIDriver *wspip,
/* Starting memory mapped mode using the passed parameters.*/
wspip->ospi->CR = OCTOSPI_CR_FMODE_1 | OCTOSPI_CR_FMODE_0 | OCTOSPI_CR_EN;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->IR = cmdp->cmd;
wspip->ospi->ABR = 0U;

30
os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.h
View File

@ -125,6 +125,34 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#endif
/**
* @brief OCTOSPI1 TCR_SSHIFT enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI1_SSHIFT) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_SSHIFT TRUE
#endif
/**
* @brief OCTOSPI2 TCR_SSHIFT enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI2_SSHIFT) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_SSHIFT TRUE
#endif
/**
* @brief OCTOSPI1 TCR_DHQC enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI1_DHQC) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_DHQC TRUE
#endif
/**
* @brief OCTOSPI2 TCR_DHQC enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI2_DHQC) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_DHQC TRUE
#endif
/**
* @brief OCTOSPI1 interrupt priority level setting.
*/
@ -292,6 +320,8 @@
* @brief Low level fields of the WSPI driver structure.
*/
#define wspi_lld_driver_fields \
/* Extra bits for the TCR register.*/ \
uint32_t extra_tcr; \
/* Pointer to the OCTOSPIx registers block.*/ \
OCTOSPI_TypeDef *ospi; \
/* OCTOSPI DMA stream.*/ \

24
os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.c
View File

@ -109,12 +109,28 @@ void wspi_lld_init(void) {
#if STM32_WSPI_USE_OCTOSPI1
wspiObjectInit(&WSPID1);
WSPID1.extra_tcr = 0U
#if STM32_WSPI_OCTOSPI1_SSHIFT
| OCTOSPI_TCR_SSHIFT
#endif
#if STM32_WSPI_OCTOSPI1_DHQC
| OCTOSPI_TCR_DHQC
#endif
;
WSPID1.ospi = OCTOSPI1;
WSPID1.mdma = NULL;
#endif
#if STM32_WSPI_USE_OCTOSPI2
wspiObjectInit(&WSPID2);
WSPID2.extra_tcr = 0U
#if STM32_WSPI_OCTOSPI2_SSHIFT
| OCTOSPI_TCR_SSHIFT
#endif
#if STM32_WSPI_OCTOSPI1_DHQC
| OCTOSPI_TCR_DHQC
#endif
;
WSPID2.ospi = OCTOSPI2;
WSPID2.mdma = NULL;
#endif
@ -220,7 +236,7 @@ void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = 0U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
@ -273,7 +289,7 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
@ -328,7 +344,7 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) | OCTOSPI_CR_FMODE_0;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->ABR = cmdp->alt;
wspip->ospi->IR = cmdp->cmd;
@ -358,7 +374,7 @@ void wspi_lld_map_flash(WSPIDriver *wspip,
/* Starting memory mapped mode using the passed parameters.*/
wspip->ospi->CR = OCTOSPI_CR_FMODE_1 | OCTOSPI_CR_FMODE_0 | OCTOSPI_CR_EN;
wspip->ospi->TCR = cmdp->dummy;
wspip->ospi->TCR = cmdp->dummy | wspip->extra_tcr;
wspip->ospi->CCR = cmdp->cfg;
wspip->ospi->IR = cmdp->cmd;
wspip->ospi->ABR = 0U;

30
os/hal/ports/STM32/LLD/OCTOSPIv2/hal_wspi_lld.h
View File

@ -126,6 +126,34 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#endif
/**
* @brief OCTOSPI1 TCR_SSHIFT enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI1_SSHIFT) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_SSHIFT TRUE
#endif
/**
* @brief OCTOSPI2 TCR_SSHIFT enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI2_SSHIFT) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_SSHIFT TRUE
#endif
/**
* @brief OCTOSPI1 TCR_DHQC enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI1_DHQC) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI1_DHQC TRUE
#endif
/**
* @brief OCTOSPI2 TCR_DHQC enforcing.
*/
#if !defined(STM32_WSPI_OCTOSPI2_DHQC) || defined(__DOXYGEN__)
#define STM32_WSPI_OCTOSPI2_DHQC TRUE
#endif
/**
* @brief OCTOSPI1 MDMA channel selection.
*/
@ -276,6 +304,8 @@
* @brief Low level fields of the WSPI driver structure.
*/
#define wspi_lld_driver_fields \
/* Extra bits for the TCR register.*/ \
uint32_t extra_tcr; \
/* Pointer to the OCTOSPIx registers block.*/ \
OCTOSPI_TypeDef *ospi; \
/* QUADSPI MDMA channel.*/ \