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ChibiOS
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Small changes. 

git-svn-id: https://svn.code.sf.net/p/chibios/svn2/trunk@11582 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
isiora 2018-02-27 00:25:39 +00:00
parent e372b812a0
commit 92d9ec18b5
2 changed files with 12 additions and 19 deletions
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9
testhal/ATSAMA5D2/FLEX-SPI/chconf.h
View File

@ -419,7 +419,7 @@
* *
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#define CH_DBG_ENABLE_ASSERTS FALSE #define CH_DBG_ENABLE_ASSERTS TRUE
/** /**
* @brief Debug option, trace buffer. * @brief Debug option, trace buffer.
@ -603,13 +603,6 @@
/* Port-specific settings (override port settings defaulted in chcore.h). */ /* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief Trust zone configuration.
* @details If enabled the kernel is configured for the secure world
* and can access specific devices.
*/
#define CH_CFG_SEC_WORLD TRUE
#endif /* CHCONF_H */ #endif /* CHCONF_H */
/** @} */ /** @} */

22
testhal/ATSAMA5D2/FLEX-SPI/main.c
View File

@ -26,26 +26,26 @@ static uint8_t rxbuf[BUFFER_SIZE];
* SPI high speed configuration (peripheral clock / 3 = 27,6 Mhz, CPHA=0, CPOL=0, MSb first). * SPI high speed configuration (peripheral clock / 3 = 27,6 Mhz, CPHA=0, CPOL=0, MSb first).
*/ */
static const SPIConfig hs_spicfg = { static const SPIConfig hs_spicfg = {
NULL, /* callback if present */ NULL, /* callback if present */
0, /* cs pad number */ 0, /* cs pad number */
SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */ SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */
SPI_CSR_SCBR(3) /* csr */ SPI_CSR_SCBR(1) /* csr */
}; };
/* /*
* SPI low speed configuration (peripheral clock / 166 = 500KHz, CPHA=0, CPOL=0, MSb first). * SPI low speed configuration (peripheral clock / 166 = 500KHz, CPHA=0, CPOL=0, MSb first).
*/ */
static const SPIConfig ls_spicfg = { static const SPIConfig ls_spicfg = {
NULL, /* callback if present */ NULL, /* callback if present */
0, /* cs pad number */ 0, /* cs pad number */
SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */ SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */
SPI_CSR_SCBR(166) /* csr */ SPI_CSR_SCBR(1) /* csr */
}; };
/* /*
* SPI bus contender 1. * SPI bus contender 1.
*/ */
static THD_WORKING_AREA(spi_thread_1_wa, 256); static THD_WORKING_AREA(spi_thread_1_wa, 1024);
static THD_FUNCTION(spi_thread_1, p) { static THD_FUNCTION(spi_thread_1, p) {
(void)p; (void)p;
@ -65,7 +65,7 @@ static THD_FUNCTION(spi_thread_1, p) {
/* /*
* SPI bus contender 2. * SPI bus contender 2.
*/ */
static THD_WORKING_AREA(spi_thread_2_wa, 256); static THD_WORKING_AREA(spi_thread_2_wa, 1024);
static THD_FUNCTION(spi_thread_2, p) { static THD_FUNCTION(spi_thread_2, p) {
(void)p; (void)p;
@ -75,7 +75,7 @@ static THD_FUNCTION(spi_thread_2, p) {
spiAcquireBus(&FSPID2); /* Acquire ownership of the bus. */ spiAcquireBus(&FSPID2); /* Acquire ownership of the bus. */
palSetLine(LINE_LED_RED); /* LED OFF. */ palSetLine(LINE_LED_RED); /* LED OFF. */
spiStart(&FSPID2, &ls_spicfg); /* Setup transfer parameters. */ spiStart(&FSPID2, &ls_spicfg); /* Setup transfer parameters. */
spiExchange(&FSPID2, 512, spiExchange(&FSPID2, BUFFER_SIZE,
txbuf, rxbuf); /* Atomic transfer operations. */ txbuf, rxbuf); /* Atomic transfer operations. */
cacheInvalidateRegion(&rxbuf, sizeof(rxbuf)); cacheInvalidateRegion(&rxbuf, sizeof(rxbuf));
spiReleaseBus(&FSPID2); /* Ownership release. */ spiReleaseBus(&FSPID2); /* Ownership release. */