diff --git a/demos/STM32/RT-STM32WB55CG-NUCLEO-USBDongle/cfg/mcuconf.h b/demos/STM32/RT-STM32WB55CG-NUCLEO-USBDongle/cfg/mcuconf.h index 6cbbb12bd..1daeddb08 100644 --- a/demos/STM32/RT-STM32WB55CG-NUCLEO-USBDongle/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32WB55CG-NUCLEO-USBDongle/cfg/mcuconf.h @@ -114,7 +114,7 @@ #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC12_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 @@ -134,10 +134,10 @@ #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 @@ -182,10 +182,10 @@ */ #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 @@ -207,8 +207,8 @@ * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") @@ -222,6 +222,6 @@ * WSPI driver system settings. */ #define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #endif /* MCUCONF_H */ diff --git a/demos/STM32/RT-STM32WB55RG-NUCLEO/cfg/mcuconf.h b/demos/STM32/RT-STM32WB55RG-NUCLEO/cfg/mcuconf.h index 985561de5..ec22b2c7d 100644 --- a/demos/STM32/RT-STM32WB55RG-NUCLEO/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32WB55RG-NUCLEO/cfg/mcuconf.h @@ -114,7 +114,7 @@ #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC12_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 @@ -134,10 +134,10 @@ #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 @@ -182,10 +182,10 @@ */ #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 @@ -207,8 +207,8 @@ * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") @@ -222,6 +222,6 @@ * WSPI driver system settings. */ #define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY #endif /* MCUCONF_H */ diff --git a/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.c b/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.c index a53dd6c65..9386a867c 100644 --- a/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.c +++ b/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2020 Ilya Kharin + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.h b/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.h index 372437d5e..25a0757d5 100644 --- a/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.h +++ b/os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2020 Ilya Kharin + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -208,7 +208,9 @@ #define GPIOG_PIN15 15U #define GPIOH_PIN0 0U +#define GPIOH_OSC_IN 0U #define GPIOH_PIN1 1U +#define GPIOH_OSC_OUT 1U #define GPIOH_PIN2 2U #define GPIOH_PIN3 3U #define GPIOH_PIN4 4U @@ -248,6 +250,9 @@ #define LINE_OSC32_IN PAL_LINE(GPIOC, GPIOC_PIN14) #define LINE_OSC32_OUT PAL_LINE(GPIOC, GPIOC_PIN15) +#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_PIN0) +#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_PIN1) + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/boards/ST_NUCLEO_WB55RG/board.c b/os/hal/boards/ST_NUCLEO_WB55RG/board.c index 9fd16b758..74e05f3a4 100644 --- a/os/hal/boards/ST_NUCLEO_WB55RG/board.c +++ b/os/hal/boards/ST_NUCLEO_WB55RG/board.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2019 Ilya Kharin + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/ST_NUCLEO_WB55RG/board.h b/os/hal/boards/ST_NUCLEO_WB55RG/board.h index c75e89ad4..cd2620c1a 100644 --- a/os/hal/boards/ST_NUCLEO_WB55RG/board.h +++ b/os/hal/boards/ST_NUCLEO_WB55RG/board.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2019 Ilya Kharin + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -235,7 +235,9 @@ #define GPIOG_PIN14 14U #define GPIOG_PIN15 15U +#define GPIOH_PIN0 0U #define GPIOH_OSC_IN 0U +#define GPIOH_PIN1 1U #define GPIOH_OSC_OUT 1U #define GPIOH_PIN2 2U #define GPIOH_PIN3 3U @@ -280,6 +282,9 @@ #define LINE_B3 PAL_LINE(GPIOD, GPIOD_PIN1) #define LINE_BUTTON_3 PAL_LINE(GPIOD, GPIOD_PIN1) +#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_PIN0) +#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_PIN1) + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32WBxx/stm32_registry.h b/os/hal/ports/STM32/STM32WBxx/stm32_registry.h index 6b580fb12..d354dfa14 100644 --- a/os/hal/ports/STM32/STM32WBxx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32WBxx/stm32_registry.h @@ -1,244 +1,264 @@ -/* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Ilya Kharin. -*/ - -/** - * @file STM32WBxx/stm32_registry.h - * @brief STM32WBxx capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef STM32_REGISTRY_H -#define STM32_REGISTRY_H - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32WBxx capabilities - * @{ - */ - -/*===========================================================================*/ -/* Common. */ -/*===========================================================================*/ - -/* RNG attributes.*/ -#define STM32_HAS_RNG1 TRUE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_STORAGE_SIZE 80 -#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 -#define STM32_RTC_WKUP_HANDLER Vector4C -#define STM32_RTC_ALARM_HANDLER VectorE4 -#define STM32_RTC_TAMP_STAMP_NUMBER 2 -#define STM32_RTC_WKUP_NUMBER 3 -#define STM32_RTC_ALARM_NUMBER 41 -#define STM32_RTC_ALARM_EXTI 17 -#define STM32_RTC_TAMP_STAMP_EXTI 18 -#define STM32_RTC_WKUP_EXTI 19 -#define STM32_RTC_IRQ_ENABLE() do { \ - nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \ - nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ - nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ -} while (false) - -#define STM32_HAS_HASH1 TRUE -#define STM32_HAS_CRYP1 TRUE - -/*===========================================================================*/ -/* STM32WB55xx. */ -/*===========================================================================*/ - -#if defined(STM32WB55xx) || defined(__DOXYGEN__) - -/* Clock attributes.*/ -#define STM32_CLOCK_HAS_HSI48 TRUE - -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_HAS_CAN3 FALSE - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE -#define STM32_HAS_DAC1_CH2 FALSE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_SUPPORTS_DMAMUX TRUE -#define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 7 -#define STM32_DMA2_NUM_CHANNELS 7 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 40 -#define STM32_EXTI_IMR1_MASK 0x7FC00000U -#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U - -/* Flash attributes.*/ -#define STM32_FLASH_NUMBER_OF_BANKS 1 -#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/ - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ - RCC_AHB2ENR_GPIOBEN | \ - RCC_AHB2ENR_GPIOCEN | \ - RCC_AHB2ENR_GPIODEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C_USE_I2C2 FALSE - -/* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 TRUE - -/* SDMMC attributes.*/ -#define STM32_HAS_SDMMC1 FALSE -#define STM32_HAS_SDMMC2 FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S FALSE - -#define STM32_HAS_SPI3 FALSE -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 - -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 - -#define STM32_HAS_TIM3 FALSE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_LPUART1 TRUE -#define STM32_HAS_USART2 FALSE -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 1024 -#define STM32_USB_HAS_BCDR TRUE - -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED TRUE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE -#endif /* defined(STM32WB50xx) */ - -/*===========================================================================*/ -/* STM32WB50xx. */ -/*===========================================================================*/ - -#if defined(STM32WB50xx) || defined(__DOXYGEN__) -#error "STM32WB50xx is not supported" -#endif /* defined(STM32WB50xx) */ - -/** @} */ - -#endif /* STM32_REGISTRY_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Ilya Kharin. +*/ + +/** + * @file STM32WBxx/stm32_registry.h + * @brief STM32WBxx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef STM32_REGISTRY_H +#define STM32_REGISTRY_H + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32WBxx capabilities + * @{ + */ + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + +/* RNG attributes.*/ +#define STM32_HAS_RNG1 TRUE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_STORAGE_SIZE 80 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 18 +#define STM32_RTC_WKUP_EXTI 19 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) + +#define STM32_HAS_HASH1 TRUE +#define STM32_HAS_CRYP1 TRUE + +/*===========================================================================*/ +/* STM32WB55xx. */ +/*===========================================================================*/ + +#if defined(STM32WB55xx) || defined(__DOXYGEN__) + +/* Clock attributes.*/ +#define STM32_CLOCK_HAS_HSI48 TRUE + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA2_NUM_CHANNELS 7 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 49 +#define STM32_EXTI_IMR1_MASK 0x7FC00000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFCFDU + +/* Flash attributes.*/ +#define STM32_FLASH_NUMBER_OF_BANKS 1 +#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/ + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ + RCC_AHB2ENR_GPIOBEN | \ + RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIODEN | \ + RCC_AHB2ENR_GPIOEEN | \ + RCC_AHB2ENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C3 TRUE + +#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 2 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 2 + +#define STM32_HAS_TIM3 FALSE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_USART2 FALSE +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 1024 +#define STM32_USB_HAS_BCDR TRUE + +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE +#endif /* defined(STM32WB55xx) */ + +/*===========================================================================*/ +/* STM32WB50xx. */ +/*===========================================================================*/ + +#if defined(STM32WB50xx) || defined(__DOXYGEN__) +#error "STM32WB50xx is not supported" +#endif /* defined(STM32WB50xx) */ + +/*===========================================================================*/ +/* STM32WB35xx. */ +/*===========================================================================*/ + +#if defined(STM32WB35xx) || defined(__DOXYGEN__) +#error "STM32WB35xx is not supported" +#endif /* defined(STM32WB35xx) */ + +/*===========================================================================*/ +/* STM32WB30xx. */ +/*===========================================================================*/ + +#if defined(STM32WB30xx) || defined(__DOXYGEN__) +#error "STM32WB30xx is not supported" +#endif /* defined(STM32WB30xx) */ + +/** @} */ + +#endif /* STM32_REGISTRY_H */ + +/** @} */