OCTOSPI driver and demo, to be tested.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12395 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
gdisirio
parent
f42818b0a2
commit
9487a1f58c
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@ -30,6 +30,11 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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/* Workarounds for bugs in ST headers.*/
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#if !defined(OCTOSPI_FCR_CTOF) && defined(OCTOSPI_FCR_TOF)
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#define OCTOSPI_FCR_CTOF OCTOSPI_FCR_TOF
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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@ -39,6 +44,11 @@
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WSPIDriver WSPID1;
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#endif
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/** @brief OCTOSPI2 driver identifier.*/
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#if STM32_WSPI_USE_OCTOSPI2 || defined(__DOXYGEN__)
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WSPIDriver WSPID2;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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@ -102,8 +112,8 @@ OSAL_IRQ_HANDLER(STM32_OCTOSPI1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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OCTOSPI->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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OCTOSPI1->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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wspi_lld_serve_interrupt(&WSPID1);
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@ -112,6 +122,30 @@ OSAL_IRQ_HANDLER(STM32_OCTOSPI1_HANDLER) {
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#endif /* !defined(STM32_OCTOSPI1_SUPPRESS_ISR) */
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#endif /* STM32_WSPI_USE_OCTOSPI1 */
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#if STM32_WSPI_USE_OCTOSPI2 || defined(__DOXYGEN__)
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#if !defined(STM32_OCTOSPI2_SUPPRESS_ISR)
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#if !defined(STM32_OCTOSPI2_HANDLER)
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#error "STM32_OCTOSPI2_HANDLER not defined"
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#endif
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/**
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* @brief STM32_OCTOSPI2_HANDLER interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_OCTOSPI2_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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OCTOSPI2->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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wspi_lld_serve_interrupt(&WSPID2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(STM32_OCTOSPI2_SUPPRESS_ISR) */
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#endif /* STM32_WSPI_USE_OCTOSPI2 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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@ -125,8 +159,8 @@ void wspi_lld_init(void) {
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#if STM32_WSPI_USE_OCTOSPI1
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wspiObjectInit(&WSPID1);
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WSPID1.ospi = OCTOSPI;
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WSPID1.dma = STM32_DMA_STREAM(STM32_WSPI_OCTOSPI1_DMA_STREAM);
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WSPID1.ospi = OCTOSPI1;
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WSPID1.dma = STM32_DMA_STREAM(STM32_WSPI_OCTOSPI1_DMA_CHANNEL);
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WSPID1.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI1_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_BYTE |
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@ -136,6 +170,20 @@ void wspi_lld_init(void) {
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STM32_DMA_CR_TEIE;
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nvicEnableVector(STM32_OCTOSPI1_NUMBER, STM32_WSPI_OCTOSPI1_IRQ_PRIORITY);
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#endif
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#if STM32_WSPI_USE_OCTOSPI2
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wspiObjectInit(&WSPID2);
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WSPID2.ospi = OCTOSPI2;
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WSPID2.dma = STM32_DMA_STREAM(STM32_WSPI_OCTOSPI2_DMA_CHANNEL);
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WSPID2.dmamode = STM32_DMA_CR_CHSEL(OCTOSPI2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_WSPI_OCTOSPI2_DMA_PRIORITY) |
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STM32_DMA_CR_PSIZE_BYTE |
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STM32_DMA_CR_MSIZE_BYTE |
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STM32_DMA_CR_MINC |
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STM32_DMA_CR_DMEIE |
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STM32_DMA_CR_TEIE;
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nvicEnableVector(STM32_OCTOSPI2_NUMBER, STM32_WSPI_OCTOSPI2_IRQ_PRIORITY);
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#endif
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}
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/**
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@ -160,16 +208,29 @@ void wspi_lld_start(WSPIDriver *wspip) {
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}
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#endif
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#if STM32_WSPI_USE_OCTOSPI2
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if (&WSPID2 == wspip) {
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bool b = dmaStreamAllocate(wspip->dma,
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STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)wspi_lld_serve_dma_interrupt,
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(void *)wspip);
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osalDbgAssert(!b, "stream already allocated");
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rccEnableOCTOSPI2(true);
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}
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#endif
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/* Common initializations.*/
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dmaStreamSetPeripheral(wspip->dma, &wspip->ospi->DR);
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}
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/* WSPI setup and enable.*/
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wspip->ospi->DCR = wspip->config->dcr;
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wspip->ospi->CR = ((STM32_WSPI_OCTOSPI1_PRESCALER_VALUE - 1U) << 24U) |
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OCTOSPI_CR_TCIE | OCTOSPI_CR_DMAEN | OCTOSPI_CR_EN;
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wspip->ospi->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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wspip->ospi->DCR1 = wspip->config->dcr1;
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wspip->ospi->DCR2 = wspip->config->dcr2 |
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STM32_DCR2_PRESCALER(STM32_WSPI_OCTOSPI1_PRESCALER_VALUE - 1U);
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wspip->ospi->DCR3 = wspip->config->dcr3;
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wspip->ospi->CR = OCTOSPI_CR_TCIE | OCTOSPI_CR_DMAEN | OCTOSPI_CR_EN;
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wspip->ospi->FCR = OCTOSPI_FCR_CTEF | OCTOSPI_FCR_CTCF |
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OCTOSPI_FCR_CSMF | OCTOSPI_FCR_CTOF;
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}
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/**
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@ -210,7 +271,7 @@ void wspi_lld_stop(WSPIDriver *wspip) {
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*/
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void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
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#if STM32_USE_STM32_D1_WORKAROUND == TRUE
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#if 0 //STM32_USE_STM32_D1_WORKAROUND == TRUE
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/* If it is a command without address and alternate phases then the command
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is sent as an alternate byte, the command phase is suppressed.*/
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if ((cmdp->cfg & (WSPI_CFG_ADDR_MODE_MASK | WSPI_CFG_ALT_MODE_MASK)) == 0U) {
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@ -222,9 +283,12 @@ void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
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return;
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}
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#endif
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wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
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wspip->ospi->DLR = 0U;
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wspip->ospi->IR = cmdp->cmd;
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wspip->ospi->ABR = cmdp->alt;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg;
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wspip->ospi->TCR = cmdp->dummy;
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wspip->ospi->CCR = cmdp->cfg;
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if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
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wspip->ospi->AR = cmdp->addr;
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}
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@ -248,9 +312,12 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
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dmaStreamSetTransactionSize(wspip->dma, n);
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dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_M2P);
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wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
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wspip->ospi->DLR = n - 1;
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wspip->ospi->IR = cmdp->cmd;
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wspip->ospi->ABR = cmdp->alt;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg;
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wspip->ospi->TCR = cmdp->dummy;
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wspip->ospi->CCR = cmdp->cfg;
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if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
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wspip->ospi->AR = cmdp->addr;
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}
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@ -276,11 +343,12 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
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dmaStreamSetTransactionSize(wspip->dma, n);
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dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_P2M);
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wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) | OCTOSPI_CR_FMODE_0;
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wspip->ospi->DLR = n - 1;
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wspip->ospi->IR = cmdp->cmd;
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wspip->ospi->ABR = cmdp->alt;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg |
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OCTOSPI_CCR_DUMMY_CYCLES(cmdp->dummy) |
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OCTOSPI_CCR_FMODE_0;
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wspip->ospi->TCR = cmdp->dummy;
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wspip->ospi->CCR = cmdp->cfg;
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if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
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wspip->ospi->AR = cmdp->addr;
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}
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@ -309,11 +377,14 @@ void wspi_lld_map_flash(WSPIDriver *wspip,
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wspip->ospi->CR &= ~OCTOSPI_CR_DMAEN;
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/* Starting memory mapped mode using the passed parameters.*/
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wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) |
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(OCTOSPI_CR_FMODE_1 | OCTOSPI_CR_FMODE_0);
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wspip->ospi->DLR = 0;
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wspip->ospi->IR = cmdp->cmd;
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wspip->ospi->ABR = 0;
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wspip->ospi->TCR = cmdp->dummy;
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wspip->ospi->AR = 0;
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wspip->ospi->CCR = cmdp->cmd | cmdp->cfg |
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OCTOSPI_CCR_FMODE_1 | OCTOSPI_CCR_FMODE_0;
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wspip->ospi->CCR = cmdp->cfg;
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/* Mapped flash absolute base address.*/
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if (addrp != NULL) {
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#define WSPI_DEFAULT_CFG_MASKS TRUE
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/** @} */
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/**
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* @name DCR1 register options
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* @{
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*/
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#define STM32_DCR1_CK_MODE (1U << 0U)
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#define STM32_DCR1_FRCK_MODE (1U << 1U)
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#define STM32_DCR1_CSHT_MASK (7U << 8U)
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#define STM32_DCR1_CSHT(n) ((n) << 8U)
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#define STM32_DCR1_DEVSIZE_MASK (31U << 16U)
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#define STM32_DCR1_DEVSIZE(n) ((n) << 16U)
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#define STM32_DCR1_MTYP_MASK (7U << 16U)
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#define STM32_DCR1_MTYP(n) ((n) << 24U)
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/** @} */
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/**
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* @name DCR2 register options
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* @{
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*/
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#define STM32_DCR2_PRESCALER_MASK (255U << 0U)
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#define STM32_DCR2_PRESCALER(n) ((n) << 0U)
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#define STM32_DCR2_WRAPSIZE_MASK (7U << 16U)
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#define STM32_DCR2_WRAPSIZE(n) ((n) << 16U)
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/**
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* @name DCR3 register options
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* @{
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*/
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#define STM32_DCR3_MAXTRAN_MASK (255U << 0U)
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#define STM32_DCR3_MAXTRAN(n) ((n) << 0U)
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#define STM32_DCR3_CSBOUND_MASK (7U << 16U)
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#define STM32_DCR3_CSBOUND(n) ((n) << 16U)
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/**
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* @name DCR4 register options
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* @{
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*/
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#define STM32_DCR4_REFRESH_MASK (255U << 0U)
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#define STM32_DCR4_REFRESH(n) ((n) << 0U)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -56,6 +96,15 @@
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#define STM32_WSPI_USE_OCTOSPI1 FALSE
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#endif
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/**
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* @brief WSPID2 driver enable switch.
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* @details If set to @p TRUE the support for OCTOSPI2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_WSPI_USE_OCTOSPI2) || defined(__DOXYGEN__)
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#define STM32_WSPI_USE_OCTOSPI2 FALSE
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#endif
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/**
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* @brief OCTOSPI1 prescaler setting.
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* @note This is the prescaler divider value 1..256. The maximum frequency
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@ -66,6 +115,16 @@
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#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
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#endif
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/**
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* @brief OCTOSPI2 prescaler setting.
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* @note This is the prescaler divider value 1..256. The maximum frequency
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* varies depending on the STM32 model and operating conditions,
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* find the details in the data sheet.
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*/
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#if !defined(STM32_WSPI_OCTOSPI2_PRESCALER_VALUE) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
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#endif
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/**
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* @brief OCTOSPI1 interrupt priority level setting.
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*/
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@ -73,6 +132,13 @@
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#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief OCTOSPI2 interrupt priority level setting.
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*/
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#if !defined(STM32_WSPI_OCTOSPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief OCTOSPI1 DMA priority (0..3|lowest..highest).
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*/
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@ -80,6 +146,13 @@
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#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
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#endif
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/**
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* @brief OCTOSPI2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_WSPI_OCTOSPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
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#endif
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/**
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* @brief OCTOSPI1 DMA interrupt priority level setting.
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*/
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@ -87,6 +160,13 @@
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#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
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#endif
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/**
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* @brief OCTOSPI2 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
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#endif
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/**
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* @brief OCTOSPI DMA error hook.
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*/
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@ -103,11 +183,19 @@
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#define STM32_HAS_OCTOSPI1 FALSE
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#endif
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#if !defined(STM32_HAS_OCTOSPI2)
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#define STM32_HAS_OCTOSPI2 FALSE
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#endif
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#if STM32_WSPI_USE_OCTOSPI1 && !STM32_HAS_OCTOSPI1
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#error "OCTOSPI1 not present in the selected device"
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#endif
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#if !STM32_WSPI_USE_OCTOSPI1
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#if STM32_WSPI_USE_OCTOSPI2 && !STM32_HAS_OCTOSPI2
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#error "OCTOSPI2 not present in the selected device"
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#endif
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#if !STM32_WSPI_USE_OCTOSPI1 && !STM32_WSPI_USE_OCTOSPI2
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#error "WSPI driver activated but no OCTOSPI peripheral assigned"
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#endif
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@ -123,28 +211,52 @@
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#error "Invalid IRQ priority assigned to OCTOSPI1"
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#endif
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#if STM32_WSPI_USE_OCTOSPI2 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to OCTOSPI2"
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#endif
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#if STM32_WSPI_USE_OCTOSPI1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to OCTOSPI1 DMA"
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#endif
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/* Check on the presence of the DMA chennels settings in mcuconf.h.*/
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#if STM32_WSPI_USE_OCTOSPI2 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to OCTOSPI2 DMA"
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#endif
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/* Check on the presence of the DMA channels settings in mcuconf.h.*/
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#if STM32_WSPI_USE_OCTOSPI1 && !defined(STM32_WSPI_OCTOSPI1_DMA_CHANNEL)
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#error "OCTOSPI1 DMA channel not defined"
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#endif
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#if STM32_WSPI_USE_OCTOSPI2 && !defined(STM32_WSPI_OCTOSPI2_DMA_CHANNEL)
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#error "OCTOSPI2 DMA channel not defined"
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#endif
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/* Check on the validity of the assigned DMA channels.*/
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#if STM32_WSPI_USE_OCTOSPI1 && \
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!STM32_DMA_IS_VALID_CHANNEL(STM32_OCTOSPI1_DMA_MSK)
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!STM32_DMA_IS_VALID_CHANNEL(STM32_WSPI_OCTOSPI1_DMA_CHANNEL)
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#error "invalid DMA stream associated to OCTOSPI1"
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#endif
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#if STM32_WSPI_USE_OCTOSPI2 && \
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!STM32_DMA_IS_VALID_CHANNEL(STM32_WSPI_OCTOSPI2_DMA_CHANNEL)
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||||
#error "invalid DMA stream associated to OCTOSPI2"
|
||||
#endif
|
||||
|
||||
/* Check on DMA channels priority.*/
|
||||
#if STM32_WSPI_USE_OCTOSPI1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to OCTOSPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_WSPI_USE_OCTOSPI2 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_WSPI_OCTOSPI2_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to OCTOSPI2"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
|
@ -168,12 +280,18 @@ struct hal_wspi_config {
|
|||
uint32_t dcr1;
|
||||
/**
|
||||
* @brief DCR2 register initialization data.
|
||||
* @note Prescaler field is internally ORed to this field, leave it
|
||||
* to zero.
|
||||
*/
|
||||
uint32_t dcr2;
|
||||
/**
|
||||
* @brief DCR3 register initialization data.
|
||||
*/
|
||||
uint32_t dcr3;
|
||||
/**
|
||||
* @brief DCR4 register initialization data.
|
||||
*/
|
||||
uint32_t dcr4;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -230,6 +348,10 @@ struct hal_wspi_driver {
|
|||
extern WSPIDriver WSPID1;
|
||||
#endif
|
||||
|
||||
#if (STM32_WSPI_USE_OCTOSPI2 == TRUE) && !defined(__DOXYGEN__)
|
||||
extern WSPIDriver WSPID2;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
|
|||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OCTOSPIv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
|
||||
|
|
|
|||
|
|
@ -598,31 +598,54 @@
|
|||
/** @} */
|
||||
|
||||
/**
|
||||
* @name QUADSPI peripherals specific RCC operations
|
||||
* @name OCTOSPI peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the QUADSPI1 peripheral clock.
|
||||
* @brief Enables the OCTOSPI1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
|
||||
#define rccEnableOCTOSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the QUADSPI1 peripheral clock.
|
||||
* @brief Disables the OCTOSPI1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
|
||||
#define rccDisableOCTOSPI1() rccDisableAHB3(RCC_AHB3ENR_OSPI1EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the QUADSPI1 peripheral.
|
||||
* @brief Resets the OCTOSPI1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
|
||||
#define rccResetOCTOSPI1() rccResetAHB3(RCC_AHB3RSTR_OSPI1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the OCTOSPI2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableOCTOSPI2(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the OCTOSPI2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableOCTOSPI2() rccDisableAHB3(RCC_AHB3ENR_OSPI2EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the OCTOSPI1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetOCTOSPI2() rccResetAHB3(RCC_AHB3RSTR_OSPI2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -189,7 +189,11 @@
|
|||
/* OCTOSPI attributes.*/
|
||||
#define STM32_HAS_OCTOSPI1 TRUE
|
||||
#define STM32_OCTOSPI1_HANDLER Vector15C
|
||||
#define STM32_QUADSPI1_NUMBER 71
|
||||
#define STM32_OCTOSPI1_NUMBER 71
|
||||
|
||||
#define STM32_HAS_OCTOSPI2 TRUE
|
||||
#define STM32_OCTOSPI2_HANDLER Vector170
|
||||
#define STM32_OCTOSPI2_NUMBER 76
|
||||
|
||||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 FALSE
|
||||
|
|
|
|||
|
|
@ -69,6 +69,40 @@
|
|||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
<cconfiguration id="0.365230168.523175374.1317499780">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.365230168.523175374.1317499780" moduleId="org.eclipse.cdt.core.settings" name="Build for STM32L4R9I-Discovery">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.365230168.523175374.1317499780" name="Build for STM32L4R9I-Discovery" parent="org.eclipse.cdt.build.core.prefbase.cfg">
|
||||
<folderInfo id="0.365230168.523175374.1317499780." name="/" resourcePath="">
|
||||
<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.422616424" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
|
||||
<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.422616424.831498612" name=""/>
|
||||
<builder arguments="-f ./make/stm32l4r9_discovery.make" autoBuildTarget="all" cleanBuildTarget="clean" command="make" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.909647824" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1213130413" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.1946493293" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1093589864" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.1471618601" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.324762531" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.289663315" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1897662839" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="STM32-WSPI-MFS.null.1829068891" name="STM32-WSPI-MFS"/>
|
||||
|
|
@ -78,6 +112,9 @@
|
|||
<configuration configurationName="Default">
|
||||
<resource resourceType="PROJECT" workspacePath="/STM32-WSPI-MFS"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Build for STM32L4R9I-Discovery">
|
||||
<resource resourceType="PROJECT" workspacePath="/STM32-WSPI-MFS"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Build for STM32L476-Discovery"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
|
|
|||
|
|
@ -6,6 +6,9 @@ all:
|
|||
@echo
|
||||
@echo === Building for STM32L476-Discovery ===============================
|
||||
+@make --no-print-directory -f ./make/stm32l476_discovery.make all
|
||||
@echo
|
||||
@echo === Building for STM32L4R9-Discovery ===============================
|
||||
+@make --no-print-directory -f ./make/stm32l4r9_discovery.make all
|
||||
@echo ====================================================================
|
||||
@echo
|
||||
|
||||
|
|
@ -13,6 +16,8 @@ clean:
|
|||
@echo
|
||||
+@make --no-print-directory -f ./make/stm32l476_discovery.make clean
|
||||
@echo
|
||||
+@make --no-print-directory -f ./make/stm32l4r9_discovery.make clean
|
||||
@echo
|
||||
|
||||
#
|
||||
##############################################################################
|
||||
|
|
|
|||
|
|
@ -26,11 +26,22 @@
|
|||
|
||||
#include "portab.h"
|
||||
|
||||
#if defined(STM32_WSPI_USE_OCTOSPI1)
|
||||
/* 16MB device, 2 cycles delay after NCS.*/
|
||||
const WSPIConfig WSPIcfg1 = {
|
||||
.end_cb = NULL,
|
||||
.dcr = STM32_DCR_FSIZE(24) | STM32_DCR_CSHT(1)
|
||||
.dcr1 = STM32_DCR1_DEVSIZE(24U) | STM32_DCR1_CSHT(1U),
|
||||
.dcr2 = 0U,
|
||||
.dcr3 = 0U,
|
||||
.dcr4 = 0U
|
||||
};
|
||||
#else /* It is a quad SPI.*/
|
||||
/* 16MB device, 2 cycles delay after NCS.*/
|
||||
const WSPIConfig WSPIcfg1 = {
|
||||
.end_cb = NULL,
|
||||
.dcr = STM32_DCR_FSIZE(24U) | STM32_DCR_CSHT(1U)
|
||||
};
|
||||
#endif
|
||||
|
||||
const SNORConfig snorcfg1 = {
|
||||
.busp = &WSPID1,
|
||||
|
|
|
|||
Loading…
Reference in New Issue