Missing initializations and some code reorganization.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14500 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
cbb355f514
commit
94b88b3c41
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@ -249,6 +249,83 @@ static const system_limits_t vos_range2 = {
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#include "stm32_bd.inc"
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/**
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* @brief Configures the PWR unit.
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* @note CR1, CR2 and CR5 are not initialized inside this function.
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*/
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static void hal_lld_set_static_pwr(void) {
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/* PWR clock enabled.*/
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rccEnablePWRInterface(false);
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/* Static PWR configurations.*/
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PWR->CR3 = STM32_PWR_CR3;
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PWR->CR4 = STM32_PWR_CR4;
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PWR->PUCRA = STM32_PWR_PUCRA;
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PWR->PDCRA = STM32_PWR_PDCRA;
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PWR->PUCRB = STM32_PWR_PUCRB;
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PWR->PDCRB = STM32_PWR_PDCRB;
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PWR->PUCRC = STM32_PWR_PUCRC;
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PWR->PDCRC = STM32_PWR_PDCRC;
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#if STM32_HAS_GPIOD
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PWR->PUCRD = STM32_PWR_PUCRD;
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PWR->PDCRD = STM32_PWR_PDCRD;
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#endif
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#if STM32_HAS_GPIOE
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PWR->PUCRE = STM32_PWR_PUCRE;
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PWR->PDCRE = STM32_PWR_PDCRE;
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#endif
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#if STM32_HAS_GPIOF
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PWR->PUCRF = STM32_PWR_PUCRF;
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PWR->PDCRF = STM32_PWR_PDCRF;
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#endif
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#if STM32_HAS_GPIOG
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PWR->PUCRG = STM32_PWR_PUCRG;
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PWR->PDCRG = STM32_PWR_PDCRG;
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#endif
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#if STM32_HAS_GPIOH
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PWR->PUCRH = STM32_PWR_PUCRH;
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PWR->PDCRH = STM32_PWR_PDCRH;
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#endif
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#if STM32_HAS_GPIOI
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PWR->PUCRI = STM32_PWR_PUCRI;
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PWR->PDCRI = STM32_PWR_PDCRI;
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#endif
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}
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/**
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* @brief Initializes static muxes and dividers.
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*/
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static void hal_lld_set_static_clocks(void) {
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uint32_t ccipr;
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/*Clock-related settings (dividers, MCO etc).*/
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RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
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STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* CCIPR register initialization, note, must take care of the _OFF
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pseudo settings.*/
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ccipr = STM32_ADCSEL |
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STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
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STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
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STM32_LPUART1SEL | STM32_UART5SEL | STM32_UART4SEL |
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STM32_USART3SEL | STM32_USART2SEL | STM32_USART1SEL;
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RCC->CCIPR = ccipr;
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/* CCIPR2 register initialization, note, must take care of the _OFF
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pseudo settings.*/
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ccipr = STM32_OSPISEL | STM32_PLLSAI2DIVR |
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STM32_SDMMCSEL | STM32_DSISEL | STM32_ADFSDMSEL |
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STM32_DFSDMSEL | STM32_I2C4SEL;
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#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
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ccipr |= STM32_SAI2SEL;
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#endif
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#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
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ccipr |= STM32_SAI1SEL;
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#endif
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RCC->CCIPR2 = ccipr;
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}
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#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
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static bool hal_lld_check_pll(const system_limits_t *slp,
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uint32_t cfgr,
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@ -703,44 +780,12 @@ void stm32_clock_init(void) {
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(false);
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/* Static PWR configurations.*/
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hal_lld_set_static_pwr();
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/* Backup domain made accessible.*/
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PWR->CR1 |= PWR_CR1_DBP;
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/* Static PWR initializations.*/
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PWR->PUCRA = STM32_PWR_PUCRA;
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PWR->PDCRA = STM32_PWR_PDCRA;
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PWR->PUCRB = STM32_PWR_PUCRB;
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PWR->PDCRB = STM32_PWR_PDCRB;
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PWR->PUCRC = STM32_PWR_PUCRC;
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PWR->PDCRC = STM32_PWR_PDCRC;
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#if STM32_HAS_GPIOD
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PWR->PUCRD = STM32_PWR_PUCRD;
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PWR->PDCRD = STM32_PWR_PDCRD;
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#endif
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#if STM32_HAS_GPIOE
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PWR->PUCRE = STM32_PWR_PUCRE;
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PWR->PDCRE = STM32_PWR_PDCRE;
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#endif
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#if STM32_HAS_GPIOF
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PWR->PUCRF = STM32_PWR_PUCRF;
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PWR->PDCRF = STM32_PWR_PDCRF;
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#endif
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#if STM32_HAS_GPIOG
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PWR->PUCRG = STM32_PWR_PUCRG;
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PWR->PDCRG = STM32_PWR_PDCRG;
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#endif
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#if STM32_HAS_GPIOH
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PWR->PUCRH = STM32_PWR_PUCRH;
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PWR->PDCRH = STM32_PWR_PDCRH;
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#endif
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#if STM32_HAS_GPIOI
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PWR->PUCRI = STM32_PWR_PUCRI;
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PWR->PDCRI = STM32_PWR_PDCRI;
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#endif
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/* Backup domain reset.*/
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bd_reset();
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@ -752,6 +797,9 @@ void stm32_clock_init(void) {
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RCC->CR |= RCC_CR_MSIRGSEL;
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RCC->CSR = (RCC->CSR & ~RCC_CSR_MSISRANGE_Msk) | STM32_MSISRANGE;
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/* Static clocks setup.*/
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hal_lld_set_static_clocks();
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/* Selecting the default clock/power/flash configuration.*/
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if (hal_lld_clock_raw_switch(&hal_clkcfg_default)) {
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osalSysHalt("clkswc");
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@ -791,50 +839,18 @@ void stm32_clock_init(void) {
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(false);
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/* Static PWR configurations.*/
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hal_lld_set_static_pwr();
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/* Additional PWR configurations.*/
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PWR->CR2 = STM32_PWR_CR2;
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PWR->CR5 = STM32_CR5BITS;
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/* Core voltage setup, backup domain access enabled and left open.*/
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PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
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while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
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; /* stable. */
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/* Additional PWR configurations.*/
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PWR->CR2 = STM32_PWR_CR2;
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PWR->CR3 = STM32_PWR_CR3;
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PWR->CR4 = STM32_PWR_CR4;
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PWR->CR5 = STM32_CR5BITS;
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PWR->PUCRA = STM32_PWR_PUCRA;
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PWR->PDCRA = STM32_PWR_PDCRA;
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PWR->PUCRB = STM32_PWR_PUCRB;
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PWR->PDCRB = STM32_PWR_PDCRB;
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PWR->PUCRC = STM32_PWR_PUCRC;
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PWR->PDCRC = STM32_PWR_PDCRC;
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#if STM32_HAS_GPIOD
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PWR->PUCRD = STM32_PWR_PUCRD;
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PWR->PDCRD = STM32_PWR_PDCRD;
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#endif
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#if STM32_HAS_GPIOE
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PWR->PUCRE = STM32_PWR_PUCRE;
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PWR->PDCRE = STM32_PWR_PDCRE;
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#endif
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#if STM32_HAS_GPIOF
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PWR->PUCRF = STM32_PWR_PUCRF;
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PWR->PDCRF = STM32_PWR_PDCRF;
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#endif
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#if STM32_HAS_GPIOG
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PWR->PUCRG = STM32_PWR_PUCRG;
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PWR->PDCRG = STM32_PWR_PDCRG;
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#endif
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#if STM32_HAS_GPIOH
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PWR->PUCRH = STM32_PWR_PUCRH;
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PWR->PDCRH = STM32_PWR_PDCRH;
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#endif
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#if STM32_HAS_GPIOI
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PWR->PUCRI = STM32_PWR_PUCRI;
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PWR->PDCRI = STM32_PWR_PDCRI;
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#endif
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/* MSI clock reset.*/
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msi_reset();
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@ -857,35 +873,8 @@ void stm32_clock_init(void) {
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pllsai1_init();
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pllsai2_init();
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
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STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* CCIPR register initialization, note, must take care of the _OFF
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pseudo settings.*/
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{
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uint32_t ccipr = STM32_ADCSEL |
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STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
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STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
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STM32_LPUART1SEL | STM32_UART5SEL | STM32_UART4SEL |
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STM32_USART3SEL | STM32_USART2SEL | STM32_USART1SEL;
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RCC->CCIPR = ccipr;
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}
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/* CCIPR2 register initialization, note, must take care of the _OFF
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pseudo settings.*/
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{
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uint32_t ccipr = STM32_OSPISEL | STM32_PLLSAI2DIVR |
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STM32_SDMMCSEL | STM32_DSISEL | STM32_ADFSDMSEL |
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STM32_DFSDMSEL | STM32_I2C4SEL;
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#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
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ccipr |= STM32_SAI2SEL;
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#endif
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#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
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ccipr |= STM32_SAI1SEL;
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#endif
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RCC->CCIPR2 = ccipr;
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}
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/* Static clocks setup.*/
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hal_lld_set_static_clocks();
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/* Set flash WS's for SYSCLK source */
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if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
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