From 94be09c796428e600fd0578113cdaf3ed1a769c2 Mon Sep 17 00:00:00 2001
From: vrepetenko <none@example.com>
Date: Sun, 25 Jul 2021 06:50:44 +0000
Subject: [PATCH] Added STM32WL support.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14617 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c | 16 ++++++++--------
 os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h |  6 +++---
 os/hal/ports/STM32/LLD/ADCv5/notes.txt     |  4 ++--
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c
index 00efe3273..b857b26a6 100644
--- a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c
+++ b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c
@@ -173,7 +173,7 @@ void adc_lld_init(void) {
   rccEnableADC1(true);
 
   /* CCR setup.*/
-  ADC->CCR = STM32_ADC_PRESC << 18;
+  ADC1_COMMON->CCR = STM32_ADC_PRESC << 18;
 
   /* Regulator enabled and stabilized before calibration.*/
   adc_lld_vreg_on(ADC1);
@@ -241,7 +241,7 @@ void adc_lld_stop(ADCDriver *adcp) {
     adcp->dmastp = NULL;
 
     /* Restoring CCR default.*/
-    ADC->CCR = STM32_ADC_PRESC << 18;
+    ADC1_COMMON->CCR = STM32_ADC_PRESC << 18;
 
     /* Disabling ADC.*/
     if (adcp->adc->CR & ADC_CR_ADEN) {
@@ -385,7 +385,7 @@ void adcSTM32EnableVREF(ADCDriver *adcp) {
 
   (void)adcp;
 
-  ADC->CCR |= ADC_CCR_VREFEN;
+  ADC1_COMMON->CCR |= ADC_CCR_VREFEN;
 }
 
 /**
@@ -402,7 +402,7 @@ void adcSTM32DisableVREF(ADCDriver *adcp) {
 
   (void)adcp;
 
-  ADC->CCR &= ~ADC_CCR_VREFEN;
+  ADC1_COMMON->CCR &= ~ADC_CCR_VREFEN;
 }
 
 /**
@@ -419,7 +419,7 @@ void adcSTM32EnableTS(ADCDriver *adcp) {
 
   (void)adcp;
 
-  ADC->CCR |= ADC_CCR_TSEN;
+  ADC1_COMMON->CCR |= ADC_CCR_TSEN;
 }
 
 /**
@@ -436,7 +436,7 @@ void adcSTM32DisableTS(ADCDriver *adcp) {
 
   (void)adcp;
 
-  ADC->CCR &= ~ADC_CCR_TSEN;
+  ADC1_COMMON->CCR &= ~ADC_CCR_TSEN;
 }
 
 #if defined(ADC_CCR_VBATEN) || defined(__DOXYGEN__)
@@ -454,7 +454,7 @@ void adcSTM32EnableVBAT(ADCDriver *adcp) {
 
   (void)adcp;
 
-  ADC->CCR |= ADC_CCR_VBATEN;
+  ADC1_COMMON->CCR |= ADC_CCR_VBATEN;
 }
 
 /**
@@ -471,7 +471,7 @@ void adcSTM32DisableVBAT(ADCDriver *adcp) {
 
   (void)adcp;
 
-  ADC->CCR &= ~ADC_CCR_VBATEN;
+  ADC1_COMMON->CCR &= ~ADC_CCR_VBATEN;
 }
 #endif /* defined(ADC_CCR_VBATEN) */
 
diff --git a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
index 642760512..16e35250e 100644
--- a/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
@@ -200,8 +200,8 @@
 /*===========================================================================*/
 
 /* Supported devices checks.*/
-#if !defined(STM32G0XX)
-#error "ADCv5 only supports G0 STM32 devices"
+#if !defined(STM32G0XX) && !defined(STM32WLXX)
+#error "ADCv5 only supports G0 and WL STM32 devices"
 #endif
 
 /* Registry checks.*/
@@ -366,7 +366,7 @@ typedef uint32_t adcerror_t;
  *          Manual.
  * @note    PRESC bits must not be specified and left to zero.
  */
-#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
+#define adcSTM32SetCCR(ccr) (ADC1_COMMON->CCR = (ccr))
 
 /*===========================================================================*/
 /* External declarations.                                                    */
diff --git a/os/hal/ports/STM32/LLD/ADCv5/notes.txt b/os/hal/ports/STM32/LLD/ADCv5/notes.txt
index 283e5c37a..941c7d1af 100644
--- a/os/hal/ports/STM32/LLD/ADCv5/notes.txt
+++ b/os/hal/ports/STM32/LLD/ADCv5/notes.txt
@@ -1,8 +1,8 @@
-STM32 ADCv1 driver.
+STM32 ADCv5 driver.
 
 Driver capability:
 
-- Supports the STM32 "simple" ADC, the one found on small devices (G0).
+- Supports the STM32 "simple" ADC, the one found on small devices (G0 and WL).
 
 The file registry must export: