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Upgrades to STM32 GPT, ICU and PWM drivers. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6150 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2013-08-15 08:17:27 +00:00
parent 7391ec61e2
commit 9568ccf9d1
27 changed files with 142 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
demos/ARMCM3-STM32F100-DISCOVERY/main.c
View File

@ -71,6 +71,7 @@ static PWMConfig pwmcfg = {
}, },
/* HW dependent part.*/ /* HW dependent part.*/
0, 0,
0,
#if STM32_PWM_USE_ADVANCED #if STM32_PWM_USE_ADVANCED
0 0
#endif #endif

1
demos/ARMCM3-STM32L152-DISCOVERY/main.c
View File

@ -73,6 +73,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
/* HW dependent part.*/ /* HW dependent part.*/
0,
0 0
}; };

1
demos/ARMCM4-STM32F407-DISCOVERY-MEMS/main.c
View File

@ -117,6 +117,7 @@ static const PWMConfig pwmcfg = {
{PWM_OUTPUT_ACTIVE_HIGH, NULL} {PWM_OUTPUT_ACTIVE_HIGH, NULL}
}, },
/* HW dependent part.*/ /* HW dependent part.*/
0,
0 0
}; };

1
demos/ARMCM4-STM32F407-DISCOVERY/main.c
View File

@ -70,6 +70,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_ACTIVE_HIGH, NULL} {PWM_OUTPUT_ACTIVE_HIGH, NULL}
}, },
/* HW dependent part.*/ /* HW dependent part.*/
0,
0 0
}; };

42
os/hal/platforms/STM32/TIMv1/gpt_lld.c
View File

@ -606,10 +606,12 @@ void gpt_lld_start(GPTDriver *gptp) {
"gpt_lld_start(), #1", "invalid frequency"); "gpt_lld_start(), #1", "invalid frequency");
/* Timer configuration.*/ /* Timer configuration.*/
gptp->tim->CR1 = 0; /* Initially stopped. */ gptp->tim->CR1 = 0; /* Initially stopped. */
gptp->tim->CR2 = STM32_TIM_CR2_CCDS; /* DMA on UE (if any). */ gptp->tim->CR2 = STM32_TIM_CR2_CCDS; /* DMA on UE (if any). */
gptp->tim->PSC = psc; /* Prescaler value. */ gptp->tim->PSC = psc; /* Prescaler value. */
gptp->tim->DIER = 0; gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
STM32_TIM_DIER_IRQ_MASK;
gptp->tim->SR = 0; /* Clear pending IRQs. */
} }
/** /**
@ -622,9 +624,9 @@ void gpt_lld_start(GPTDriver *gptp) {
void gpt_lld_stop(GPTDriver *gptp) { void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) { if (gptp->state == GPT_READY) {
gptp->tim->CR1 = 0; /* Timer disabled. */ gptp->tim->CR1 = 0; /* Timer disabled. */
gptp->tim->DIER = 0; /* All IRQs disabled. */ gptp->tim->DIER = 0; /* All IRQs disabled. */
gptp->tim->SR = 0; /* Clear eventual pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
#if STM32_GPT_USE_TIM1 #if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
@ -711,16 +713,16 @@ void gpt_lld_stop(GPTDriver *gptp) {
*/ */
void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
gptp->tim->ARR = interval - 1; /* Time constant. */ gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */
gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
gptp->tim->CNT = 0; /* Reset counter. */ gptp->tim->CNT = 0; /* Reset counter. */
/* NOTE: After generating the UG event it takes several clock cycles before /* NOTE: After generating the UG event it takes several clock cycles before
SR bit 0 goes to 1. This is because the clearing of CNT has been inserted SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
before the clearing of SR, to give it some time.*/ before the clearing of SR, to give it some time.*/
gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->DIER = STM32_TIM_DIER_UIE; /* Update Event IRQ enabled. */ gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
gptp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; gptp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
} }
/** /**
@ -732,9 +734,11 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
*/ */
void gpt_lld_stop_timer(GPTDriver *gptp) { void gpt_lld_stop_timer(GPTDriver *gptp) {
gptp->tim->CR1 = 0; /* Initially stopped. */ gptp->tim->CR1 = 0; /* Initially stopped. */
gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->DIER = 0; /* Interrupts disabled. */
/* All interrupts disabled.*/
gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
} }
/** /**
@ -750,9 +754,9 @@ void gpt_lld_stop_timer(GPTDriver *gptp) {
*/ */
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
gptp->tim->ARR = interval - 1; /* Time constant. */ gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */
gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
while (!(gptp->tim->SR & STM32_TIM_SR_UIF)) while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
; ;

10
os/hal/platforms/STM32/TIMv1/gpt_lld.h
View File

@ -367,7 +367,7 @@ typedef uint32_t gptfreq_t;
/** /**
* @brief GPT counter type. * @brief GPT counter type.
*/ */
typedef uint16_t gptcnt_t; typedef uint32_t gptcnt_t;
/** /**
* @brief Driver configuration structure. * @brief Driver configuration structure.
@ -386,6 +386,12 @@ typedef struct {
*/ */
gptcallback_t callback; gptcallback_t callback;
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
/**
* @brief TIM CR2 register initialization data.
* @note The value of this field should normally be equal to zero.
* @note Only the DMA-related bits can be specified in this field.
*/
uint32_t dier;
} GPTConfig; } GPTConfig;
/** /**
@ -432,7 +438,7 @@ struct GPTDriver {
* @notapi * @notapi
*/ */
#define gpt_lld_change_interval(gptp, interval) \ #define gpt_lld_change_interval(gptp, interval) \
((gptp)->tim->ARR = (uint16_t)((interval) - 1)) ((gptp)->tim->ARR = (uint32_t)((interval) - 1))
/*===========================================================================*/ /*===========================================================================*/
/* External declarations. */ /* External declarations. */

13
os/hal/platforms/STM32/TIMv1/icu_lld.c
View File

@ -112,7 +112,7 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
uint16_t sr; uint16_t sr;
sr = icup->tim->SR; sr = icup->tim->SR;
sr &= icup->tim->DIER; sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
icup->tim->SR = ~sr; icup->tim->SR = ~sr;
if (icup->config->channel == ICU_CHANNEL_1) { if (icup->config->channel == ICU_CHANNEL_1) {
if ((sr & STM32_TIM_SR_CC1IF) != 0) if ((sr & STM32_TIM_SR_CC1IF) != 0)
@ -468,7 +468,8 @@ void icu_lld_start(ICUDriver *icup) {
else { else {
/* Driver re-configuration scenario, it must be stopped first.*/ /* Driver re-configuration scenario, it must be stopped first.*/
icup->tim->CR1 = 0; /* Timer disabled. */ icup->tim->CR1 = 0; /* Timer disabled. */
icup->tim->DIER = 0; /* All IRQs disabled. */ icup->tim->DIER = icup->config->dier &/* DMA-related DIER settings. */
~STM32_TIM_DIER_IRQ_MASK;
icup->tim->SR = 0; /* Clear eventual pending IRQs. */ icup->tim->SR = 0; /* Clear eventual pending IRQs. */
icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */
icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */
@ -631,9 +632,11 @@ void icu_lld_enable(ICUDriver *icup) {
*/ */
void icu_lld_disable(ICUDriver *icup) { void icu_lld_disable(ICUDriver *icup) {
icup->tim->CR1 = 0; /* Initially stopped. */ icup->tim->CR1 = 0; /* Initially stopped. */
icup->tim->SR = 0; /* Clear pending IRQs (if any). */ icup->tim->SR = 0; /* Clear pending IRQs (if any). */
icup->tim->DIER = 0; /* Interrupts disabled. */
/* All interrupts disabled.*/
icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
} }
#endif /* HAL_USE_ICU */ #endif /* HAL_USE_ICU */

6
os/hal/platforms/STM32/TIMv1/icu_lld.h
View File

@ -291,6 +291,12 @@ typedef struct {
* @note Only inputs TIMx 1 and 2 are supported. * @note Only inputs TIMx 1 and 2 are supported.
*/ */
icuchannel_t channel; icuchannel_t channel;
/**
* @brief TIM CR2 register initialization data.
* @note The value of this field should normally be equal to zero.
* @note Only the DMA-related bits can be specified in this field.
*/
uint32_t dier;
} ICUConfig; } ICUConfig;
/** /**

30
os/hal/platforms/STM32/TIMv1/pwm_lld.c
View File

@ -113,7 +113,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
uint16_t sr; uint16_t sr;
sr = pwmp->tim->SR; sr = pwmp->tim->SR;
sr &= pwmp->tim->DIER; sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
pwmp->tim->SR = ~sr; pwmp->tim->SR = ~sr;
if ((sr & STM32_TIM_SR_CC1IF) != 0) if ((sr & STM32_TIM_SR_CC1IF) != 0)
pwmp->config->channels[0].callback(pwmp); pwmp->config->channels[0].callback(pwmp);
@ -170,9 +170,8 @@ CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
sr = STM32_TIM1->SR & STM32_TIM1->DIER; sr = STM32_TIM1->SR & STM32_TIM1->DIER & STM32_TIM_DIER_IRQ_MASK;
STM32_TIM1->SR = ~(STM32_TIM_SR_CC1IF | STM32_TIM_SR_CC2IF | STM32_TIM1->SR = ~sr;
STM32_TIM_SR_CC3IF | STM32_TIM_SR_CC4IF);
if ((sr & STM32_TIM_SR_CC1IF) != 0) if ((sr & STM32_TIM_SR_CC1IF) != 0)
PWMD1.config->channels[0].callback(&PWMD1); PWMD1.config->channels[0].callback(&PWMD1);
if ((sr & STM32_TIM_SR_CC2IF) != 0) if ((sr & STM32_TIM_SR_CC2IF) != 0)
@ -300,9 +299,8 @@ CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
sr = STM32_TIM8->SR & STM32_TIM8->DIER; sr = STM32_TIM8->SR & STM32_TIM8->DIER & STM32_TIM_DIER_IRQ_MASK;
STM32_TIM8->SR = ~(STM32_TIM_SR_CC1IF | STM32_TIM_SR_CC2IF | STM32_TIM8->SR = ~sr;
STM32_TIM_SR_CC3IF | STM32_TIM_SR_CC4IF);
if ((sr & STM32_TIM_SR_CC1IF) != 0) if ((sr & STM32_TIM_SR_CC1IF) != 0)
PWMD8.config->channels[0].callback(&PWMD8); PWMD8.config->channels[0].callback(&PWMD8);
if ((sr & STM32_TIM_SR_CC2IF) != 0) if ((sr & STM32_TIM_SR_CC2IF) != 0)
@ -483,7 +481,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
else { else {
/* Driver re-configuration scenario, it must be stopped first.*/ /* Driver re-configuration scenario, it must be stopped first.*/
pwmp->tim->CR1 = 0; /* Timer disabled. */ pwmp->tim->CR1 = 0; /* Timer disabled. */
pwmp->tim->DIER = 0; /* All IRQs disabled. */ pwmp->tim->DIER = pwmp->config->dier &/* DMA-related DIER settings. */
~STM32_TIM_DIER_IRQ_MASK;
pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */
pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */
pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */
@ -572,19 +571,20 @@ void pwm_lld_start(PWMDriver *pwmp) {
} }
#endif /* STM32_PWM_USE_ADVANCED*/ #endif /* STM32_PWM_USE_ADVANCED*/
pwmp->tim->CCER = ccer; pwmp->tim->CCER = ccer;
pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ pwmp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE; pwmp->tim->DIER |= pwmp->config->callback == NULL ? 0 : STM32_TIM_DIER_UIE;
pwmp->tim->SR = 0; /* Clear pending IRQs. */ pwmp->tim->SR = 0; /* Clear pending IRQs. */
#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8 #if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
#if STM32_PWM_USE_ADVANCED #if STM32_PWM_USE_ADVANCED
pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE; pwmp->tim->BDTR = pwmp->config->bdtr | STM32_TIM_BDTR_MOE;
#else #else
pwmp->tim->BDTR = STM32_TIM_BDTR_MOE; pwmp->tim->BDTR = STM32_TIM_BDTR_MOE;
#endif #endif
#endif #endif
/* Timer configured and started.*/ /* Timer configured and started.*/
pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; pwmp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS |
STM32_TIM_CR1_CEN;
} }
/** /**

10
os/hal/platforms/STM32/TIMv1/pwm_lld.h
View File

@ -345,14 +345,20 @@ typedef struct {
* @brief TIM CR2 register initialization data. * @brief TIM CR2 register initialization data.
* @note The value of this field should normally be equal to zero. * @note The value of this field should normally be equal to zero.
*/ */
uint16_t cr2; uint32_t cr2;
#if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__) #if STM32_PWM_USE_ADVANCED || defined(__DOXYGEN__)
/** /**
* @brief TIM BDTR (break & dead-time) register initialization data. * @brief TIM BDTR (break & dead-time) register initialization data.
* @note The value of this field should normally be equal to zero. * @note The value of this field should normally be equal to zero.
*/ \ */ \
uint16_t bdtr; uint32_t bdtr;
#endif #endif
/**
* @brief TIM CR2 register initialization data.
* @note The value of this field should normally be equal to zero.
* @note Only the DMA-related bits can be specified in this field.
*/
uint32_t dier;
} PWMConfig; } PWMConfig;
/** /**

11
os/hal/platforms/STM32/TIMv1/stm32_tim.h
View File

@ -121,6 +121,17 @@
#define STM32_TIM_DIER_CC4DE (1U << 12) #define STM32_TIM_DIER_CC4DE (1U << 12)
#define STM32_TIM_DIER_COMDE (1U << 13) #define STM32_TIM_DIER_COMDE (1U << 13)
#define STM32_TIM_DIER_TDE (1U << 14) #define STM32_TIM_DIER_TDE (1U << 14)
#define STM32_TIM_DIER_IRQ_MASK (STM32_TIM_DIER_UIE | \
STM32_TIM_DIER_CC1IE | \
STM32_TIM_DIER_CC2IE | \
STM32_TIM_DIER_CC3IE | \
STM32_TIM_DIER_CC4IE | \
STM32_TIM_DIER_COMIE | \
STM32_TIM_DIER_TIE | \
STM32_TIM_DIER_BIE | \
STM32_TIM_DIER_UDE)
/** @} */ /** @} */
/** /**

5
readme.txt
View File

@ -112,6 +112,9 @@
(backported to 2.6.0). (backported to 2.6.0).
- FIX: Fixed MS2ST() and US2ST() macros error (bug #415)(backported to 2.6.0, - FIX: Fixed MS2ST() and US2ST() macros error (bug #415)(backported to 2.6.0,
2.4.4, 2.2.10, NilRTOS). 2.4.4, 2.2.10, NilRTOS).
- NEW: Added initializer for the DIER register to the STM32 GPT, ICU and
PWM drivers.
- NEW: Added support for 32bits counters to the STM32 GPT driver.
- NEW: Added support for STM32F4xx backup RAM. - NEW: Added support for STM32F4xx backup RAM.
- NEW: Added port support for SCP560B64. - NEW: Added port support for SCP560B64.
- NEW: Added DAC driver high level files and low level files templates. - NEW: Added DAC driver high level files and low level files templates.
@ -120,6 +123,8 @@
- NEW: SPI driver for SPC560Pxx, SPC563Mxx, SPC564Axx, SPC56ELAxx, SPC560Dxx. - NEW: SPI driver for SPC560Pxx, SPC563Mxx, SPC564Axx, SPC56ELAxx, SPC560Dxx.
- NEW: Support for SPC560Dxx devices. - NEW: Support for SPC560Dxx devices.
- NEW: DMA-MUX support for SPC5xx devices. - NEW: DMA-MUX support for SPC5xx devices.
- CHANGE: Moved the STM32 GPT, ICU and PWM low level drivers under
./os/hal/platform/STM32/TIMv1. Updated all the impacted project files.
*** 2.5.2 *** *** 2.5.2 ***
- FIX: Fixed lwipthread.h should explicitly include lwip/opts.h (bug #414). - FIX: Fixed lwipthread.h should explicitly include lwip/opts.h (bug #414).

6
testhal/STM32F0xx/IRQ_STORM/main.c
View File

@ -147,7 +147,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -155,7 +156,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };

4
testhal/STM32F0xx/PWM-ICU/main.c
View File

@ -40,6 +40,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0
}; };
icucnt_t last_width, last_period; icucnt_t last_width, last_period;
@ -67,7 +68,8 @@ static ICUConfig icucfg = {
icuwidthcb, icuwidthcb,
icuperiodcb, icuperiodcb,
icuoverflowcb, icuoverflowcb,
ICU_CHANNEL_1 ICU_CHANNEL_1,
0
}; };
/* /*

6
testhal/STM32F1xx/GPT/main.c
View File

@ -43,7 +43,8 @@ static void gpt2cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt1cfg = { static const GPTConfig gpt1cfg = {
10000, /* 10kHz timer clock.*/ 10000, /* 10kHz timer clock.*/
gpt1cb /* Timer callback.*/ gpt1cb, /* Timer callback.*/
0
}; };
/* /*
@ -51,7 +52,8 @@ static const GPTConfig gpt1cfg = {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
10000, /* 10kHz timer clock.*/ 10000, /* 10kHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*

6
testhal/STM32F1xx/IRQ_STORM/main.c
View File

@ -147,7 +147,8 @@ static void gpt2cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt1cfg = { static const GPTConfig gpt1cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt1cb /* Timer callback.*/ gpt1cb, /* Timer callback.*/
0
}; };
/* /*
@ -155,7 +156,8 @@ static const GPTConfig gpt1cfg = {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };

4
testhal/STM32F1xx/PWM-ICU/main.c
View File

@ -40,6 +40,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0,
#if STM32_PWM_USE_ADVANCED #if STM32_PWM_USE_ADVANCED
0 0
#endif #endif
@ -63,7 +64,8 @@ static ICUConfig icucfg = {
icuwidthcb, icuwidthcb,
icuperiodcb, icuperiodcb,
NULL, NULL,
ICU_CHANNEL_1 ICU_CHANNEL_1,
0
}; };
/* /*

6
testhal/STM32F30x/IRQ_STORM/main.c
View File

@ -147,7 +147,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -155,7 +156,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };

4
testhal/STM32F30x/PWM-ICU/main.c
View File

@ -40,6 +40,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0
}; };
icucnt_t last_width, last_period; icucnt_t last_width, last_period;
@ -62,7 +63,8 @@ static ICUConfig icucfg = {
icuwidthcb, icuwidthcb,
icuperiodcb, icuperiodcb,
NULL, NULL,
ICU_CHANNEL_1 ICU_CHANNEL_1,
0
}; };
/* /*

6
testhal/STM32F37x/IRQ_STORM/main.c
View File

@ -147,7 +147,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -155,7 +156,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };

4
testhal/STM32F37x/PWM-ICU/main.c
View File

@ -40,6 +40,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0
}; };
icucnt_t last_width, last_period; icucnt_t last_width, last_period;
@ -62,7 +63,8 @@ static ICUConfig icucfg = {
icuwidthcb, icuwidthcb,
icuperiodcb, icuperiodcb,
NULL, NULL,
ICU_CHANNEL_1 ICU_CHANNEL_1,
0
}; };
/* /*

6
testhal/STM32F4xx/GPT/main.c
View File

@ -43,7 +43,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
10000, /* 10kHz timer clock.*/ 10000, /* 10kHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -51,7 +52,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
10000, /* 10kHz timer clock.*/ 10000, /* 10kHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };
/* /*

6
testhal/STM32F4xx/IRQ_STORM/main.c
View File

@ -147,7 +147,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -155,7 +156,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };

6
testhal/STM32F4xx/IRQ_STORM_FPU/main.c
View File

@ -127,7 +127,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -135,7 +136,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };

4
testhal/STM32F4xx/PWM-ICU/main.c
View File

@ -40,6 +40,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0
}; };
icucnt_t last_width, last_period; icucnt_t last_width, last_period;
@ -62,7 +63,8 @@ static ICUConfig icucfg = {
icuwidthcb, icuwidthcb,
icuperiodcb, icuperiodcb,
NULL, NULL,
ICU_CHANNEL_1 ICU_CHANNEL_1,
0
}; };
/* /*

6
testhal/STM32L1xx/IRQ_STORM/main.c
View File

@ -147,7 +147,8 @@ static void gpt3cb(GPTDriver *gptp) {
*/ */
static const GPTConfig gpt2cfg = { static const GPTConfig gpt2cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt2cb /* Timer callback.*/ gpt2cb, /* Timer callback.*/
0
}; };
/* /*
@ -155,7 +156,8 @@ static const GPTConfig gpt2cfg = {
*/ */
static const GPTConfig gpt3cfg = { static const GPTConfig gpt3cfg = {
1000000, /* 1MHz timer clock.*/ 1000000, /* 1MHz timer clock.*/
gpt3cb /* Timer callback.*/ gpt3cb, /* Timer callback.*/
0
}; };

4
testhal/STM32L1xx/PWM-ICU/main.c
View File

@ -40,6 +40,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0
}; };
icucnt_t last_width, last_period; icucnt_t last_width, last_period;
@ -62,7 +63,8 @@ static ICUConfig icucfg = {
icuwidthcb, icuwidthcb,
icuperiodcb, icuperiodcb,
NULL, NULL,
ICU_CHANNEL_1 ICU_CHANNEL_1,
0
}; };
/* /*