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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16364 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
bfc374b607
commit
963dffe8c5
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@ -79,7 +79,7 @@
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*/
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#define CLK_SYSCLK 0U
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#define CLK_PLL1PCLK 1U
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#define CLK_PLL1QCLK 2U
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#define CLK_PLL2QCLK 2U
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#define CLK_PLL1RCLK 3U
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#define CLK_PLL2PCLK 4U
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#define CLK_PLL2QCLK 5U
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@ -2274,84 +2274,239 @@
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#endif /* !STM32_HSE_ENABLED */
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/**
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* @brief PLL input clock frequency.
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* @brief PLL1 input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
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#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
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#if (STM32_PLL1SRC == STM32_PLL1SRC_HSE) || defined(__DOXYGEN__)
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#define STM32_PLL1CLKIN (STM32_HSECLK / STM32_PLL1M_VALUE)
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
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#elif STM32_PLL1SRC == STM32_PLL1SRC_CSI
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#define STM32_PLL1CLKIN (STM32_CSICLK / STM32_PLL1M_VALUE)
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#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
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#define STM32_PLLCLKIN 0
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#elif STM32_PLL1SRC == STM32_PLL1SRC_HSI
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#define STM32_PLL1CLKIN (STM32_HSICLK / STM32_PLL1M_VALUE)
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#elif STM32_PLL1SRC == STM32_PLL1SRC_NOCLOCK
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#define STM32_PLL1CLKIN 0
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/*
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* PLL enable check.
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*/
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#if (STM32_SW == STM32_SW_PLLRCLK) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
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(STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
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(STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
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(STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
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(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
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(STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
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(STM32_OSPISEL == STM32_OSPISEL_PLLQCLK) || \
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defined(__DOXYGEN__)
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/**
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* @brief PLL activation flag.
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*/
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#define STM32_ACTIVATE_PLL TRUE
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#else
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#define STM32_ACTIVATE_PLL FALSE
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#error "invalid STM32_PLL1SRC value specified"
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#endif
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/**
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* @brief STM32_PLLPEN field.
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* @brief PLL2 input clock frequency.
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*/
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#if (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
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(STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
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defined(__DOXYGEN__)
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#define STM32_PLLPEN (1 << 16)
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#if (STM32_PLL2SRC == STM32_PLL2SRC_HSE) || defined(__DOXYGEN__)
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#define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PLL2M_VALUE)
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#elif STM32_PLL2SRC == STM32_PLL2SRC_CSI
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#define STM32_PLL2CLKIN (STM32_CSICLK / STM32_PLL2M_VALUE)
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#elif STM32_PLL2SRC == STM32_PLL2SRC_HSI
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#define STM32_PLL2CLKIN (STM32_HSICLK / STM32_PLL2M_VALUE)
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#elif STM32_PLL2SRC == STM32_PLL2SRC_NOCLOCK
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#define STM32_PLL2CLKIN 0
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#else
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#define STM32_PLLPEN (0 << 16)
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#error "invalid STM32_PLL2SRC value specified"
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#endif
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/**
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* @brief STM32_PLLQEN field.
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* @brief PLL3 input clock frequency.
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*/
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#if (STM32_OSPISEL == STM32_OSPISEL_PLLQCLK) || \
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(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
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(STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
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(STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
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defined(__DOXYGEN__)
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#define STM32_PLLQEN (1 << 20)
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#if (STM32_PLL3SRC == STM32_PLL3SRC_HSE) || defined(__DOXYGEN__)
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#define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PLL3M_VALUE)
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#elif STM32_PLL3SRC == STM32_PLL3SRC_CSI
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#define STM32_PLL3CLKIN (STM32_CSICLK / STM32_PLL3M_VALUE)
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#elif STM32_PLL3SRC == STM32_PLL3SRC_HSI
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#define STM32_PLL3CLKIN (STM32_HSICLK / STM32_PLL3M_VALUE)
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#elif STM32_PLL3SRC == STM32_PLL3SRC_NOCLOCK
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#define STM32_PLL3CLKIN 0
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#else
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#define STM32_PLLQEN (0 << 20)
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#error "invalid STM32_PLL3SRC value specified"
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#endif
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/**
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* @brief STM32_PLLREN field.
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* @brief STM32_PLL1PEN field.
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*/
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#if (STM32_SW == STM32_SW_PLLRCLK) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
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#if (STM32_SW == STM32_SW_PLL1P) || \
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(STM32_MCO1SEL == STM32_MCO1SEL_PLL1P) || \
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(STM32_MCO2SEL == STM32_MCO2SEL_PLL1P) || \
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defined(__DOXYGEN__)
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#define STM32_PLLREN (1 << 24)
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#define STM32_PLL1PEN (1U << 16)
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#else
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#define STM32_PLLREN (0 << 24)
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#define STM32_PLL1PEN (0U << 16)
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#endif
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/**
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* @brief STM32_PLL1QEN field.
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*/
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#if (STM32_SPI1SEL == STM32_SPI1SEL_PLL1Q) || \
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(STM32_SPI2SEL == STM32_SPI2SEL_PLL1Q) || \
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(STM32_SPI3SEL == STM32_SPI3SEL_PLL1Q) || \
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(STM32_OSPISEL == STM32_OSPISEL_PLL1Q) || \
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(STM32_USBSEL == STM32_USBSEL_PLL1Q) || \
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(STM32_SDMMC1SEL == STM32_SDMMC1SEL_PLL1Q) || \
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(STM32_SDMMC2SEL == STM32_SDMMC2SEL_PLL1Q) || \
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(STM32_RNGSEL == STM32_RNGSEL_PLL1Q) || \
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(STM32_CECSEL == STM32_CECSEL_PLL1Q) || \
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(STM32_FDCANSEL == STM32_FDCANSEL_PLL1Q) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLL1Q) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLL1Q) || \
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defined(__DOXYGEN__)
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#define STM32_PLL1QEN (1U << 17)
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#else
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#define STM32_PLL1QEN (0U << 17)
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#endif
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/**
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* @brief STM32_PLL1REN field.
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*/
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#if FALSE || \
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defined(__DOXYGEN__)
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#define STM32_PLL1REN (1U << 18)
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#else
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#define STM32_PLL1REN (0U << 18)
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#endif
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/**
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* @brief STM32_PLL2PEN field.
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*/
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#if (STM32_SW == STM32_SW_PLL2P) || \
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(STM32_MCO2SEL == STM32_MCO2SEL_PLL1P) || \
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(STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL2P) || \
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(STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL2P) || \
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(STM32_LPTIM3SEL == STM32_LPTIM3SEL_PLL2P) || \
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(STM32_LPTIM4SEL == STM32_LPTIM4SEL_PLL2P) || \
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(STM32_LPTIM5SEL == STM32_LPTIM5SEL_PLL2P) || \
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(STM32_LPTIM6SEL == STM32_LPTIM6SEL_PLL2P) || \
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(STM32_SPI1SEL == STM32_SPI1SEL_PLL2P) || \
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(STM32_SPI2SEL == STM32_SPI2SEL_PLL2P) || \
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(STM32_SPI3SEL == STM32_SPI3SEL_PLL2P) || \
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(STM32_SPI4SEL == STM32_SPI4SEL_PLL2P) || \
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(STM32_SPI5SEL == STM32_SPI5SEL_PLL2P) || \
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(STM32_SPI6SEL == STM32_SPI6SEL_PLL2P) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLL2P) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLL2P) || \
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defined(__DOXYGEN__)
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#define STM32_PLL2PEN (1U << 16)
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#else
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#define STM32_PLL2PEN (0U << 16)
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#endif
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/**
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* @brief STM32_PLL2QEN field.
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*/
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#if (STM32_USART1SEL == STM32_USART1SEL_PLL2Q) || \
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(STM32_USART2SEL == STM32_USART2SEL_PLL2Q) || \
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(STM32_USART3SEL == STM32_USART3SEL_PLL2Q) || \
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(STM32_UART4SEL == STM32_UART4SEL_PLL2Q) || \
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(STM32_UART5SEL == STM32_UART5SEL_PLL2Q) || \
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(STM32_USART6SEL == STM32_USART6SEL_PLL2Q) || \
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(STM32_UART7SEL == STM32_UART7SEL_PLL2Q) || \
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(STM32_UART8SEL == STM32_UART8SEL_PLL2Q) || \
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(STM32_UART9SEL == STM32_UART9SEL_PLL2Q) || \
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(STM32_USART10SEL == STM32_USART10SEL_PLL2Q) || \
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(STM32_USART11SEL == STM32_USART11SEL_PLL2Q) || \
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(STM32_UART12SEL == STM32_UART12SEL_PLL2Q) || \
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(STM32_LPUART1SEL == STM32_LPUART1SEL_PLL2Q) || \
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(STM32_FDCANSEL == STM32_FDCANSEL_PLL2Q) || \
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defined(__DOXYGEN__)
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#define STM32_PLL2QEN (1U << 17)
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#else
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#define STM32_PLL2QEN (0U << 17)
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#endif
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/**
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* @brief STM32_PLL2REN field.
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*/
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#if (STM32_OSPISEL == STM32_OSPISEL_PLL2R) || \
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(STM32_SDMMC1SEL == STM32_SDMMC1SEL_PLL2R) || \
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(STM32_SDMMC2SEL == STM32_SDMMC2SEL_PLL2R) || \
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(STM32_ADCDACSEL == STM32_ADCDACSEL_PLL2R) || \
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defined(__DOXYGEN__)
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#define STM32_PLL2REN (1U << 18)
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#else
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#define STM32_PLL2REN (0U << 18)
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#endif
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/**
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* @brief STM32_PLL3PEN field.
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*/
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#if (STM32_SPI1SEL == STM32_SPI1SEL_PLL3P) || \
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(STM32_SPI2SEL == STM32_SPI2SEL_PLL3P) || \
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(STM32_SPI3SEL == STM32_SPI3SEL_PLL3P) || \
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(STM32_SPI4SEL == STM32_SPI4SEL_PLL3P) || \
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(STM32_SPI5SEL == STM32_SPI5SEL_PLL3P) || \
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(STM32_SPI6SEL == STM32_SPI6SEL_PLL3P) || \
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(STM32_SAI1SEL == STM32_SAI1SEL_PLL3P) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLL3P) || \
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defined(__DOXYGEN__)
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#define STM32_PLL3PEN (1U << 16)
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#else
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#define STM32_PLL3PEN (0U << 16)
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#endif
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/**
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* @brief STM32_PLL3QEN field.
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*/
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#if (STM32_USART1SEL == STM32_USART1SEL_PLL3Q) || \
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(STM32_USART2SEL == STM32_USART2SEL_PLL3Q) || \
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(STM32_USART3SEL == STM32_USART3SEL_PLL3Q) || \
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(STM32_UART4SEL == STM32_UART4SEL_PLL3Q) || \
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(STM32_UART5SEL == STM32_UART5SEL_PLL3Q) || \
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(STM32_USART6SEL == STM32_USART6SEL_PLL3Q) || \
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(STM32_UART7SEL == STM32_UART7SEL_PLL3Q) || \
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(STM32_UART8SEL == STM32_UART8SEL_PLL3Q) || \
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(STM32_UART9SEL == STM32_UART9SEL_PLL3Q) || \
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(STM32_USART10SEL == STM32_USART10SEL_PLL3Q) || \
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(STM32_USART11SEL == STM32_USART11SEL_PLL3Q) || \
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(STM32_UART12SEL == STM32_UART12SEL_PLL3Q) || \
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(STM32_LPUART1SEL == STM32_LPUART1SEL_PLL3Q) || \
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(STM32_USBSEL == STM32_USBSEL_PLL3Q) || \
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defined(__DOXYGEN__)
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#define STM32_PLL3QEN (1U << 17)
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#else
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#define STM32_PLL3QEN (0U << 17)
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#endif
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/**
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* @brief STM32_PLL3REN field.
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*/
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#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL3P) || \
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(STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL3P) || \
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(STM32_LPTIM3SEL == STM32_LPTIM3SEL_PLL3P) || \
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(STM32_LPTIM4SEL == STM32_LPTIM4SEL_PLL3P) || \
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(STM32_LPTIM5SEL == STM32_LPTIM5SEL_PLL3P) || \
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(STM32_LPTIM6SEL == STM32_LPTIM6SEL_PLL3P) || \
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(STM32_I2C1SEL == STM32_I2C1SEL_PLL3R) || \
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(STM32_I2C2SEL == STM32_I2C2SEL_PLL3R) || \
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(STM32_I2C3SEL == STM32_I2C3SEL_PLL3R) || \
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(STM32_I2C4SEL == STM32_I2C4SEL_PLL3R) || \
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(STM32_I3C1SEL == STM32_I3C1SEL_PLL3R) || \
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defined(__DOXYGEN__)
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#define STM32_PLL3REN (1U << 18)
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#else
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#define STM32_PLL3REN (0U << 18)
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#endif
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/* Inclusion of PLL-related checks and calculations.*/
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#include <stm32_pll.inc>
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#include <stm32_pll1.inc>
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#include <stm32_pll2.inc>
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#include <stm32_pll3.inc>
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/**
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* @brief System clock source.
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