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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@263 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2008-04-13 17:03:56 +00:00
parent 9e2c8595c8
commit 97ec157b50
9 changed files with 285 additions and 7 deletions
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3
demos/ARMCM3-STM32F103-GCC/Makefile
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@ -75,7 +75,8 @@ SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \
ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s
# List all user directories here # List all user directories here
UINCDIR = ../../src/include ../../src/lib ../../ports/ARMCM3 UINCDIR = ../../src/include ../../src/lib ../../test \
../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103
# List the user directory to look for the libraries here # List the user directory to look for the libraries here
ULIBDIR = ULIBDIR =

6
demos/ARMCM3-STM32F103-GCC/board.c
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@ -21,6 +21,7 @@
#include <nvic.h> #include <nvic.h>
#include "board.h" #include "board.h"
#include "stm32_serial.h"
/* /*
* Hardware initialization goes here. * Hardware initialization goes here.
@ -88,4 +89,9 @@ void hwinit(void) {
ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
ST_CVR = 0; ST_CVR = 0;
ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS;
/*
* Other subsystems initialization.
*/
InitSerial(0xA0, 0xA0, 0xA0);
} }

9
demos/ARMCM3-STM32F103-GCC/main.c
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@ -18,8 +18,10 @@
*/ */
#include <ch.h> #include <ch.h>
#include <test.h>
#include "board.h" #include "board.h"
#include "stm32_serial.h"
/* /*
* Red LEDs blinker thread, times are in milliseconds. * Red LEDs blinker thread, times are in milliseconds.
@ -56,7 +58,10 @@ int main(int argc, char **argv) {
* Normal main() thread activity, in this demo it does nothing except * Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop. * sleeping in a loop.
*/ */
while (TRUE) while (TRUE) {
chThdSleep(1000); if (GPIOA->IDR & GPIOA_BUTTON)
TestThread(&COM2);
chThdSleep(500);
}
return 0; return 0;
} }

251
demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h Normal file
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@ -0,0 +1,251 @@
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */
#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */
#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */
#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */
#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */
#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */
#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */
#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \
(CHANNEL == PVD_IRQChannel) || \
(CHANNEL == TAMPER_IRQChannel) || \
(CHANNEL == RTC_IRQChannel) || \
(CHANNEL == FLASH_IRQChannel) || \
(CHANNEL == RCC_IRQChannel) || \
(CHANNEL == EXTI0_IRQChannel) || \
(CHANNEL == EXTI1_IRQChannel) || \
(CHANNEL == EXTI2_IRQChannel) || \
(CHANNEL == EXTI3_IRQChannel) || \
(CHANNEL == EXTI4_IRQChannel) || \
(CHANNEL == DMAChannel1_IRQChannel) || \
(CHANNEL == DMAChannel2_IRQChannel) || \
(CHANNEL == DMAChannel3_IRQChannel) || \
(CHANNEL == DMAChannel4_IRQChannel) || \
(CHANNEL == DMAChannel5_IRQChannel) || \
(CHANNEL == DMAChannel6_IRQChannel) || \
(CHANNEL == DMAChannel7_IRQChannel) || \
(CHANNEL == ADC_IRQChannel) || \
(CHANNEL == USB_HP_CAN_TX_IRQChannel) || \
(CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \
(CHANNEL == CAN_RX1_IRQChannel) || \
(CHANNEL == CAN_SCE_IRQChannel) || \
(CHANNEL == EXTI9_5_IRQChannel) || \
(CHANNEL == TIM1_BRK_IRQChannel) || \
(CHANNEL == TIM1_UP_IRQChannel) || \
(CHANNEL == TIM1_TRG_COM_IRQChannel) || \
(CHANNEL == TIM1_CC_IRQChannel) || \
(CHANNEL == TIM2_IRQChannel) || \
(CHANNEL == TIM3_IRQChannel) || \
(CHANNEL == TIM4_IRQChannel) || \
(CHANNEL == I2C1_EV_IRQChannel) || \
(CHANNEL == I2C1_ER_IRQChannel) || \
(CHANNEL == I2C2_EV_IRQChannel) || \
(CHANNEL == I2C2_ER_IRQChannel) || \
(CHANNEL == SPI1_IRQChannel) || \
(CHANNEL == SPI2_IRQChannel) || \
(CHANNEL == USART1_IRQChannel) || \
(CHANNEL == USART2_IRQChannel) || \
(CHANNEL == USART3_IRQChannel) || \
(CHANNEL == EXTI15_10_IRQChannel) || \
(CHANNEL == RTCAlarm_IRQChannel) || \
(CHANNEL == USBWakeUp_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_SVCall) || \
(HANDLER == SystemHandler_DebugMonitor) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_SVCall) || \
(HANDLER == SystemHandler_DebugMonitor) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \
(HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \
(VECTTAB == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \
(LP == NVIC_LP_SLEEPDEEP) || \
(LP == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \
(GROUP == NVIC_PriorityGroup_1) || \
(GROUP == NVIC_PriorityGroup_2) || \
(GROUP == NVIC_PriorityGroup_3) || \
(GROUP == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10)
#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/

11
ports/ARMCM3-STM32F103/stm32_serial.c
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@ -20,7 +20,9 @@
#include <ch.h> #include <ch.h>
#include "board.h" #include "board.h"
#include "nvic.h"
#include "stm32_serial.h" #include "stm32_serial.h"
#include "stm32lib/stm32f10x_nvic.h"
#ifdef USE_USART1 #ifdef USE_USART1
FullDuplexDriver COM1; FullDuplexDriver COM1;
@ -172,16 +174,25 @@ void InitSerial(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
#ifdef USE_USART1 #ifdef USE_USART1
chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1); chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
GPIOA->CRH = (GPIOA->CRH & 0xFFFFF00F) | 0x000004B0;
RCC->APB2ENR |= 0x00002000;
SetUSARTI(USART1, 38400, 0, CR2_STOP1_BITS | CR2_LINEN, 0); SetUSARTI(USART1, 38400, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
NVICEnableVector(USART1_IRQChannel, prio1);
#endif #endif
#ifdef USE_USART2 #ifdef USE_USART2
chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2); chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
GPIOA->CRL = (GPIOA->CRL & 0xFFFF00FF) | 0x00004B00;
RCC->APB1ENR |= 0x00020000;
SetUSARTI(USART2, 38400, 0, CR2_STOP1_BITS | CR2_LINEN, 0); SetUSARTI(USART2, 38400, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
NVICEnableVector(USART2_IRQChannel, prio2);
#endif #endif
#ifdef USE_USART3 #ifdef USE_USART3
chFDDInit(&COM3, ib3, sizeof ib3, NULL, ob3, sizeof ob3, OutNotify3); chFDDInit(&COM3, ib3, sizeof ib3, NULL, ob3, sizeof ob3, OutNotify3);
GPIOB->CRH = (GPIOB->CRH & 0xFFFF00FF) | 0x00004B00;
RCC->APB1ENR |= 0x00040000;
SetUSARTI(USART3, 38400, 0, CR2_STOP1_BITS | CR2_LINEN, 0); SetUSARTI(USART3, 38400, 0, CR2_STOP1_BITS | CR2_LINEN, 0);
NVICEnableVector(USART3_IRQChannel, prio3);
#endif #endif
} }

4
ports/ARMCM3-STM32F103/stm32_serial.h
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@ -20,9 +20,9 @@
#ifndef _STM32_SERIAL_H_ #ifndef _STM32_SERIAL_H_
#define _STM32_SERIAL_H_ #define _STM32_SERIAL_H_
#define USE_USART1 //#define USE_USART1
#define USE_USART2 #define USE_USART2
#define USE_USART3 //#define USE_USART3
/* /*
* Configuration parameter, you can change the depth of the queue buffers * Configuration parameter, you can change the depth of the queue buffers

1
ports/ARMCM3/chcore.c
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@ -56,6 +56,7 @@ void chSysSwitchI(Thread *otp, Thread *ntp) {
__attribute__((naked, weak)) __attribute__((naked, weak))
void chSysHalt(void) { void chSysHalt(void) {
chSysLock();
while (TRUE) { while (TRUE) {
} }
} }

5
ports/ARMCM3/nvic.c
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@ -20,5 +20,8 @@
#include <ch.h> #include <ch.h>
#include <nvic.h> #include <nvic.h>
void SetNVICVector(void) { void NVICEnableVector(uint32_t n, uint32_t prio) {
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << (n & 3))) | (prio << (n & 3));
NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
} }

2
ports/ARMCM3/nvic.h
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@ -131,7 +131,7 @@ typedef struct {
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
void SetNVICVector(void); void NVICEnableVector(uint32_t n, uint32_t prio);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif