Fixed bugs

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11894 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
edolomb 2018-04-11 16:47:15 +00:00
parent c5efa3af6f
commit 9877090f8b
4 changed files with 39 additions and 12 deletions

View File

@ -91,12 +91,8 @@
bool mtxConfigPeriphSecurity(Matrix *mtxp, uint32_t id, bool mode) {
uint32_t mask;
if (id < 74) {
mask = id & 0x1F;
}
else {
mask = (id & 0x1F) - 1;
}
mask = id & 0x1F;
mtxDisableWP(mtxp);
if (mode) {
mtxp->MATRIX_SPSELR[id / 32] |= (MATRIX_SPSELR_NSECP0 << mask);

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@ -77,7 +77,7 @@
*/
#define pmcEnablePidLow(mask) { \
pmcDisableWP(); \
PMC->PMC_PCER0 |= (mask); \
PMC->PMC_PCER0 = (mask); \
pmcEnableWP(); \
}
@ -91,7 +91,7 @@
*/
#define pmcDisablePidLow(mask) { \
pmcDisableWP(); \
PMC->PMC_PCDR0 |= (mask); \
PMC->PMC_PCDR0 = (mask); \
pmcEnableWP(); \
}
@ -105,7 +105,7 @@
*/
#define pmcEnablePidHigh(mask) { \
pmcDisableWP(); \
PMC->PMC_PCER1 |= (mask); \
PMC->PMC_PCER1 = (mask); \
pmcEnableWP(); \
}
@ -119,7 +119,7 @@
*/
#define pmcDisablePidHigh(mask) { \
pmcDisableWP(); \
PMC->PMC_PCDR1 |= (mask); \
PMC->PMC_PCDR1 = (mask); \
pmcEnableWP(); \
}
/** @} */

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@ -148,8 +148,32 @@ OSAL_IRQ_HANDLER(SAMA_SECUMOD_HANDLER) {
else if ((sr & SECUMOD_SR_VDDCOREH) && (nimpr & SECUMOD_NIMPR_VDDCOREH)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_VDDCOREH);
}
else if ((sr & SECUMOD_SR_DET0) && (nimpr & SECUMOD_NIMPR_DET0)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU0);
}
else if ((sr & SECUMOD_SR_DET1) && (nimpr & SECUMOD_NIMPR_DET1)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU1);
}
else if ((sr & SECUMOD_SR_DET2) && (nimpr & SECUMOD_NIMPR_DET2)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU2);
}
else if ((sr & SECUMOD_SR_DET3) && (nimpr & SECUMOD_NIMPR_DET3)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU3);
}
else if ((sr & SECUMOD_SR_DET4) && (nimpr & SECUMOD_NIMPR_DET4)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU4);
}
else if ((sr & SECUMOD_SR_DET5) && (nimpr & SECUMOD_NIMPR_DET5)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU5);
}
else if ((sr & SECUMOD_SR_DET6) && (nimpr & SECUMOD_NIMPR_DET6)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU6);
}
else if ((sr & SECUMOD_SR_DET7) && (nimpr & SECUMOD_NIMPR_DET7)) {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU7);
}
else {
SECD0.secumod_callback(&SECD0, SEC_EVENT_PIOBU);
(void) 0;
}
/* wait at least one slow clock */

View File

@ -226,7 +226,14 @@ typedef enum {
SEC_EVENT_VDDBUH = 8, /* Triggered on High VDDBU Voltage Monitor. */
SEC_EVENT_VDDCOREL = 9, /* Triggered on Low VDDCORE Voltage Monitor. */
SEC_EVENT_VDDCOREH = 10, /* Triggered on High VDDCORE Voltage Monitor. */
SEC_EVENT_PIOBU = 11 /* Triggered on PIOBU intrusion. */
SEC_EVENT_PIOBU0 = 11, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU1 = 12, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU2 = 13, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU3 = 14, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU4 = 15, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU5 = 16, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU6 = 17, /* Triggered on PIOBUx intrusion. */
SEC_EVENT_PIOBU7 = 18 /* Triggered on PIOBUx intrusion. */
} secevent_t;
/**