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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6420 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
pcirillo 2013-11-09 09:28:24 +00:00
parent 5756ea1498
commit 99b95e812c
4 changed files with 157 additions and 164 deletions
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31
os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
View File

@ -380,12 +380,8 @@ void icu_lld_init(void) {
A2_3 = 0U; A2_3 = 0U;
/* eMIOSx channels initially all not in use.*/ /* eMIOSx channels initially all not in use.*/
#if SPC5_HAS_EMIOS0
reset_emios0_active_channels(); reset_emios0_active_channels();
#endif
#if SPC5_HAS_EMIOS1
reset_emios1_active_channels(); reset_emios1_active_channels();
#endif
#if SPC5_ICU_USE_EMIOS0_CH0 #if SPC5_ICU_USE_EMIOS0_CH0
/* Driver initialization.*/ /* Driver initialization.*/
@ -493,14 +489,11 @@ void icu_lld_init(void) {
*/ */
void icu_lld_start(ICUDriver *icup) { void icu_lld_start(ICUDriver *icup) {
#if SPC5_HAS_EMIOS0 chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",
chDbgAssert(get_emios0_active_channels() < 25, "icu_lld_start(), #1",
"too many channels"); "too many channels");
#endif
#if SPC5_HAS_EMIOS1 chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_start(), #2",
chDbgAssert(get_emios1_active_channels() < 25, "icu_lld_start(), #2",
"too many channels"); "too many channels");
#endif
if (icup->state == ICU_STOP) { if (icup->state == ICU_STOP) {
/* Enables the peripheral.*/ /* Enables the peripheral.*/
@ -547,12 +540,12 @@ void icu_lld_start(ICUDriver *icup) {
/* Set eMIOS0 Clock.*/ /* Set eMIOS0 Clock.*/
#if SPC5_ICU_USE_EMIOS0 #if SPC5_ICU_USE_EMIOS0
active_emios0_clock(icup, NULL); icu_active_emios0_clock(icup);
#endif #endif
/* Set eMIOS1 Clock.*/ /* Set eMIOS1 Clock.*/
#if SPC5_ICU_USE_EMIOS1 #if SPC5_ICU_USE_EMIOS1
active_emios1_clock(icup, NULL); icu_active_emios1_clock(icup);
#endif #endif
} }
@ -570,7 +563,7 @@ void icu_lld_start(ICUDriver *icup) {
chDbgAssert((psc <= 0xFFFF) && chDbgAssert((psc <= 0xFFFF) &&
(((psc) * icup->config->frequency) == icup->clock) && (((psc) * icup->config->frequency) == icup->clock) &&
((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
"icu_lld_start(), #3", "invalid frequency"); "icu_lld_start(), #1", "invalid frequency");
icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0; icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;
icup->emiosp->CH[icup->ch_number].CCR.R |= icup->emiosp->CH[icup->ch_number].CCR.R |=
@ -605,14 +598,10 @@ void icu_lld_start(ICUDriver *icup) {
*/ */
void icu_lld_stop(ICUDriver *icup) { void icu_lld_stop(ICUDriver *icup) {
#if SPC5_HAS_EMIOS0 chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",
chDbgAssert(get_emios0_active_channels() < 25, "icu_lld_stop(), #1",
"too many channels"); "too many channels");
#endif chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",
#if SPC5_HAS_EMIOS1
chDbgAssert(get_emios1_active_channels() < 25, "icu_lld_stop(), #2",
"too many channels"); "too many channels");
#endif
if (icup->state == ICU_READY) { if (icup->state == ICU_READY) {
@ -700,12 +689,12 @@ void icu_lld_stop(ICUDriver *icup) {
/* eMIOS0 clock deactivation.*/ /* eMIOS0 clock deactivation.*/
#if SPC5_ICU_USE_EMIOS0 #if SPC5_ICU_USE_EMIOS0
deactive_emios0_clock(icup, NULL); icu_deactive_emios0_clock(icup);
#endif #endif
/* eMIOS1 clock deactivation.*/ /* eMIOS1 clock deactivation.*/
#if SPC5_ICU_USE_EMIOS1 #if SPC5_ICU_USE_EMIOS1
deactive_emios1_clock(icup, NULL); icu_deactive_emios1_clock(icup);
#endif #endif
} }
} }

51
os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c
View File

@ -696,12 +696,8 @@ CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F22F23_HANDLER) {
*/ */
void pwm_lld_init(void) { void pwm_lld_init(void) {
/* eMIOSx channels initially all not in use.*/ /* eMIOSx channels initially all not in use.*/
#if SPC5_HAS_EMIOS0
reset_emios0_active_channels(); reset_emios0_active_channels();
#endif
#if SPC5_HAS_EMIOS1
reset_emios1_active_channels(); reset_emios1_active_channels();
#endif
#if SPC5_PWM_USE_EMIOS0_GROUP0 #if SPC5_PWM_USE_EMIOS0_GROUP0
/* Driver initialization.*/ /* Driver initialization.*/
@ -776,14 +772,10 @@ void pwm_lld_start(PWMDriver *pwmp) {
uint32_t psc = 0, i = 0; uint32_t psc = 0, i = 0;
#if SPC5_HAS_EMIOS0 chDbgAssert(get_emios0_active_channels() < 28,
chDbgAssert(get_emios0_active_channels() < 25,
"pwm_lld_start(), #1", "too many channels"); "pwm_lld_start(), #1", "too many channels");
#endif chDbgAssert(get_emios1_active_channels() < 28,
#if SPC5_HAS_EMIOS1
chDbgAssert(get_emios1_active_channels() < 25,
"pwm_lld_start(), #2", "too many channels"); "pwm_lld_start(), #2", "too many channels");
#endif
if (pwmp->state == PWM_STOP) { if (pwmp->state == PWM_STOP) {
#if SPC5_PWM_USE_EMIOS0_GROUP0 #if SPC5_PWM_USE_EMIOS0_GROUP0
@ -818,12 +810,12 @@ void pwm_lld_start(PWMDriver *pwmp) {
/* Set eMIOS0 Clock.*/ /* Set eMIOS0 Clock.*/
#if SPC5_PWM_USE_EMIOS0 #if SPC5_PWM_USE_EMIOS0
active_emios0_clock(NULL, pwmp); pwm_active_emios0_clock(pwmp);
#endif #endif
/* Set eMIOS1 Clock.*/ /* Set eMIOS1 Clock.*/
#if SPC5_PWM_USE_EMIOS1 #if SPC5_PWM_USE_EMIOS1
active_emios1_clock(NULL, pwmp); pwm_active_emios1_clock(pwmp);
#endif #endif
} }
@ -890,37 +882,20 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif #endif
/* Set clock prescaler and control register.*/ /* Set clock prescaler and control register.*/
#if SPC5_HAS_EMIOS0 && SPC5_HAS_EMIOS1
if (pwmp->emiosp == &EMIOS_0) { if (pwmp->emiosp == &EMIOS_0) {
psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency); psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency);
chDbgAssert((psc <= 0xFFFF) && chDbgAssert((psc <= 0xFFFF) &&
(((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) && (((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) &&
((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
"pwm_lld_start(), #3", "invalid frequency"); "pwm_lld_start(), #1", "invalid frequency");
} else if (pwmp->emiosp == &EMIOS_1) { } else if (pwmp->emiosp == &EMIOS_1) {
psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency); psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency);
chDbgAssert((psc <= 0xFFFF) && chDbgAssert((psc <= 0xFFFF) &&
(((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) && (((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) &&
((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)), ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
"pwm_lld_start(), #4", "invalid frequency"); "pwm_lld_start(), #2", "invalid frequency");
} }
#elif SPC5_HAS_EMIOS0
if (pwmp->emiosp == &EMIOS_0) {
psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency);
chDbgAssert((psc <= 0xFFFF) &&
(((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) &&
((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
"pwm_lld_start(), #3", "invalid frequency");
}
#elif SPC5_HAS_EMIOS1
if (pwmp->emiosp == &EMIOS_1) {
psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency);
chDbgAssert((psc <= 0xFFFF) &&
(((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) &&
((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
"pwm_lld_start(), #3", "invalid frequency");
}
#endif
#if SPC5_PWM_USE_EMIOS0_GROUP0 #if SPC5_PWM_USE_EMIOS0_GROUP0
if (&PWMD1 == pwmp) { if (&PWMD1 == pwmp) {
@ -1335,14 +1310,10 @@ void pwm_lld_stop(PWMDriver *pwmp) {
uint32_t i = 0; uint32_t i = 0;
#if SPC5_HAS_EMIOS0 chDbgAssert(get_emios0_active_channels() < 28, "pwm_lld_stop(), #1",
chDbgAssert(get_emios0_active_channels() < 25, "pwm_lld_stop(), #1",
"too many channels"); "too many channels");
#endif chDbgAssert(get_emios1_active_channels() < 28, "pwm_lld_stop(), #2",
#if SPC5_HAS_EMIOS1
chDbgAssert(get_emios1_active_channels() < 25, "pwm_lld_stop(), #2",
"too many channels"); "too many channels");
#endif
if (pwmp->state == PWM_READY) { if (pwmp->state == PWM_READY) {
@ -1399,12 +1370,12 @@ void pwm_lld_stop(PWMDriver *pwmp) {
/* eMIOS0 clock deactivation.*/ /* eMIOS0 clock deactivation.*/
#if SPC5_PWM_USE_EMIOS0 #if SPC5_PWM_USE_EMIOS0
deactive_emios0_clock(NULL, pwmp); pwm_deactive_emios0_clock(pwmp);
#endif #endif
/* eMIOS1 clock deactivation.*/ /* eMIOS1 clock deactivation.*/
#if SPC5_PWM_USE_EMIOS1 #if SPC5_PWM_USE_EMIOS1
deactive_emios1_clock(NULL, pwmp); pwm_deactive_emios1_clock(pwmp);
#endif #endif
} }
} }

209
os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
View File

@ -44,26 +44,29 @@
/** /**
* @brief Number of active eMIOSx Channels. * @brief Number of active eMIOSx Channels.
*/ */
#if SPC5_HAS_EMIOS0
static uint32_t emios0_active_channels; static uint32_t emios0_active_channels;
#endif
#if SPC5_HAS_EMIOS1
static uint32_t emios1_active_channels; static uint32_t emios1_active_channels;
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
#if SPC5_HAS_EMIOS0
void reset_emios0_active_channels() { void reset_emios0_active_channels() {
emios0_active_channels = 0; emios0_active_channels = 0;
} }
void reset_emios1_active_channels() {
emios1_active_channels = 0;
}
uint32_t get_emios0_active_channels() { uint32_t get_emios0_active_channels() {
return emios0_active_channels; return emios0_active_channels;
} }
uint32_t get_emios1_active_channels() {
return emios1_active_channels;
}
void increase_emios0_active_channels() { void increase_emios0_active_channels() {
emios0_active_channels++; emios0_active_channels++;
} }
@ -72,64 +75,6 @@ void decrease_emios0_active_channels() {
emios0_active_channels--; emios0_active_channels--;
} }
void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
/* If this is the first Channel activated then the eMIOS0 is enabled.*/
if (emios0_active_channels == 1) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_START_PCTL);
/* Disable all unified channels.*/
if (icup != NULL) {
icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U;
icup->emiosp->UCDIS.R = 0xFFFFFFFF;
} else if (pwmp != NULL) {
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;
pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
}
}
}
void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
/* If it is the last active channels then the eMIOS0 is disabled.*/
if (emios0_active_channels == 0) {
if (icup != NULL) {
if (icup->emiosp->UCDIS.R == 0) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_STOP_PCTL);
}
} else if (pwmp != NULL) {
if (pwmp->emiosp->UCDIS.R == 0) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_STOP_PCTL);
}
}
}
}
#endif
#if SPC5_HAS_EMIOS1
void reset_emios1_active_channels() {
emios1_active_channels = 0;
}
uint32_t get_emios1_active_channels() {
return emios1_active_channels;
}
void increase_emios1_active_channels() { void increase_emios1_active_channels() {
emios1_active_channels++; emios1_active_channels++;
} }
@ -138,49 +83,129 @@ void decrease_emios1_active_channels() {
emios1_active_channels--; emios1_active_channels--;
} }
void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) { #if HAL_USE_ICU
void icu_active_emios0_clock(ICUDriver *icup) {
/* If this is the first Channel activated then the eMIOS0 is enabled.*/
if (emios0_active_channels == 1) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_START_PCTL);
/* Disable all unified channels.*/
icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U;
icup->emiosp->UCDIS.R = 0xFFFFFFFF;
}
}
#endif
#if HAL_USE_PWM
void pwm_active_emios0_clock(PWMDriver *pwmp) {
/* If this is the first Channel activated then the eMIOS0 is enabled.*/
if (emios0_active_channels == 1) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_START_PCTL);
/* Disable all unified channels.*/
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;
pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
}
}
#endif
#if HAL_USE_ICU
void icu_active_emios1_clock(ICUDriver *icup) {
/* If this is the first Channel activated then the eMIOS1 is enabled.*/ /* If this is the first Channel activated then the eMIOS1 is enabled.*/
if (emios1_active_channels == 1) { if (emios1_active_channels == 1) {
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL, halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
SPC5_EMIOS1_START_PCTL); SPC5_EMIOS1_START_PCTL);
/* Disable all unified channels.*/ /* Disable all unified channels.*/
if (icup != NULL) { icup->emiosp->MCR.B.GPREN = 0;
icup->emiosp->MCR.B.GPREN = 0; icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE); icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
icup->emiosp->MCR.B.GTBE = 1U; icup->emiosp->MCR.B.GTBE = 1U;
icup->emiosp->UCDIS.R = 0xFFFFFFFF; icup->emiosp->UCDIS.R = 0xFFFFFFFF;
} else if (pwmp != NULL) {
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;
pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
}
} }
} }
#endif
void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) { #if HAL_USE_PWM
void pwm_active_emios1_clock(PWMDriver *pwmp) {
/* If this is the first Channel activated then the eMIOS1 is enabled.*/
if (emios1_active_channels == 1) {
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
SPC5_EMIOS1_START_PCTL);
/* Disable all unified channels.*/
pwmp->emiosp->MCR.B.GPREN = 0;
pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);
pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
pwmp->emiosp->MCR.B.GTBE = 1U;
pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
}
}
#endif
#if HAL_USE_ICU
void icu_deactive_emios0_clock(ICUDriver *icup) {
/* If it is the last active channels then the eMIOS0 is disabled.*/
if (emios0_active_channels == 0) {
if (icup->emiosp->UCDIS.R == 0) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_STOP_PCTL);
}
}
}
#endif
#if HAL_USE_PWM
void pwm_deactive_emios0_clock(PWMDriver *pwmp) {
/* If it is the last active channels then the eMIOS0 is disabled.*/
if (emios0_active_channels == 0) {
if (pwmp->emiosp->UCDIS.R == 0) {
halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
SPC5_EMIOS0_STOP_PCTL);
}
}
}
#endif
#if HAL_USE_ICU
void icu_deactive_emios1_clock(ICUDriver *icup) {
/* If it is the last active channels then the eMIOS1 is disabled.*/ /* If it is the last active channels then the eMIOS1 is disabled.*/
if (emios1_active_channels == 0) { if (emios1_active_channels == 0) {
if (icup != NULL) { if (icup->emiosp->UCDIS.R == 0) {
if (icup->emiosp->UCDIS.R == 0) { halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL, SPC5_EMIOS1_STOP_PCTL);
SPC5_EMIOS1_STOP_PCTL); }
} }
} else if (pwmp != NULL) { }
if (pwmp->emiosp->UCDIS.R == 0) { #endif
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
SPC5_EMIOS1_STOP_PCTL); #if HAL_USE_PWM
} void pwm_deactive_emios1_clock(PWMDriver *pwmp) {
/* If it is the last active channels then the eMIOS1 is disabled.*/
if (emios1_active_channels == 0) {
if (pwmp->emiosp->UCDIS.R == 0) {
halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
SPC5_EMIOS1_STOP_PCTL);
} }
} }
} }

30
os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h
View File

@ -25,7 +25,7 @@
#ifndef _SPC5_EMIOS_H_ #ifndef _SPC5_EMIOS_H_
#define _SPC5_EMIOS_H_ #define _SPC5_EMIOS_H_
#if HAL_USE_ICU || defined(__DOXYGEN__) #if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
/*===========================================================================*/ /*===========================================================================*/
/* Driver constants. */ /* Driver constants. */
@ -149,24 +149,32 @@
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
#if SPC5_HAS_EMIOS0
void reset_emios0_active_channels(void); void reset_emios0_active_channels(void);
void reset_emios1_active_channels(void);
uint32_t get_emios0_active_channels(void); uint32_t get_emios0_active_channels(void);
uint32_t get_emios1_active_channels(void);
void increase_emios0_active_channels(void); void increase_emios0_active_channels(void);
void decrease_emios0_active_channels(void); void decrease_emios0_active_channels(void);
void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
#endif
#if SPC5_HAS_EMIOS1
void reset_emios1_active_channels(void);
uint32_t get_emios1_active_channels(void);
void increase_emios1_active_channels(void); void increase_emios1_active_channels(void);
void decrease_emios1_active_channels(void); void decrease_emios1_active_channels(void);
void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp); #if HAL_USE_ICU
void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp); void icu_active_emios0_clock(ICUDriver *icup);
void icu_active_emios1_clock(ICUDriver *icup);
#endif
#if HAL_USE_PWM
void pwm_active_emios0_clock(PWMDriver *pwmp);
void pwm_active_emios1_clock(PWMDriver *pwmp);
#endif
#if HAL_USE_ICU
void icu_deactive_emios0_clock(ICUDriver *icup);
void icu_deactive_emios1_clock(ICUDriver *icup);
#endif
#if HAL_USE_PWM
void pwm_deactive_emios0_clock(PWMDriver *pwmp);
void pwm_deactive_emios1_clock(PWMDriver *pwmp);
#endif #endif
#endif /* HAL_USE_ICU */ #endif /* HAL_USE_ICU || HAL_USE_PWM */
#endif /* _SPC5_EMIOS_H_ */ #endif /* _SPC5_EMIOS_H_ */