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ChibiOS
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Mass update. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14399 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-20 07:51:50 +00:00
parent edecbf5144
commit 9a01c5a1e2
13 changed files with 52 additions and 26 deletions
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6
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
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@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
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@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
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@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -43,9 +43,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE

6
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
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@ -54,9 +54,11 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}