diff --git a/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h index 4484c1f0c..4a7a92e76 100644 --- a/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h @@ -168,6 +168,19 @@ #define STM32_I2C_I2C2_DMA_PRIORITY 1 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | STM32_I2S_MODE_RX) +#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | STM32_I2S_MODE_RX) +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + /* * ICU driver system settings. */ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index ecaa8cf09..e75cf5288 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -208,12 +208,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -491,12 +495,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE @@ -980,12 +988,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI1 FALSE #define STM32_HAS_SPI4 FALSE @@ -1209,12 +1221,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI1 FALSE #define STM32_HAS_SPI4 FALSE @@ -1460,12 +1476,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -1725,12 +1745,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE @@ -1969,12 +1993,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI1 FALSE #define STM32_HAS_SPI4 FALSE @@ -2452,12 +2480,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -2965,12 +2997,16 @@ #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE diff --git a/readme.txt b/readme.txt index 806f9eb3e..aa4bc0e9d 100644 --- a/readme.txt +++ b/readme.txt @@ -74,4 +74,6 @@ ***************************************************************************** *** Next *** +- FIX: Fixed I2S-related definitions missing in STM32F3xx registry (bug #1162) + (backported to 21.6.1)(backported to 20.3.4). - FIX: Fixed AVR port broken (bug #1161)(backported to 21.6.1).