git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3474 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
4f783ee161
commit
9e51498e11
|
@ -289,10 +289,10 @@
|
|||
PIN_MODE_INPUT(9) | \
|
||||
PIN_MODE_INPUT(10) | \
|
||||
PIN_MODE_INPUT(11) | \
|
||||
PIN_MODE_INPUT(GPIOD_LED4) | \
|
||||
PIN_MODE_INPUT(GPIOD_LED3) | \
|
||||
PIN_MODE_INPUT(GPIOD_LED5) | \
|
||||
PIN_MODE_INPUT(GPIOD_LED6))
|
||||
PIN_MODE_OUTPUT(GPIOD_LED4) | \
|
||||
PIN_MODE_OUTPUT(GPIOD_LED3) | \
|
||||
PIN_MODE_OUTPUT(GPIOD_LED5) | \
|
||||
PIN_MODE_OUTPUT(GPIOD_LED6))
|
||||
#define VAL_GPIOD_OTYPER 0x00000000
|
||||
#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF
|
||||
#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \
|
||||
|
@ -311,7 +311,7 @@
|
|||
PIN_PUDR_FLOATING(GPIOD_LED3) | \
|
||||
PIN_PUDR_FLOATING(GPIOD_LED5) | \
|
||||
PIN_PUDR_FLOATING(GPIOD_LED6))
|
||||
#define VAL_GPIOD_ODR 0x0FFFFFCF
|
||||
#define VAL_GPIOD_ODR 0x00000FCF
|
||||
#define VAL_GPIOD_AFRL 0x00000000
|
||||
#define VAL_GPIOD_AFRH 0x00000000
|
||||
|
||||
|
|
|
@ -159,6 +159,7 @@ static void spicb(SPIDriver *spip) {
|
|||
* a seconds counter.
|
||||
*/
|
||||
static WORKING_AREA(waThread1, 128);
|
||||
#if 0
|
||||
static msg_t Thread1(void *arg) {
|
||||
static uint32_t seconds_counter;
|
||||
|
||||
|
@ -169,6 +170,19 @@ static msg_t Thread1(void *arg) {
|
|||
seconds_counter++;
|
||||
}
|
||||
}
|
||||
#else
|
||||
static msg_t Thread1(void *arg) {
|
||||
|
||||
(void)arg;
|
||||
chRegSetThreadName("blinker");
|
||||
while (TRUE) {
|
||||
palSetPad(GPIOD, GPIOD_LED5);
|
||||
chThdSleepMilliseconds(500);
|
||||
palClearPad(GPIOD, GPIOD_LED5);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
|
|
|
@ -99,7 +99,7 @@ void _pal_lld_init(const PALConfig *config) {
|
|||
*/
|
||||
#if defined(STM32L1XX_MD)
|
||||
rccEnableAHB(AHB_EN_MASK, TRUE);
|
||||
#elif defined(STM32F2XX)
|
||||
#elif defined(STM32F2XX) || defined(STM32F4XX)
|
||||
RCC->AHB1ENR |= AHB1_EN_MASK;
|
||||
RCC->AHB1LPENR |= AHB1_LPEN_MASK;
|
||||
#endif
|
||||
|
|
|
@ -84,10 +84,6 @@ void hal_lld_init(void) {
|
|||
*
|
||||
* @special
|
||||
*/
|
||||
#if defined(STM32F2XX) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Clocks and internal voltage initialization.
|
||||
*/
|
||||
void stm32_clock_init(void) {
|
||||
|
||||
#if !STM32_NO_INIT
|
||||
|
@ -135,7 +131,7 @@ void stm32_clock_init(void) {
|
|||
|
||||
#if STM32_ACTIVATE_PLLI2S
|
||||
/* PLLI2S activation.*/
|
||||
RCC->PLLI2SCFGR = STM32_PLI2SR_VALUE | STM32_PLLI2SN_VALUE;
|
||||
RCC->PLLI2SCFGR = STM32_PLLI2SR_VALUE | STM32_PLLI2SN_VALUE;
|
||||
RCC->CR |= RCC_CR_PLLI2SON;
|
||||
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
|
||||
; /* Waits until PLLI2S is stable. */
|
||||
|
@ -145,19 +141,16 @@ void stm32_clock_init(void) {
|
|||
RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
|
||||
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
|
||||
/* Flash setup. */
|
||||
/* Flash setup.*/
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS;
|
||||
|
||||
/* Switching to the configured clock source if it is different from MSI. */
|
||||
/* Switching to the configured clock source if it is different from MSI.*/
|
||||
#if (STM32_SW != STM32_SW_HSI)
|
||||
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
|
||||
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
#endif
|
||||
#endif /* STM32_NO_INIT */
|
||||
}
|
||||
#else
|
||||
void stm32_clock_init(void) {}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
|
Loading…
Reference in New Issue