git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13432 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-03-17 08:37:39 +00:00
commit 9ebf531661
150 changed files with 1249 additions and 24748 deletions

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>NIL-STM32G071RB-NUCLEO64</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>mingw32-make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>false</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
<link>
<name>test</name>
<type>2</type>
<locationURI>CHIBIOS/test</locationURI>
</link>
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@ -1,189 +0,0 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data.
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO).
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# FPU-related options.
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, target, sources and paths
#
# Define project name here
PROJECT = ch
# Target settings.
MCU = cortex-m0
# Imported source files and paths.
CHIBIOS := ../../..
CONFDIR := ./cfg
BUILDDIR := ./build
DEPDIR := ./.dep
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g0xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32G0xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G071RB/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/nil/nil.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
include $(CHIBIOS)/test/lib/test.mk
include $(CHIBIOS)/test/nil/nil_test.mk
include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32G071xB.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(ALLCPPSRC)
# List ASM source files here.
ASMSRC = $(ALLASMSRC)
# List ASM with preprocessor source files here.
ASMXSRC = $(ALLXASMSRC)
# Inclusion directories.
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
# Define C warning options here.
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here.
CPPWARN = -Wall -Wextra -Wundef
#
# Project, target, sources and paths
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user section
##############################################################################
##############################################################################
# Common rules
#
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/arm-none-eabi.mk
include $(RULESPATH)/rules.mk
#
# Common rules
##############################################################################
##############################################################################
# Custom rules
#
#
# Custom rules
##############################################################################

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@ -1,479 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file nil/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup NIL_CONFIG
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_NIL_CONF_
#define _CHIBIOS_NIL_CONF_VER_4_0_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Maximum number of user threads in the application.
* @note This number is not inclusive of the idle thread which is
* implicitly handled.
* @note Set this value to be exactly equal to the number of threads you
* will use or you would be wasting RAM and cycles.
* @note This values also defines the number of available priorities
* (0..CH_CFG_MAX_THREADS-1).
*/
#if !defined(CH_CFG_MAX_THREADS)
#define CH_CFG_MAX_THREADS 8
#endif
/**
* @brief Auto starts threads when @p chSysInit() is invoked.
*/
#if !defined(CH_CFG_AUTOSTART_THREADS)
#define CH_CFG_AUTOSTART_THREADS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name System timer settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @note This value together with the @p CH_CFG_ST_RESOLUTION
* option defines the maximum amount of time allowed for
* timeouts.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 1000
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note Feature not currently implemented.
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES FALSE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES TRUE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES TRUE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY TRUE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note Feature not currently implemented.
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief System assertions.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Stack check.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System initialization hook.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
*/
#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
/* Add custom threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) {}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/**
* @brief System halt hook.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in nilcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

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@ -1,531 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS TRUE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

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@ -1,236 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32G0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32G0xx_MCUCONF
#define STM32G071_MCUCONF
#define STM32G081_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
#define STM32_HSIDIV_VALUE 1
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 2
#define STM32_PLLN_VALUE 16
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 4
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clocks and sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_CECSEL STM32_CECSEL_HSI16DIV
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK
#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
#define STM32_TIM15SEL STM32_TIM15SEL_TIMPCLK
#define STM32_RNGSEL STM32_RNGSEL_HSI16
#define STM32_RNGDIV_VALUE 1
#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
/*
* Shared IRQ settings.
*/
#define STM32_IRQ_EXTI0_1_PRIORITY 3
#define STM32_IRQ_EXTI2_3_PRIORITY 3
#define STM32_IRQ_EXTI4_15_PRIORITY 3
#define STM32_IRQ_EXTI1921_PRIORITY 3
#define STM32_IRQ_USART1_PRIORITY 2
#define STM32_IRQ_USART2_PRIORITY 2
#define STM32_IRQ_USART3_4_LP1_PRIORITY 2
#define STM32_IRQ_TIM1_UP_PRIORITY 1
#define STM32_IRQ_TIM1_CC_PRIORITY 1
#define STM32_IRQ_TIM2_PRIORITY 1
#define STM32_IRQ_TIM3_PRIORITY 1
#define STM32_IRQ_TIM6_PRIORITY 1
#define STM32_IRQ_TIM7_PRIORITY 1
#define STM32_IRQ_TIM14_PRIORITY 1
#define STM32_IRQ_TIM15_PRIORITY 1
#define STM32_IRQ_TIM16_PRIORITY 1
#define STM32_IRQ_TIM17_PRIORITY 1
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 3
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 3
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
#define STM32_I2C_I2C2_IRQ_PRIORITY 3
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 2
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
* NOTE: STM32G081 only.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

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@ -1,53 +0,0 @@
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@ -1,96 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#include "ch.h"
#include "nil_test_root.h"
#include "oslib_test_root.h"
/*
* Blinker thread #1.
*/
static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
while (true) {
while (true) {
palClearLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500);
palSetLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500);
}
}
}
/*
* Tester thread.
*/
THD_WORKING_AREA(waThread3, 256);
THD_FUNCTION(Thread3, arg) {
(void)arg;
/*
* Activates the serial driver 1 using the driver default configuration.
* PA9 and PA10 are routed to USART1.
*/
sdStart(&SD2, NULL);
/* Welcome message.*/
chnWrite(&SD2, (const uint8_t *)"Hello World!\r\n", 14);
/* Waiting for button push and activation of the test suite.*/
while (true) {
if (palReadLine(LINE_BUTTON) == PAL_LOW) {
test_execute((BaseSequentialStream *)&SD2, &nil_test_suite);
test_execute((BaseSequentialStream *)&SD2, &oslib_test_suite);
}
chThdSleepMilliseconds(500);
}
}
/*
* Threads creation table, one entry per thread.
*/
THD_TABLE_BEGIN
THD_TABLE_THREAD(0, "blinker1", waThread1, Thread1, NULL)
THD_TABLE_THREAD(4, "tester", waThread3, Thread3, NULL)
THD_TABLE_END
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/* This is now the idle thread loop, you may perform here a low priority
task but you must never try to sleep or wait in this loop. Note that
this tasks runs at the lowest priority level so any instruction added
here will be executed after all other tasks have been started.*/
while (true) {
}
}

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@ -1,55 +0,0 @@
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</cproject>

View File

@ -1,95 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>NIL-STM32G474RE-NUCLEO64</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>mingw32-make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>false</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
<link>
<name>test</name>
<type>2</type>
<locationURI>CHIBIOS/test</locationURI>
</link>
</linkedResources>
</projectDescription>

View File

@ -1,189 +0,0 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data.
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO).
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# FPU-related options.
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, target, sources and paths
#
# Define project name here
PROJECT = ch
# Target settings.
MCU = cortex-m4
# Imported source files and paths.
CHIBIOS := ../../..
CONFDIR := ./cfg
BUILDDIR := ./build
DEPDIR := ./.dep
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g4xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/nil/nil.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
include $(CHIBIOS)/test/lib/test.mk
include $(CHIBIOS)/test/nil/nil_test.mk
include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32G474xE.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(ALLCPPSRC)
# List ASM source files here.
ASMSRC = $(ALLASMSRC)
# List ASM with preprocessor source files here.
ASMXSRC = $(ALLXASMSRC)
# Inclusion directories.
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
# Define C warning options here.
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here.
CPPWARN = -Wall -Wextra -Wundef
#
# Project, target, sources and paths
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user section
##############################################################################
##############################################################################
# Common rules
#
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/arm-none-eabi.mk
include $(RULESPATH)/rules.mk
#
# Common rules
##############################################################################
##############################################################################
# Custom rules
#
#
# Custom rules
##############################################################################

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@ -1,479 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file nil/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup NIL_CONFIG
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_NIL_CONF_
#define _CHIBIOS_NIL_CONF_VER_4_0_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Maximum number of user threads in the application.
* @note This number is not inclusive of the idle thread which is
* implicitly handled.
* @note Set this value to be exactly equal to the number of threads you
* will use or you would be wasting RAM and cycles.
* @note This values also defines the number of available priorities
* (0..CH_CFG_MAX_THREADS-1).
*/
#if !defined(CH_CFG_MAX_THREADS)
#define CH_CFG_MAX_THREADS 8
#endif
/**
* @brief Auto starts threads when @p chSysInit() is invoked.
*/
#if !defined(CH_CFG_AUTOSTART_THREADS)
#define CH_CFG_AUTOSTART_THREADS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name System timer settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @note This value together with the @p CH_CFG_ST_RESOLUTION
* option defines the maximum amount of time allowed for
* timeouts.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 5000
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note Feature not currently implemented.
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES FALSE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES TRUE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES TRUE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY TRUE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note Feature not currently implemented.
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief System assertions.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Stack check.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System initialization hook.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
*/
#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
/* Add custom threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) {}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/**
* @brief System halt hook.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in nilcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

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@ -1,531 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS TRUE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

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@ -1,372 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32G4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32G4xx_MCUCONF
#define STM32G473_MCUCONF
#define STM32G483_MCUCONF
#define STM32G474_MCUCONF
#define STM32G484_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSE_ENABLED TRUE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 6
#define STM32_PLLN_VALUE 85
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 8
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
#define STM32_FDCANSEL STM32_FDCANSEL_HSE
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI164041_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI212229_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_FDCAN2_PRIORITY 10
#define STM32_IRQ_FDCAN3_PRIORITY 10
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_UP_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_TIM20_UP_PRIORITY 7
#define STM32_IRQ_TIM20_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_USE_ADC4 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_FDCAN3 FALSE
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_USE_DAC2_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH2 FALSE
#define STM32_DAC_USE_DAC4_CH1 FALSE
#define STM32_DAC_USE_DAC4_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC4_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC4_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
#define STM32_PWM_USE_TIM20 FALSE
/*
* RTC driver system settings.
*/
/*
* SDC driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_LPUART1 TRUE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#endif /* MCUCONF_H */

View File

@ -1,53 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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</launchConfiguration>

View File

@ -1,96 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#include "ch.h"
#include "nil_test_root.h"
#include "oslib_test_root.h"
/*
* Blinker thread #1.
*/
static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
while (true) {
while (true) {
palClearLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500);
palSetLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500);
}
}
}
/*
* Tester thread.
*/
THD_WORKING_AREA(waThread3, 256);
THD_FUNCTION(Thread3, arg) {
(void)arg;
/*
* Activates the serial driver 1 using the driver default configuration.
* PA9 and PA10 are routed to USART1.
*/
sdStart(&LPSD1, NULL);
/* Welcome message.*/
chnWrite(&LPSD1, (const uint8_t *)"Hello World!\r\n", 14);
/* Waiting for button push and activation of the test suite.*/
while (true) {
if (palReadLine(LINE_BUTTON)) {
test_execute((BaseSequentialStream *)&LPSD1, &nil_test_suite);
test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
}
chThdSleepMilliseconds(500);
}
}
/*
* Threads creation table, one entry per thread.
*/
THD_TABLE_BEGIN
THD_TABLE_THREAD(0, "blinker1", waThread1, Thread1, NULL)
THD_TABLE_THREAD(4, "tester", waThread3, Thread3, NULL)
THD_TABLE_END
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/* This is now the idle thread loop, you may perform here a low priority
task but you must never try to sleep or wait in this loop. Note that
this tasks runs at the lowest priority level so any instruction added
here will be executed after all other tasks have been started.*/
while (true) {
}
}

View File

@ -1,55 +0,0 @@
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View File

@ -1,95 +0,0 @@
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<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
<link>
<name>test</name>
<type>2</type>
<locationURI>CHIBIOS/test</locationURI>
</link>
</linkedResources>
</projectDescription>

View File

@ -1,189 +0,0 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data.
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO).
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# FPU-related options.
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, target, sources and paths
#
# Define project name here
PROJECT = ch
# Target settings.
MCU = cortex-m7
# Imported source files and paths.
CHIBIOS := ../../..
CONFDIR := ./cfg
BUILDDIR := ./build
DEPDIR := ./.dep
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H755ZI/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/nil/nil.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
include $(CHIBIOS)/test/lib/test.mk
include $(CHIBIOS)/test/nil/nil_test.mk
include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32H755xI_M7.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(ALLCPPSRC)
# List ASM source files here.
ASMSRC = $(ALLASMSRC)
# List ASM with preprocessor source files here.
ASMXSRC = $(ALLXASMSRC)
# Inclusion directories.
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
# Define C warning options here.
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here.
CPPWARN = -Wall -Wextra -Wundef
#
# Project, target, sources and paths
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS = -DCORE_CM7
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user section
##############################################################################
##############################################################################
# Common rules
#
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/arm-none-eabi.mk
include $(RULESPATH)/rules.mk
#
# Common rules
##############################################################################
##############################################################################
# Custom rules
#
#
# Custom rules
##############################################################################

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@ -1,479 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file nil/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup NIL_CONFIG
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_NIL_CONF_
#define _CHIBIOS_NIL_CONF_VER_4_0_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Maximum number of user threads in the application.
* @note This number is not inclusive of the idle thread which is
* implicitly handled.
* @note Set this value to be exactly equal to the number of threads you
* will use or you would be wasting RAM and cycles.
* @note This values also defines the number of available priorities
* (0..CH_CFG_MAX_THREADS-1).
*/
#if !defined(CH_CFG_MAX_THREADS)
#define CH_CFG_MAX_THREADS 8
#endif
/**
* @brief Auto starts threads when @p chSysInit() is invoked.
*/
#if !defined(CH_CFG_AUTOSTART_THREADS)
#define CH_CFG_AUTOSTART_THREADS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name System timer settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @note This value together with the @p CH_CFG_ST_RESOLUTION
* option defines the maximum amount of time allowed for
* timeouts.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 5000
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note Feature not currently implemented.
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES FALSE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES TRUE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES TRUE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY TRUE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note Feature not currently implemented.
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief System assertions.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Stack check.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System initialization hook.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
*/
#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
/* Add custom threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) {}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/**
* @brief System halt hook.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in nilcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

View File

@ -1,531 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC TRUE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI TRUE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS FALSE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

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@ -1,484 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32H7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32H7xx_MCUCONF
#define STM32H742_MCUCONF
#define STM32H743_MCUCONF
#define STM32H753_MCUCONF
#define STM32H745_MCUCONF
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
/*
* General settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_TARGET_CORE 1
/*
* Memory attributes settings.
*/
#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
#define STM32_NOCACHE_SRAM3 TRUE
/*
* PWR system settings.
* Reading STM32 Reference Manual is required, settings in PWR_CR3 are
* very critical.
* Register constants are taken from the ST header.
*/
#define STM32_VOS STM32_VOS_SCALE1
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN)
#define STM32_PWR_CR3 (PWR_CR3_SMPSEN | PWR_CR3_USB33DEN)
#define STM32_PWR_CPUCR 0
/*
* Clock tree static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_CSI_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
/*
* PLLs static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
#define STM32_PLLCFGR_MASK ~0
#define STM32_PLL1_ENABLED TRUE
#define STM32_PLL1_P_ENABLED TRUE
#define STM32_PLL1_Q_ENABLED TRUE
#define STM32_PLL1_R_ENABLED TRUE
#define STM32_PLL1_DIVM_VALUE 4
#define STM32_PLL1_DIVN_VALUE 480
#define STM32_PLL1_FRACN_VALUE 0
#define STM32_PLL1_DIVP_VALUE 2
#define STM32_PLL1_DIVQ_VALUE 20
#define STM32_PLL1_DIVR_VALUE 8
#define STM32_PLL2_ENABLED TRUE
#define STM32_PLL2_P_ENABLED TRUE
#define STM32_PLL2_Q_ENABLED TRUE
#define STM32_PLL2_R_ENABLED TRUE
#define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
#define STM32_PLL3_P_ENABLED TRUE
#define STM32_PLL3_Q_ENABLED TRUE
#define STM32_PLL3_R_ENABLED TRUE
#define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLL3_DIVN_VALUE 400
#define STM32_PLL3_FRACN_VALUE 0
#define STM32_PLL3_DIVP_VALUE 8
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
/*
* Core clocks dynamic settings (can be changed at runtime).
* Reading STM32 Reference Manual is required.
*/
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV4
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
/*
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE_VALUE 4
#define STM32_TIMPRE_ENABLE TRUE
#define STM32_HRTIMSEL 0
#define STM32_STOPKERWUCK 0
#define STM32_STOPWUCK 0
#define STM32_RTCPRE_VALUE 8
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK
#define STM32_FMCSEL STM32_QSPISEL_HCLK
#define STM32_SWPSEL STM32_SWPSEL_PCLK1
#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE_CK
#define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK
#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1
#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
#define STM32_USART16SEL STM32_USART16SEL_PCLK2
#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI16_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_21_PRIORITY 6
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_FDCAN2_PRIORITY 10
#define STM32_IRQ_MDMA_PRIORITY 9
#define STM32_IRQ_QUADSPI1_PRIORITY 10
#define STM32_IRQ_SDMMC1_PRIORITY 9
#define STM32_IRQ_SDMMC2_PRIORITY 9
#define STM32_IRQ_TIM1_UP_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_TIM15_PRIORITY 7
#define STM32_IRQ_TIM16_PRIORITY 7
#define STM32_IRQ_TIM17_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_USART6_PRIORITY 12
#define STM32_IRQ_UART7_PRIORITY 12
#define STM32_IRQ_UART8_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_FDCAN2 FALSE
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM13 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM12 FALSE
#define STM32_ICU_USE_TIM13 FALSE
#define STM32_ICU_USE_TIM14 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM12 FALSE
#define STM32_PWM_USE_TIM13 FALSE
#define STM32_PWM_USE_TIM14 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
/*
* RTC driver system settings.
*/
#define STM32_RTC_PRESA_VALUE 32
#define STM32_RTC_PRESS_VALUE 1024
#define STM32_RTC_CR_INIT 0
#define STM32_RTC_TAMPCR_INIT 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_USE_SDMMC1 TRUE
#define STM32_SDC_USE_SDMMC2 FALSE
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC_PWRSAV TRUE
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 TRUE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USE_UART7 FALSE
#define STM32_SERIAL_USE_UART8 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_UART7_DMA_PRIORITY 0
#define STM32_UART_UART8_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 FALSE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_HOST_WAKEUP_DURATION 2
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
#endif /* MCUCONF_H */

View File

@ -1,53 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\NIL-STM32H755ZI-NUCLEO144\debug"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20&#13;&#10;monitor reset init&#13;&#10;monitor sleep 50&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="NIL-STM32H755ZI-NUCLEO144"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1984968159"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/NIL-STM32H755ZI-NUCLEO144"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<mapAttribute key="org.eclipse.debug.core.preferred_launchers"/>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>

View File

@ -1,104 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#include "ch.h"
#include "nil_test_root.h"
#include "oslib_test_root.h"
/*
* Blinker thread #1.
*/
static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
while (true) {
while (true) {
palSetLine(LINE_LED1);
chThdSleepMilliseconds(50);
palSetLine(LINE_LED2);
chThdSleepMilliseconds(50);
palSetLine(LINE_LED3);
chThdSleepMilliseconds(200);
palClearLine(LINE_LED1);
chThdSleepMilliseconds(50);
palClearLine(LINE_LED2);
chThdSleepMilliseconds(50);
palClearLine(LINE_LED3);
chThdSleepMilliseconds(200);
}
}
}
/*
* Tester thread.
*/
THD_WORKING_AREA(waThread3, 256);
THD_FUNCTION(Thread3, arg) {
(void)arg;
/*
* Activates the serial driver 1 using the driver default configuration.
* PA9 and PA10 are routed to USART1.
*/
sdStart(&SD3, NULL);
/* Welcome message.*/
chnWrite(&SD3, (const uint8_t *)"Hello World!\r\n", 14);
/* Waiting for button push and activation of the test suite.*/
while (true) {
if (palReadLine(LINE_BUTTON)) {
test_execute((BaseSequentialStream *)&SD3, &nil_test_suite);
test_execute((BaseSequentialStream *)&SD3, &oslib_test_suite);
}
chThdSleepMilliseconds(500);
}
}
/*
* Threads creation table, one entry per thread.
*/
THD_TABLE_BEGIN
THD_TABLE_THREAD(0, "blinker1", waThread1, Thread1, NULL)
THD_TABLE_THREAD(4, "tester", waThread3, Thread3, NULL)
THD_TABLE_END
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/* This is now the idle thread loop, you may perform here a low priority
task but you must never try to sleep or wait in this loop. Note that
this tasks runs at the lowest priority level so any instruction added
here will be executed after all other tasks have been started.*/
while (true) {
}
}

View File

@ -224,8 +224,7 @@
</option>
<option>
<name>CCDefines</name>
<state>TEST_CFG_SIZE_REPORT=0</state>
<state>CORTEX_USE_FPU=1</state>
<state></state>
</option>
<option>
<name>CCPreprocFile</name>
@ -558,8 +557,7 @@
</option>
<option>
<name>ADefines</name>
<state>TEST_CFG_SIZE_REPORT=0</state>
<state>CORTEX_USE_FPU=1</state>
<state></state>
</option>
<option>
<name>AList</name>
@ -1316,8 +1314,7 @@
</option>
<option>
<name>CCDefines</name>
<state>TEST_CFG_SIZE_REPORT=0</state>
<state>CORTEX_USE_FPU=1</state>
<state></state>
</option>
<option>
<name>CCPreprocFile</name>
@ -1650,8 +1647,7 @@
</option>
<option>
<name>ADefines</name>
<state>TEST_CFG_SIZE_REPORT=0</state>
<state>CORTEX_USE_FPU=1</state>
<state></state>
</option>
<option>
<name>AList</name>

View File

@ -1,52 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\RT-STM32G474RE-NUCLEO64\debug"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
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<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;brr-usart_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x48000000&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32G474RE-NUCLEO64"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.603687198"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RT-STM32G474RE-NUCLEO64"/>
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<listEntry value="4"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>

View File

@ -1,54 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="0.603687198">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.603687198" moduleId="org.eclipse.cdt.core.settings" name="Default">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.603687198" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="0.603687198." name="/" resourcePath="">
<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.586709963" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.586709963.1446538340" name=""/>
<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1490952991" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1134067298" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.1927705259" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1013764026" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1367371861" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1824820452" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1584496456" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1781547795" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Default">
<resource resourceType="PROJECT" workspacePath="/RT-STM32L552ZE-NUCLEO144"/>
</configuration>
</storageModule>
</cproject>

View File

@ -1,43 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RT-STM32L552ZE-NUCLEO144</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_NUCLEO144_L552ZE</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
<link>
<name>test</name>
<type>2</type>
<locationURI>CHIBIOS/test</locationURI>
</link>
</linkedResources>
</projectDescription>

View File

@ -1,189 +0,0 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data.
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO).
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# FPU-related options.
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, target, sources and paths
#
# Define project name here
PROJECT = ch
# Target settings.
MCU = cortex-m33
# Imported source files and paths.
CHIBIOS := ../../..
CONFDIR := ./cfg
BUILDDIR := ./build
DEPDIR := ./.dep
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l5xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32L5xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_L552ZE/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v8m-mainline.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
include $(CHIBIOS)/test/lib/test.mk
include $(CHIBIOS)/test/rt/rt_test.mk
include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here.
LDSCRIPT= $(STARTUPLD)/STM32L552xE.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(ALLCPPSRC)
# List ASM source files here.
ASMSRC = $(ALLASMSRC)
# List ASM with preprocessor source files here.
ASMXSRC = $(ALLXASMSRC)
# Inclusion directories.
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
# Define C warning options here.
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here.
CPPWARN = -Wall -Wextra -Wundef
#
# Project, target, sources and paths
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user section
##############################################################################
##############################################################################
# Common rules
#
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/arm-none-eabi.mk
include $(RULESPATH)/rules.mk
#
# Common rules
##############################################################################
##############################################################################
# Custom rules
#
#
# Custom rules
##############################################################################

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@ -1,52 +0,0 @@
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View File

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View File

@ -1,86 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include <stdint.h>
#include <stdbool.h>
#include "ch.h"
#include "hal.h"
#include "rt_test_root.h"
#include "oslib_test_root.h"
/*
* This is a periodic thread that does absolutely nothing except flashing
* a LED.
*/
static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("blinker");
while (true) {
palSetLine(LINE_LED1);
chThdSleepMilliseconds(50);
palSetLine(LINE_LED2);
chThdSleepMilliseconds(50);
palSetLine(LINE_LED3);
chThdSleepMilliseconds(200);
palClearLine(LINE_LED1);
chThdSleepMilliseconds(50);
palClearLine(LINE_LED2);
chThdSleepMilliseconds(50);
palClearLine(LINE_LED3);
chThdSleepMilliseconds(200);
}
}
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the serial driver 3 using the driver default configuration.
*/
sdStart(&LPSD1, NULL);
/*
* Creates the example thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO + 1, Thread1, NULL);
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and check the button state.
*/
while (true) {
if (palReadLine(LINE_BUTTON)) {
test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite);
test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
}
chThdSleepMilliseconds(500);
}
}

View File

@ -1,95 +0,0 @@
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View File

@ -1,85 +0,0 @@
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<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
</linkedResources>
</projectDescription>

View File

@ -1,18 +0,0 @@
##############################################################################
# Multi-project makefile rules
#
all:
@echo
@echo === Building for STM32G474RE-Nucleo64 ==============================
+@make --no-print-directory -f ./make/stm32g474re_nucleo64.make all
@echo ====================================================================
@echo
clean:
@echo
+@make --no-print-directory -f ./make/stm32g474re_nucleo64.make clean
@echo
#
##############################################################################

View File

@ -1,756 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file rt/templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_6_1_
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_ST_RESOLUTION)
#define CH_CFG_ST_RESOLUTION 32
#endif
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_CFG_ST_FREQUENCY)
#define CH_CFG_ST_FREQUENCY 10000
#endif
/**
* @brief Time intervals data size.
* @note Allowed values are 16, 32 or 64 bits.
*/
#if !defined(CH_CFG_INTERVALS_SIZE)
#define CH_CFG_INTERVALS_SIZE 32
#endif
/**
* @brief Time types data size.
* @note Allowed values are 16 or 32 bits.
*/
#if !defined(CH_CFG_TIME_TYPES_SIZE)
#define CH_CFG_TIME_TYPES_SIZE 32
#endif
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#if !defined(CH_CFG_ST_TIMEDELTA)
#define CH_CFG_ST_TIMEDELTA 2
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#if !defined(CH_CFG_TIME_QUANTUM)
#define CH_CFG_TIME_QUANTUM 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop.
*/
#if !defined(CH_CFG_NO_IDLE_THREAD)
#define CH_CFG_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_OPTIMIZE_SPEED)
#define CH_CFG_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_TM)
#define CH_CFG_USE_TM TRUE
#endif
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_REGISTRY)
#define CH_CFG_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_WAITEXIT)
#define CH_CFG_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_SEMAPHORES)
#define CH_CFG_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MUTEXES)
#define CH_CFG_USE_MUTEXES TRUE
#endif
/**
* @brief Enables recursive behavior on mutexes.
* @note Recursive mutexes are heavier and have an increased
* memory footprint.
*
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#if !defined(CH_CFG_USE_CONDVARS)
#define CH_CFG_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_EVENTS)
#define CH_CFG_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MESSAGES)
#define CH_CFG_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#if !defined(CH_CFG_USE_DYNAMIC)
#define CH_CFG_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name OSLIB options
* @{
*/
/*===========================================================================*/
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#if !defined(CH_CFG_USE_MAILBOXES)
#define CH_CFG_USE_MAILBOXES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMCORE)
#define CH_CFG_USE_MEMCORE TRUE
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#if !defined(CH_CFG_MEMCORE_SIZE)
#define CH_CFG_MEMCORE_SIZE 0
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_CFG_USE_HEAP)
#define CH_CFG_USE_HEAP TRUE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_MEMPOOLS)
#define CH_CFG_USE_MEMPOOLS TRUE
#endif
/**
* @brief Objects FIFOs APIs.
* @details If enabled then the objects FIFOs APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_FIFOS)
#define CH_CFG_USE_OBJ_FIFOS TRUE
#endif
/**
* @brief Pipes APIs.
* @details If enabled then the pipes APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_PIPES)
#define CH_CFG_USE_PIPES TRUE
#endif
/**
* @brief Objects Caches APIs.
* @details If enabled then the objects caches APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_OBJ_CACHES)
#define CH_CFG_USE_OBJ_CACHES TRUE
#endif
/**
* @brief Delegate threads APIs.
* @details If enabled then the delegate threads APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_DELEGATES)
#define CH_CFG_USE_DELEGATES TRUE
#endif
/**
* @brief Jobs Queues APIs.
* @details If enabled then the jobs queues APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_CFG_USE_JOBS)
#define CH_CFG_USE_JOBS TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Objects factory options
* @{
*/
/*===========================================================================*/
/**
* @brief Objects Factory APIs.
* @details If enabled then the objects factory APIs are included in the
* kernel.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_CFG_USE_FACTORY)
#define CH_CFG_USE_FACTORY TRUE
#endif
/**
* @brief Maximum length for object names.
* @details If the specified length is zero then the name is stored by
* pointer but this could have unintended side effects.
*/
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#endif
/**
* @brief Enables the registry of generic objects.
*/
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
#endif
/**
* @brief Enables factory for generic buffers.
*/
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
#endif
/**
* @brief Enables factory for semaphores.
*/
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
#define CH_CFG_FACTORY_SEMAPHORES TRUE
#endif
/**
* @brief Enables factory for mailboxes.
*/
#if !defined(CH_CFG_FACTORY_MAILBOXES)
#define CH_CFG_FACTORY_MAILBOXES TRUE
#endif
/**
* @brief Enables factory for objects FIFOs.
*/
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
#endif
/**
* @brief Enables factory for Pipes.
*/
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
#define CH_CFG_FACTORY_PIPES TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_STATISTICS)
#define CH_DBG_STATISTICS FALSE
#endif
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the trace buffer is activated.
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_MASK)
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
#endif
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
#define CH_DBG_TRACE_BUFFER_SIZE 128
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#if !defined(CH_DBG_THREADS_PROFILING)
#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief System structure extension.
* @details User fields added to the end of the @p ch_system_t structure.
*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief System initialization hook.
* @details User initialization code added to the @p chSysInit() function
* just before interrupts are enabled globally.
*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p _thread_init() function.
*
* @note It is invoked from within @p _thread_init() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
#define CH_CFG_TRACE_HOOK(tep) { \
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* CHCONF_H */
/** @} */

View File

@ -1,531 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_7_1_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT TRUE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS TRUE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables circular transfers APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
#define SPI_USE_CIRCULAR FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

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@ -1,372 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32G4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32G4xx_MCUCONF
#define STM32G473_MCUCONF
#define STM32G483_MCUCONF
#define STM32G474_MCUCONF
#define STM32G484_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSE_ENABLED TRUE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 6
#define STM32_PLLN_VALUE 85
#define STM32_PLLPDIV_VALUE 0
#define STM32_PLLP_VALUE 7
#define STM32_PLLQ_VALUE 8
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clock sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
#define STM32_FDCANSEL STM32_FDCANSEL_HSE
#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 6
#define STM32_IRQ_EXTI1_PRIORITY 6
#define STM32_IRQ_EXTI2_PRIORITY 6
#define STM32_IRQ_EXTI3_PRIORITY 6
#define STM32_IRQ_EXTI4_PRIORITY 6
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#define STM32_IRQ_EXTI164041_PRIORITY 6
#define STM32_IRQ_EXTI17_PRIORITY 6
#define STM32_IRQ_EXTI18_PRIORITY 6
#define STM32_IRQ_EXTI19_PRIORITY 6
#define STM32_IRQ_EXTI20_PRIORITY 6
#define STM32_IRQ_EXTI212229_PRIORITY 6
#define STM32_IRQ_EXTI30_32_PRIORITY 6
#define STM32_IRQ_EXTI33_PRIORITY 6
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_FDCAN2_PRIORITY 10
#define STM32_IRQ_FDCAN3_PRIORITY 10
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM3_PRIORITY 7
#define STM32_IRQ_TIM4_PRIORITY 7
#define STM32_IRQ_TIM5_PRIORITY 7
#define STM32_IRQ_TIM6_PRIORITY 7
#define STM32_IRQ_TIM7_PRIORITY 7
#define STM32_IRQ_TIM8_UP_PRIORITY 7
#define STM32_IRQ_TIM8_CC_PRIORITY 7
#define STM32_IRQ_TIM20_UP_PRIORITY 7
#define STM32_IRQ_TIM20_CC_PRIORITY 7
#define STM32_IRQ_USART1_PRIORITY 12
#define STM32_IRQ_USART2_PRIORITY 12
#define STM32_IRQ_USART3_PRIORITY 12
#define STM32_IRQ_UART4_PRIORITY 12
#define STM32_IRQ_UART5_PRIORITY 12
#define STM32_IRQ_LPUART1_PRIORITY 12
/*
* ADC driver system settings.
*/
#define STM32_ADC_DUAL_MODE FALSE
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_USE_ADC4 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC4_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_FDCAN2 FALSE
#define STM32_CAN_USE_FDCAN3 FALSE
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_USE_DAC2_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH1 FALSE
#define STM32_DAC_USE_DAC3_CH2 FALSE
#define STM32_DAC_USE_DAC4_CH1 FALSE
#define STM32_DAC_USE_DAC4_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC3_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC4_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_DAC_DAC4_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 TRUE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM15 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM15 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM15 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
#define STM32_PWM_USE_TIM20 FALSE
/*
* RTC driver system settings.
*/
/*
* SDC driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_LPUART1 TRUE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* TRNG driver system settings.
*/
#define STM32_TRNG_USE_RNG1 FALSE
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_USB1 FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
/*
* WSPI driver system settings.
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#endif /* MCUCONF_H */

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@ -1,57 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file portab.c
* @brief Application portability module code.
*
* @addtogroup application_portability
* @{
*/
#include "hal.h"
#include "portab.h"
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module exported functions. */
/*===========================================================================*/
void portab_setup(void) {
}
/** @} */

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@ -1,75 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file portab.h
* @brief Application portability macros and structures.
*
* @addtogroup application_portability
* @{
*/
#ifndef PORTAB_H
#define PORTAB_H
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
#define PORTAB_LINE_LED1 LINE_LED
#define PORTAB_LED_OFF PAL_LOW
#define PORTAB_LED_ON PAL_HIGH
#define PORTAB_LINE_BUTTON LINE_BUTTON
#define PORTAB_BUTTON_PRESSED PAL_HIGH
#define PORTAB_SD1 LPSD1
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void portab_setup(void);
#ifdef __cplusplus
}
#endif
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* PORTAB_H */
/** @} */

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@ -1,52 +0,0 @@
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View File

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "chprintf.h"
#include "portab.h"
#define TEST_CYCLES 1000U
static time_measurement_t tm1, tm2;
static thread_reference_t tr;
/*
* Flyback thread.
*/
static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("flyback");
while (true) {
/* Waiting for wakeup from PENDSV then stopping measurement.*/
chSysLock();
(void) chThdSuspendS(&tr);
chTMStopMeasurementX(&tm2);
chSysUnlock();
}
}
/*
* PENDSV ISR.
*/
CH_IRQ_HANDLER(PendSV_Handler) {
CH_IRQ_PROLOGUE();
chTMChainMeasurementToX(&tm1, &tm2);
chSysLockFromISR();
chThdResumeI(&tr, MSG_OK);
chSysUnlockFromISR();
CH_IRQ_EPILOGUE();
}
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/* Starting a serial port for test report output.*/
sdStart(&PORTAB_SD1, NULL);
/* Starting the flyback thread.*/
tr = NULL;
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO + 1U, Thread1, NULL);
/* Initializing a TM objects for measurement of latency.*/
chTMObjectInit(&tm1);
chTMObjectInit(&tm2);
/* Setting up PENDSV for the latency test. Highest available priority
is used.*/
nvicSetSystemHandlerPriority(HANDLER_PENDSV, CORTEX_MAX_KERNEL_PRIORITY);
/* Printing banner.*/
chprintf((BaseSequentialStream *)&PORTAB_SD1, "*** Compiled: %s\r\n", __DATE__ " - " __TIME__);
#if defined(PLATFORM_NAME)
chprintf((BaseSequentialStream *)&PORTAB_SD1, "*** Platform: %s\r\n", PLATFORM_NAME);
#endif
#if defined(BOARD_NAME)
chprintf((BaseSequentialStream *)&PORTAB_SD1, "*** Test Board: %s\r\n", BOARD_NAME);
#endif
#if defined(PORT_ARCHITECTURE_NAME)
chprintf((BaseSequentialStream *)&PORTAB_SD1, "*** Architecture: %s\r\n", PORT_ARCHITECTURE_NAME);
#endif
#if defined(PORT_CORE_VARIANT_NAME)
chprintf((BaseSequentialStream *)&PORTAB_SD1, "*** Core Variant: %s @ %uMHz\r\n", PORT_CORE_VARIANT_NAME, SystemCoreClock / 1000000U);
#endif
#if defined(PORT_COMPILER_NAME)
chprintf((BaseSequentialStream *)&PORTAB_SD1, "*** Compiler: %s\r\n\r\n", PORT_COMPILER_NAME);
#endif
chThdSleepMilliseconds(500U);
/* Test loop.*/
for (unsigned i = 0U; i < TEST_CYCLES; i++) {
/* Triggering PENDSV, it will happen on the unlock.*/
chSysLock();
SCB->ICSR =SCB_ICSR_PENDSVSET_Msk;
chTMStartMeasurementX(&tm1);
chSysUnlock();
chThdSleepMilliseconds(1);
}
/* Printing results.*/
chprintf((BaseSequentialStream *)&PORTAB_SD1, "ISR activation time latency\r\n\r\n");
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Iterations: %u\r\n", tm1.n);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Last measurement: %u\r\n", tm1.last);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Best measurement: %u\r\n", tm1.best);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Worst measurement: %u\r\n", tm1.worst);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Cumulative time: %u\r\n\r\n", (uint32_t)tm1.cumulative);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Thread fly-back latency\r\n\r\n");
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Iterations: %u\r\n", tm2.n);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Last measurement: %u\r\n", tm2.last);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Best measurement: %u\r\n", tm2.best);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Worst measurement: %u\r\n", tm2.worst);
chprintf((BaseSequentialStream *)&PORTAB_SD1, "Cumulative time: %u\r\n\r\n", (uint32_t)tm2.cumulative);
/*
* Normal main() thread activity, if the button is pressed then the DAC
* transfer is stopped.
*/
while (true) {
if (palReadLine(PORTAB_LINE_BUTTON) == PORTAB_BUTTON_PRESSED) {
}
chThdSleepMilliseconds(500);
}
return 0;
}

View File

@ -1,191 +0,0 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data.
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO).
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# FPU-related options.
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, target, sources and paths
#
# Define project name here
PROJECT = ch
# Target settings.
MCU = cortex-m4
# Imported source files and paths.
CHIBIOS := ../../..
CONFDIR := ./cfg/stm32g474re_nucleo64
BUILDDIR := ./build/stm32g474re_nucleo64
DEPDIR := ./.dep/stm32g474re_nucleo64
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g4xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
#include $(CHIBIOS)/test/lib/test.mk
#include $(CHIBIOS)/test/rt/rt_test.mk
#include $(CHIBIOS)/test/oslib/oslib_test.mk
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32G474xE.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
$(CONFDIR)/portab.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC = $(ALLCPPSRC)
# List ASM source files here.
ASMSRC = $(ALLASMSRC)
# List ASM with preprocessor source files here.
ASMXSRC = $(ALLXASMSRC)
# Inclusion directories.
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
# Define C warning options here.
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
# Define C++ warning options here.
CPPWARN = -Wall -Wextra -Wundef
#
# Project, target, sources and paths
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user section
##############################################################################
##############################################################################
# Common rules
#
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/arm-none-eabi.mk
include $(RULESPATH)/rules.mk
#
# Common rules
##############################################################################
##############################################################################
# Custom rules
#
#
# Custom rules
##############################################################################

2
doc/ex/rsync_web.sh Normal file
View File

@ -0,0 +1,2 @@
#!/bin/bash
rsync -avP -e ssh --delete --exclude=.* ./html/ gdisirio,chibios@web.sourceforge.net:/home/groups/c/ch/chibios/htdocs/docs3/ex

View File

@ -29,12 +29,6 @@
* - EX resides on top of HAL which offers, among others, a set of abstract
* interfaces like Generic Sensor, Gyroscope, Magnetometer, Accelerometer,
* Barometer, Thermometer: EX offers a phisical implementation of them.
* - Currently Analog Devices supported devices are:
* - @b ADXL355: Low Noise, Low Drift, Low Power, 3-Axis Accelerometers;
* - Currently Bosch supported devices are:
* - @b BMP085: Digital pressure sensor;
* - Currently Micron Technology supported devices are:
* - @b M25Q: Serial NOR Flash;
* - Currently STMicroelectronics supported devices are:
* - @b HTS221: Capacitive digital humidity sensor;
* - @b L3GD20: 3-axis digital gyroscope;
@ -44,4 +38,8 @@
* - @b LPS25H: Piezoresistive 260-1260 hPa pressure sensor;
* - @b LSM6DS0: 6-axis iNEMO inertial module;
* - @b LSM303DLHC: Ultra compact high performance e-compass;
* - Currently Micron Technology supported devices are:
* - @b M25Q: Serial NOR Flash;
* - Currently Bosch supported devices are:
* - @b BMP085: Digital pressure sensor;
*/

2
doc/full_rm/rsync_web.sh Normal file
View File

@ -0,0 +1,2 @@
#!/bin/bash
rsync -avP -e ssh --delete --exclude=.* ./html/ gdisirio,chibios@web.sourceforge.net:/home/groups/c/ch/chibios/htdocs/docs3/full

View File

@ -1156,7 +1156,7 @@ HTML_FOOTER = ../common/rsc/footer_html.html
# obsolete.
# This tag requires that the tag GENERATE_HTML is set to YES.
HTML_STYLESHEET = ../common/rsc/custom.css
HTML_STYLESHEET =
# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
# cascading style sheets that are included after the standard style sheets

View File

@ -1156,7 +1156,7 @@ HTML_FOOTER = ../common/rsc/footer_html.html
# obsolete.
# This tag requires that the tag GENERATE_HTML is set to YES.
HTML_STYLESHEET = ../common/rsc/custom.css
HTML_STYLESHEET =
# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
# cascading style sheets that are included after the standard style sheets

2
doc/hal/rsync_web.sh Normal file
View File

@ -0,0 +1,2 @@
#!/bin/bash
rsync -avP -e ssh --delete --exclude=.* ./html/ gdisirio,chibios@web.sourceforge.net:/home/groups/c/ch/chibios/htdocs/docs3/hal

View File

@ -1155,7 +1155,7 @@ HTML_FOOTER = ../common/rsc/footer_html.html
# obsolete.
# This tag requires that the tag GENERATE_HTML is set to YES.
HTML_STYLESHEET = ../common/rsc/custom.css
HTML_STYLESHEET =
# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
# cascading style sheets that are included after the standard style sheets

View File

@ -1155,7 +1155,7 @@ HTML_FOOTER = ../common/rsc/footer_html.html
# obsolete.
# This tag requires that the tag GENERATE_HTML is set to YES.
HTML_STYLESHEET = ../common/rsc/custom.css
HTML_STYLESHEET =
# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
# cascading style sheets that are included after the standard style sheets

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 12:36:40
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 27672 bytes
*** RO data size: 7068 bytes
*** Data size: 128 bytes
*** BSS size: 4440 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 1
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 2000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 159984 msgs/S, 319968 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 119589 msgs/S, 239178 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 509688 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 125423 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 158574 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 757816 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 12:36:40
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 27672 bytes
*** RO data size: 7068 bytes
*** Data size: 128 bytes
*** BSS size: 4440 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 12:34:45
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 27496 bytes
*** RO data size: 7068 bytes
*** Data size: 128 bytes
*** BSS size: 3488 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 1
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 2000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 188466 msgs/S, 376932 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 134820 msgs/S, 269640 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 671272 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 142281 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 186513 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 757832 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 12:34:45
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 27496 bytes
*** RO data size: 7068 bytes
*** Data size: 128 bytes
*** BSS size: 3488 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 11:50:46
*** Platform: STM32G0 Entry-level
*** Test Board: STMicroelectronics STM32 Nucleo64-G071RB
***
*** Text size: 27204 bytes
*** RO data size: 7032 bytes
*** Data size: 128 bytes
*** BSS size: 3420 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv6-M
--- Core Variant: Cortex-M0+
--- Compiler: GCC 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
--- Port Info: Preemption through NMI
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 0
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 1000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 175820 msgs/S, 351640 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 129290 msgs/S, 258580 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 540648 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 128511 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 161613 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 627436 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 11:50:46
*** Platform: STM32G0 Entry-level
*** Test Board: STMicroelectronics STM32 Nucleo64-G071RB
***
*** Text size: 27204 bytes
*** RO data size: 7032 bytes
*** Data size: 128 bytes
*** BSS size: 3420 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv6-M
--- Core Variant: Cortex-M0+
--- Compiler: GCC 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
--- Port Info: Preemption through NMI
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 0
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 11:31:47
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 29176 bytes
*** RO data size: 7036 bytes
*** Data size: 128 bytes
*** BSS size: 4232 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 0
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 502952 msgs/S, 1005904 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 386358 msgs/S, 772716 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 1491216 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 371175 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 447364 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 2481728 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 11:31:47
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 29176 bytes
*** RO data size: 7036 bytes
*** Data size: 128 bytes
*** BSS size: 4232 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 0
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 11:25:52
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 29016 bytes
*** RO data size: 7036 bytes
*** Data size: 128 bytes
*** BSS size: 3416 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 0
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 629622 msgs/S, 1259244 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 456984 msgs/S, 913968 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 2124984 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 435893 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 544866 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 2481732 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 11:25:52
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 29016 bytes
*** RO data size: 7036 bytes
*** Data size: 128 bytes
*** BSS size: 3416 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 0
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 12:26:16
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 32352 bytes
*** RO data size: 7520 bytes
*** Data size: 128 bytes
*** BSS size: 4904 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 0
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 5000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 1764685 msgs/S, 3529370 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 1379292 msgs/S, 2758584 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 5680392 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 1263140 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 1561249 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 6575260 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 12:26:16
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 32352 bytes
*** RO data size: 7520 bytes
*** Data size: 128 bytes
*** BSS size: 4904 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 0
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,275 +0,0 @@
*** ChibiOS/NIL Test Suite
***
*** Compiled: Mar 18 2020 - 12:19:04
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 32176 bytes
*** RO data size: 7520 bytes
*** Data size: 128 bytes
*** BSS size: 4088 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/NIL
--- Stable Flag: 0
--- Version String: 4.0.0
--- Major Number: 4
--- Minor Number: 0
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_MAX_THREADS: 8
--- CH_CFG_AUTOSTART_THREADS: 1
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 5000
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_MUTEXES: 0
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 2.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (Thread Sleep functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Semaphores)
----------------------------------------------------------------------------
--- Test Case 4.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Semaphore primitives, with state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Semaphores timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 6.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 7.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages performance #1)
--- Score : 2142832 msgs/S, 4285664 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Messages performance #2)
--- Score : 1638551 msgs/S, 3277102 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.3 (Context Switch performance)
--- Score : 8135512 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.4 (Threads performance, full cycle)
--- Score : 1462518 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.5 (Threads performance, create/exit only)
--- Score : 1904741 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.6 (Semaphores wait/signal performance)
--- Score : 6575268 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.7 (RAM Footprint)
--- System: 232 bytes
--- Thread: 24 bytes
--- Semaph: 4 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 32 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 12:19:04
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 32176 bytes
*** RO data size: 7520 bytes
*** Data size: 128 bytes
*** BSS size: 4088 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 0
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

2
doc/nil/rsync_web.sh Normal file
View File

@ -0,0 +1,2 @@
#!/bin/bash
rsync -avP -e ssh --delete --exclude=.* ./html/ gdisirio,chibios@web.sourceforge.net:/home/groups/c/ch/chibios/htdocs/docs3/nil

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 17 2020 - 12:21:22
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 36344 bytes
*** RO data size: 9848 bytes
*** Data size: 220 bytes
*** BSS size: 6624 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 218137 msgs/S, 436274 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 178184 msgs/S, 356368 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 178184 msgs/S, 356368 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 628696 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 137376 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 173044 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 56416 reschedules/S, 338496 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 436280 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 455784 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 1180076 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 666520 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 17 2020 - 12:21:22
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 36344 bytes
*** RO data size: 9848 bytes
*** Data size: 220 bytes
*** BSS size: 6624 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 17 2020 - 12:18:44
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 36248 bytes
*** RO data size: 9848 bytes
*** Data size: 220 bytes
*** BSS size: 5128 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 274764 msgs/S, 549528 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 214253 msgs/S, 428506 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 214254 msgs/S, 428508 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 894264 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 159973 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 210495 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 67154 reschedules/S, 402924 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 549520 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 450110 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 1180124 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 666552 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 17 2020 - 12:18:44
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
***
*** Text size: 36248 bytes
*** RO data size: 9848 bytes
*** Data size: 220 bytes
*** BSS size: 5128 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,239 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 17 2020 - 13:48:00
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: IAR
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 192466 msgs/S, 384932 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 160678 msgs/S, 321356 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 160678 msgs/S, 321356 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 519728 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 124107 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 163596 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 47172 reschedules/S, 283032 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 313300 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 541360 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 972720 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 749808 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,239 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 17 2020 - 13:57:35
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: IAR
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 235245 msgs/S, 470490 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 189437 msgs/S, 378874 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 189437 msgs/S, 378874 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 688856 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 140049 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 192477 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 54453 reschedules/S, 326718 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 367740 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 541394 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 972752 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 749832 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,239 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 17 2020 - 14:32:12
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: RVCT
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 196137 msgs/S, 392274 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 170982 msgs/S, 341964 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 170982 msgs/S, 341964 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 610024 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 127178 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 161397 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 55203 reschedules/S, 331218 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 399348 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 321458 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 834580 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 613924 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,239 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 17 2020 - 14:25:56
*** Platform: STM32F303xC Analog & DSP
*** Test Board: STMicroelectronics STM32F3-Discovery
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: RVCT
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 240753 msgs/S, 481506 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 202776 msgs/S, 405552 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 202777 msgs/S, 405554 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 856976 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 143971 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 190439 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 64970 reschedules/S, 389820 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 495600 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 328850 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 815684 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 598620 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 18 2020 - 10:53:26
*** Platform: STM32G0 Entry-level
*** Test Board: STMicroelectronics STM32 Nucleo64-G071RB
***
*** Text size: 35408 bytes
*** RO data size: 9864 bytes
*** Data size: 220 bytes
*** BSS size: 5048 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv6-M
--- Core Variant: Cortex-M0+
--- Compiler: GCC 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
--- Port Info: Preemption through NMI
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 0
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 199373 msgs/S, 398746 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 160398 msgs/S, 320796 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 160398 msgs/S, 320796 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 591904 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 120298 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 150233 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 49307 reschedules/S, 295842 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 439852 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 388936 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 1142844 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 524584 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 116 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 10:53:26
*** Platform: STM32G0 Entry-level
*** Test Board: STMicroelectronics STM32 Nucleo64-G071RB
***
*** Text size: 35408 bytes
*** RO data size: 9864 bytes
*** Data size: 220 bytes
*** BSS size: 5048 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv6-M
--- Core Variant: Cortex-M0+
--- Compiler: GCC 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
--- Port Info: Preemption through NMI
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 18 2020 - 11:08:49
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 37608 bytes
*** RO data size: 9836 bytes
*** Data size: 220 bytes
*** BSS size: 6416 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 620426 msgs/S, 1240852 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 524683 msgs/S, 1049366 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 524683 msgs/S, 1049366 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 1730272 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 399053 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 494181 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 160984 reschedules/S, 965904 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 1218620 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 1452380 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 3399976 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 2023796 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 11:08:49
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 37608 bytes
*** RO data size: 9836 bytes
*** Data size: 220 bytes
*** BSS size: 6416 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 18 2020 - 10:58:22
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 37584 bytes
*** RO data size: 9844 bytes
*** Data size: 220 bytes
*** BSS size: 5052 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 255
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 809511 msgs/S, 1619022 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 653837 msgs/S, 1307674 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 653837 msgs/S, 1307674 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 2566024 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 469604 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 602831 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 194953 reschedules/S, 1169718 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 1626760 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 1490826 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 3269216 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 2048180 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 120 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 10:58:22
*** Platform: STM32G4 Hi-resolution Line
*** Test Board: STMicroelectronics STM32 Nucleo64-G474RE
***
*** Text size: 37584 bytes
*** RO data size: 9844 bytes
*** Data size: 220 bytes
*** BSS size: 5052 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M4
--- Compiler: GCC 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 18 2020 - 11:06:17
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 41760 bytes
*** RO data size: 10668 bytes
*** Data size: 220 bytes
*** BSS size: 9104 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 0
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 1714255 msgs/S, 3428510 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 1554056 msgs/S, 3108112 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 1558111 msgs/S, 3116222 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 5338384 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 1087365 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 1389931 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 494992 reschedules/S, 2969952 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 3844540 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 3222632 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 7999872 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 6575244 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 2176 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 11:06:17
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 41760 bytes
*** RO data size: 10668 bytes
*** Data size: 220 bytes
*** BSS size: 9104 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7F
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

View File

@ -1,372 +0,0 @@
*** ChibiOS/RT Test Suite
***
*** Compiled: Mar 18 2020 - 11:02:52
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 41696 bytes
*** RO data size: 10668 bytes
*** Data size: 220 bytes
*** BSS size: 7744 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Kernel Info)
--- Product: ChibiOS/RT
--- Stable Flag: 1
--- Version String: 6.1.0
--- Major Number: 6
--- Minor Number: 1
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Kernel Settings)
--- CH_CFG_ST_RESOLUTION: 32
--- CH_CFG_ST_FREQUENCY: 10000
--- CH_CFG_INTERVALS_SIZE: 32
--- CH_CFG_TIME_TYPES_SIZE: 32
--- CH_CFG_ST_TIMEDELTA: 2
--- CH_CFG_TIME_QUANTUM: 0
--- CH_CFG_MEMCORE_SIZE: 0
--- CH_CFG_NO_IDLE_THREAD: 0
--- CH_CFG_OPTIMIZE_SPEED: 1
--- CH_CFG_USE_TM: 1
--- CH_CFG_USE_REGISTRY: 1
--- CH_CFG_USE_WAITEXIT: 1
--- CH_CFG_USE_SEMAPHORES: 1
--- CH_CFG_USE_SEMAPHORES_PRIORITY: 0
--- CH_CFG_USE_MUTEXES: 1
--- CH_CFG_USE_MUTEXES_RECURSIVE: 0
--- CH_CFG_USE_CONDVARS: 1
--- CH_CFG_USE_CONDVARS_TIMEOUT: 1
--- CH_CFG_USE_EVENTS: 1
--- CH_CFG_USE_EVENTS_TIMEOUT: 1
--- CH_CFG_USE_MESSAGES: 1
--- CH_CFG_USE_MESSAGES_PRIORITY: 0
--- CH_CFG_USE_DYNAMIC: 1
--- CH_DBG_STATISTICS: 0
--- CH_DBG_SYSTEM_STATE_CHECK: 0
--- CH_DBG_ENABLE_CHECKS: 0
--- CH_DBG_ENABLE_ASSERTS: 0
--- CH_DBG_TRACE_MASK: 0
--- CH_DBG_TRACE_BUFFER_SIZE: 128
--- CH_DBG_ENABLE_STACK_CHECK: 0
--- CH_DBG_FILL_THREADS: 0
--- CH_DBG_THREADS_PROFILING: 0
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (System layer and port interface)
----------------------------------------------------------------------------
--- Test Case 2.1 (System integrity functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Critical zones functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Interrupts handling functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Time and Intervals Functionality)
----------------------------------------------------------------------------
--- Test Case 3.1 (System Tick Counter functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Time ranges functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Threads Functionality)
----------------------------------------------------------------------------
--- Test Case 4.1 (Thread Sleep functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.2 (Ready List functionality, threads priority order)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.3 (Priority change test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.4 (Priority change test with Priority Inheritance)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Suspend/Resume)
----------------------------------------------------------------------------
--- Test Case 5.1 (Suspend and Resume functionality)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Counter Semaphores)
----------------------------------------------------------------------------
--- Test Case 6.1 (Semaphore primitives, no state change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Semaphore enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Semaphore timeout test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.4 (Testing chSemAddCounterI() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.5 (Testing chSemWaitSignal() functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.6 (Testing Binary Semaphores special case)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Mutexes, Condition Variables and Priority Inheritance)
----------------------------------------------------------------------------
--- Test Case 7.1 (Priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Priority return verification)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Repeated locks, non recursive scenario)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.4 (Condition Variable signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.5 (Condition Variable broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.6 (Condition Variable priority boost test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Synchronous Messages)
----------------------------------------------------------------------------
--- Test Case 8.1 (Messages Server loop)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Event Sources and Event Flags)
----------------------------------------------------------------------------
--- Test Case 9.1 (Events registration)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Event Flags dispatching)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Events Flags wait using chEvtWaitOne())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Events Flags wait using chEvtWaitAny())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Events Flags wait using chEvtWaitAll())
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Events Flags wait timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.7 (Broadcasting using chEvtBroadcast())
--- Result: SUCCESS
============================================================================
=== Test Sequence 10 (Dynamic threads)
----------------------------------------------------------------------------
--- Test Case 10.1 (Threads creation from Memory Heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Threads creation from Memory Pool)
--- Result: SUCCESS
============================================================================
=== Test Sequence 11 (Benchmarks)
----------------------------------------------------------------------------
--- Test Case 11.1 (Messages performance #1)
--- Score : 2222189 msgs/S, 4444378 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Messages performance #2)
--- Score : 1846129 msgs/S, 3692258 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Messages performance #3)
--- Score : 1846131 msgs/S, 3692262 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Context Switch performance)
--- Score : 7164080 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Threads performance, full cycle)
--- Score : 1284109 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Threads performance, create/exit only)
--- Score : 1587926 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Mass reschedule performance)
--- Score : 601077 reschedules/S, 3606462 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Round-Robin voluntary reschedule)
--- Score : 4804740 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Virtual Timers set/reset performance)
--- Score : 3401870 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Semaphores wait/signal performance)
--- Score : 8135492 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Mutexes lock/unlock performance)
--- Score : 6575248 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (RAM Footprint)
--- System: 2176 bytes
--- Thread: 68 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- EventS: 4 bytes
--- EventL: 20 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS
*** ChibiOS OS Library Test Suite
***
*** Compiled: Mar 18 2020 - 11:02:52
*** Platform: STM32H755 Dual Core Very High Performance with DSP and FPU
*** Test Board: STMicroelectronics STM32 Nucleo144-H755ZI
***
*** Text size: 41696 bytes
*** RO data size: 10668 bytes
*** Data size: 220 bytes
*** BSS size: 7744 bytes
============================================================================
=== Test Sequence 1 (Information)
----------------------------------------------------------------------------
--- Test Case 1.1 (Port Info)
--- Architecture: ARMv7E-M
--- Core Variant: Cortex-M7
--- Compiler: GCC 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
--- Port Info: Advanced kernel mode
--- Natural alignment: 4
--- Stack alignment: 8
--- Working area alignment: 8
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (OS Library Info)
--- Product: ChibiOS/LIB
--- Stable Flag: 1
--- Version String: 1.2.0
--- Major Number: 1
--- Minor Number: 2
--- Patch Number: 0
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (OS Library Settings)
--- CH_CFG_USE_MAILBOXES: 1
--- CH_CFG_USE_MEMCORE: 1
--- CH_CFG_USE_HEAP: 1
--- CH_CFG_USE_MEMPOOLS: 1
--- CH_CFG_USE_OBJ_FIFOS: 1
--- CH_CFG_USE_PIPES: 1
--- CH_CFG_USE_OBJ_CACHES: 1
--- CH_CFG_USE_DELEGATES: 1
--- CH_CFG_USE_FACTORY: 1
--- CH_CFG_FACTORY_MAX_NAMES_LENGTH: 8
--- CH_CFG_FACTORY_OBJECTS_REGISTRY: 1
--- CH_CFG_FACTORY_GENERIC_BUFFERS: 1
--- CH_CFG_FACTORY_SEMAPHORES: 1
--- CH_CFG_FACTORY_MAILBOXES: 1
--- CH_CFG_FACTORY_OBJ_FIFOS: 1
--- CH_CFG_FACTORY_PIPES: 1
--- Result: SUCCESS
============================================================================
=== Test Sequence 2 (Mailboxes)
----------------------------------------------------------------------------
--- Test Case 2.1 (Mailbox normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Mailbox I-Class API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Mailbox timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 3 (Pipes)
----------------------------------------------------------------------------
--- Test Case 3.1 (Pipes normal API, non-blocking tests)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Pipe timeouts)
--- Result: SUCCESS
============================================================================
=== Test Sequence 4 (Jobs Queues)
----------------------------------------------------------------------------
--- Test Case 4.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 5 (Thread Delegates)
----------------------------------------------------------------------------
--- Test Case 5.1 (Dispatcher test)
--- Result: SUCCESS
============================================================================
=== Test Sequence 6 (Objects Caches)
----------------------------------------------------------------------------
--- Test Case 6.1 (Cache initialization)
--- Result: SUCCESS
============================================================================
=== Test Sequence 7 (Memory Pools)
----------------------------------------------------------------------------
--- Test Case 7.1 (Loading and emptying a memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.2 (Loading and emptying a guarded memory pool without waiting)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.3 (Guarded Memory Pools timeout)
--- Result: SUCCESS
============================================================================
=== Test Sequence 8 (Memory Heaps)
----------------------------------------------------------------------------
--- Test Case 8.1 (Allocation and fragmentation)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.2 (Default Heap)
--- Result: SUCCESS
============================================================================
=== Test Sequence 9 (Objects Factory)
----------------------------------------------------------------------------
--- Test Case 9.1 (Objects Registry)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic Buffers Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic Semaphores Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.4 (Dynamic Mailboxes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.5 (Dynamic Objects FIFOs Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.6 (Dynamic Pipes Factory)
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

2
doc/rt/rsync_web.sh Normal file
View File

@ -0,0 +1,2 @@
#!/bin/bash
rsync -avP -e ssh --delete --exclude=.* ./html/ gdisirio,chibios@web.sourceforge.net:/home/groups/c/ch/chibios/htdocs/docs3/rt

View File

@ -207,9 +207,7 @@ typedef enum
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
/* CHIBIOS FIX */
//#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /* FPU present */
#define __DSP_PRESENT 1U /* DSP extension present */
@ -446,7 +444,7 @@ typedef struct
} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU
* @brief Debug MCU - TODO review for STM32L5 to be done
*/
typedef struct
{
@ -454,7 +452,7 @@ typedef struct
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
@ -1300,9 +1298,7 @@ typedef struct
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
/* CHIBIOS FIX */
//#elif (__ARMCC_VERSION >= 6010050)
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
@ -1673,88 +1669,22 @@ typedef struct
#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
/*!< Debug MCU registers base address */
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0044000UL)
#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */
#define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */
/*!< Internal Flash size */
/* Internal Flash size */
#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \
((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \
(((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U)))
/*!< OTP Area */
/* OTP Area */
#define OTP_BASE (0x0BFA0000UL)
#define OTP_SIZE (0x200U)
/*!< Bootloader Area */
#define BL_ID_ADDR (0x0BF97FFEUL) /*!< Bootloader ID address */
#define BL_ID (*(uint8_t*)BL_ID_ADDR) /*!< Bootloader ID */
/*!< Root Secure Service Library */
/************ RSSLIB SAU system Flash region definition constants *************/
#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF97F40UL)
#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF97FFFUL)
/************ RSSLIB function return constants ********************************/
#define RSSLIB_ERROR (0xF5F5F5F5UL)
#define RSSLIB_SUCCESS (0xEAEAEAEAUL)
/*!< RSSLIB pointer function structure address definition */
#define RSSLIB_PFUNC_BASE (0x0BF97F40UL)
#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
/*!< HDP Area constant definition */
#define RSSLIB_HDP_AREA_Pos (0U)
#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos )
#define RSSLIB_HDP_AREA1_Pos (0U)
#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos )
#define RSSLIB_HDP_AREA2_Pos (1U)
#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos )
/**
* @brief Prototype of RSSLIB Close and exit HDP Function
* @detail This function close the requested hdp area passed in input
* parameter and jump to the reset handler present within the
* Vector table. The function does not return on successful execution.
* @param HdpArea notifies which hdp area to close, can be a combination of
* hdpa area 1 and hdp area 2
* @param pointer on the vector table containing the reset handler the function
* jumps to.
* @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
*/
typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr );
/**
* @brief RSSLib non-secure callable function pointer structure
*/
typedef struct
{
__IM uint32_t Reserved[8];
}NSC_pFuncTypeDef;
/**
* @brief RSSLib secure callable function pointer structure
*/
typedef struct
{
__IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL90; /*!< RSSLIB Bootloader ID90 Close and exit HDP Address offset: 0x20 */
__IM uint32_t Reserved2;
__IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL91; /*!< RSSLIB Bootloader ID91 Close and exit HDP Address offset: 0x28 */
}S_pFuncTypeDef;
/**
* @brief RSSLib function pointer structure
*/
typedef struct
{
NSC_pFuncTypeDef NSC;
S_pFuncTypeDef S;
}RSSLIB_pFunc_TypeDef;
/** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */
@ -4580,21 +4510,21 @@ typedef struct
#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
/******************************************************************************/
/* */
@ -16364,11 +16294,13 @@ typedef struct
/****************** Bit definition for SYSCFG_RSSCMDR register **************/
#define SYSCFG_RSSCMDR_RSSCMD_Pos (0U)
#if defined(USE_CUT2_0)
#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */
#else
#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */
#endif
#define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */
#define SYSCFG_RSSCMDR_RSSCMD_BOOTLOADER ((uint16_t)0x01C0U)
/*****************************************************************************/
/* */
/* Global TrustZone Control */

View File

@ -478,7 +478,7 @@ typedef struct
} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU
* @brief Debug MCU - TODO review for STM32L5 to be done
*/
typedef struct
{
@ -486,7 +486,7 @@ typedef struct
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
@ -1757,88 +1757,22 @@ typedef struct
#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
/*!< Debug MCU registers base address */
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0044000UL)
#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */
#define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */
/*!< Internal Flash size */
/* Internal Flash size */
#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \
((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \
(((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U)))
/*!< OTP Area */
/* OTP Area */
#define OTP_BASE (0x0BFA0000UL)
#define OTP_SIZE (0x200U)
/*!< Bootloader Area */
#define BL_ID_ADDR (0x0BF97FFEUL) /*!< Bootloader ID address */
#define BL_ID (*(uint8_t*)BL_ID_ADDR) /*!< Bootloader ID */
/*!< Root Secure Service Library */
/************ RSSLIB SAU system Flash region definition constants *************/
#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF97F40UL)
#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF97FFFUL)
/************ RSSLIB function return constants ********************************/
#define RSSLIB_ERROR (0xF5F5F5F5UL)
#define RSSLIB_SUCCESS (0xEAEAEAEAUL)
/*!< RSSLIB pointer function structure address definition */
#define RSSLIB_PFUNC_BASE (0x0BF97F40UL)
#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
/*!< HDP Area constant definition */
#define RSSLIB_HDP_AREA_Pos (0U)
#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos )
#define RSSLIB_HDP_AREA1_Pos (0U)
#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos )
#define RSSLIB_HDP_AREA2_Pos (1U)
#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos )
/**
* @brief Prototype of RSSLIB Close and exit HDP Function
* @detail This function close the requested hdp area passed in input
* parameter and jump to the reset handler present within the
* Vector table. The function does not return on successful execution.
* @param HdpArea notifies which hdp area to close, can be a combination of
* hdpa area 1 and hdp area 2
* @param pointer on the vector table containing the reset handler the function
* jumps to.
* @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
*/
typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr );
/**
* @brief RSSLib non-secure callable function pointer structure
*/
typedef struct
{
__IM uint32_t Reserved[8];
}NSC_pFuncTypeDef;
/**
* @brief RSSLib secure callable function pointer structure
*/
typedef struct
{
__IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL90; /*!< RSSLIB Bootloader ID90 Close and exit HDP Address offset: 0x20 */
__IM uint32_t Reserved2;
__IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL91; /*!< RSSLIB Bootloader ID91 Close and exit HDP Address offset: 0x28 */
}S_pFuncTypeDef;
/**
* @brief RSSLib function pointer structure
*/
typedef struct
{
NSC_pFuncTypeDef NSC;
S_pFuncTypeDef S;
}RSSLIB_pFunc_TypeDef;
/** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */
@ -4908,21 +4842,21 @@ typedef struct
#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
/******************************************************************************/
/* */
@ -17099,11 +17033,13 @@ typedef struct
/****************** Bit definition for SYSCFG_RSSCMDR register **************/
#define SYSCFG_RSSCMDR_RSSCMD_Pos (0U)
#if defined(USE_CUT2_0)
#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */
#else
#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */
#endif
#define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */
#define SYSCFG_RSSCMDR_RSSCMD_BOOTLOADER ((uint16_t)0x01C0U)
/*****************************************************************************/
/* */
/* Global TrustZone Control */

View File

@ -79,7 +79,7 @@
*/
#define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32L5_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32L5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\

View File

@ -187,9 +187,6 @@ struct port_context {};
#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4) || (CORTEX_MODEL == 7)
#include "mpu.h"
#include "chcore_v7m.h"
#elif (CORTEX_MODEL == 33) || (CORTEX_MODEL == 55)
#include "mpu_v8m.h"
#include "chcore_v8m-mainline.h"
#else
#error "unknown Cortex-M variant"
#endif

View File

@ -1,694 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file chcore_v7m.h
* @brief ARMv7-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V7M_CORE
* @{
*/
#ifndef CHCORE_V8M_MAINLINE_H
#define CHCORE_V8M_MAINLINE_H
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name Port Capabilities and Constants
* @{
*/
/**
* @brief This port supports a realtime counter.
*/
#define PORT_SUPPORTS_RT TRUE
/**
* @brief Natural alignment constant.
* @note It is the minimum alignment for pointer-size variables.
*/
#define PORT_NATURAL_ALIGN sizeof (void *)
/**
* @brief Stack alignment constant.
* @note It is the alignment required for the stack pointer.
*/
#define PORT_STACK_ALIGN 32U
/**
* @brief Working Areas alignment constant.
* @note It is the alignment to be enforced for thread working areas.
*/
#define PORT_WORKING_AREA_ALIGN 32U
/** @} */
/**
* @brief Disabled value for BASEPRI register.
*/
#define CORTEX_BASEPRI_DISABLED 0U
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Implements a syscall interface on SVC.
*/
#if !defined(PORT_USE_SYSCALL) || defined(__DOXYGEN__)
#define PORT_USE_SYSCALL FALSE
#endif
/**
* @brief Number of MPU regions to be saved/restored during context switch.
* @note The first region is always region zero.
* @note The use of this option has an overhead of 8 bytes for each
* region for each thread.
* @note Allowed values are 0..4, zero means none.
*/
#if !defined(PORT_SWITCHED_REGIONS_NUMBER) || defined(__DOXYGEN__)
#define PORT_SWITCHED_REGIONS_NUMBER 0
#endif
/**
* @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
* by @p PORT_INT_REQUIRED_STACK.
* @note In this port it is set to 16 because the idle thread does have
* a stack frame when compiling without optimizations. You may
* reduce this value to zero when compiling with optimizations.
*/
#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* @note In this port this value is conservatively set to 64 because the
* function @p chSchDoReschedule() can have a stack frame, especially
* with compiler optimizations disabled. The value can be reduced
* when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
#define PORT_INT_REQUIRED_STACK 64
#endif
/**
* @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#if !defined(CORTEX_ENABLE_WFI_IDLE)
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
* @brief FPU support in context switch.
* @details Activating this option activates the FPU support in the kernel.
*/
#if !defined(CORTEX_USE_FPU)
#define CORTEX_USE_FPU CORTEX_HAS_FPU
#elif (CORTEX_USE_FPU == TRUE) && (CORTEX_HAS_FPU == FALSE)
/* This setting requires an FPU presence check in case it is externally
redefined.*/
#error "the selected core does not have an FPU"
#endif
/**
* @brief Simplified priority handling flag.
* @details Activating this option makes the Kernel work in compact mode.
* In compact mode interrupts are disabled globally instead of
* raising the priority mask to some intermediate level.
*/
#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
#define CORTEX_SIMPLIFIED_PRIORITY FALSE
#endif
/**
* @brief SVCALL handler priority.
* @note The default SVCALL handler priority is defaulted to
* @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
* @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
* priority level.
*/
#if !defined(CORTEX_PRIORITY_SVCALL)
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U)
#elif !PORT_IRQ_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
/* If it is externally redefined then better perform a validity check on it.*/
#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
#endif
/**
* @brief NVIC PRIGROUP initialization expression.
* @details The default assigns all available priority bits as preemption
* priority with no sub-priority.
*/
#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (PORT_SWITCHED_REGIONS_NUMBER < 0) || (PORT_SWITCHED_REGIONS_NUMBER > 4)
#error "invalid PORT_SWITCHED_REGIONS_NUMBER value"
#endif
/**
* @brief Macro defining the specific ARM architecture.
*/
#define PORT_ARCHITECTURE_ARM_V8M_MAINLINE
/**
* @brief Name of the implemented architecture.
*/
#define PORT_ARCHITECTURE_NAME "ARMv8-M Mainline"
/**
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == 33) || defined(__DOXYGEN__)
#if !defined(CH_CUSTOMER_LIC_PORT_CM33)
#error "CH_CUSTOMER_LIC_PORT_CM33 not defined"
#endif
#if CH_CUSTOMER_LIC_PORT_CM33 == FALSE
#error "ChibiOS Cortex-M33 port not licensed"
#endif
/**
* @brief Name of the architecture variant.
*/
#if CORTEX_USE_FPU || defined(__DOXYGEN__)
#define PORT_CORE_VARIANT_NAME "Cortex-M33 with FPU"
#else
#define PORT_CORE_VARIANT_NAME "Cortex-M33"
#endif
#elif (CORTEX_MODEL == 55) || defined(__DOXYGEN__)
#if !defined(CH_CUSTOMER_LIC_PORT_CM55)
#error "CH_CUSTOMER_LIC_PORT_CM55 not defined"
#endif
#if CH_CUSTOMER_LIC_PORT_CM55 == FALSE
#error "ChibiOS Cortex-M55 port not licensed"
#endif
/**
* @brief Name of the architecture variant.
*/
#if CORTEX_USE_FPU || defined(__DOXYGEN__)
#define PORT_CORE_VARIANT_NAME "Cortex-M55 with FPU"
#else
#define PORT_CORE_VARIANT_NAME "Cortex-M55"
#endif
#endif
/**
* @brief Port-specific information string.
*/
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
#define PORT_INFO "Advanced kernel mode"
#else
#define PORT_INFO "Compact kernel mode"
#endif
/** @} */
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
/**
* @brief Maximum usable priority for normal ISRs.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U)
/**
* @brief BASEPRI level within kernel lock.
*/
#define CORTEX_BASEPRI_KERNEL \
CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
#else
#define CORTEX_MAX_KERNEL_PRIORITY 0U
#endif
/**
* @brief PendSV priority level.
* @note This priority is enforced to be equal to
* @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
* highest priority that cannot preempt the kernel.
*/
#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/* The documentation of the following declarations is in chconf.h in order
to not have duplicated structure names into the documentation.*/
#if !defined(__DOXYGEN__)
struct port_extctx {
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r12;
uint32_t lr_thd;
uint32_t pc;
uint32_t xpsr;
#if CORTEX_USE_FPU
uint32_t s0;
uint32_t s1;
uint32_t s2;
uint32_t s3;
uint32_t s4;
uint32_t s5;
uint32_t s6;
uint32_t s7;
uint32_t s8;
uint32_t s9;
uint32_t s10;
uint32_t s11;
uint32_t s12;
uint32_t s13;
uint32_t s14;
uint32_t s15;
uint32_t fpscr;
uint32_t reserved;
#endif /* CORTEX_USE_FPU */
};
#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__)
/**
* @brief Link context structure.
* @details This structure is used when there is the need to save extra
* context information that is not part of the registers stacked
* in HW.
*/
struct port_linkctx {
uint32_t control;
struct port_extctx *ectxp;
};
#endif
struct port_intctx {
#if (PORT_SWITCHED_REGIONS_NUMBER > 0) || defined(__DOXYGEN__)
struct {
uint32_t rbar;
uint32_t rasr;
} regions[PORT_SWITCHED_REGIONS_NUMBER];
#endif
#if CORTEX_USE_FPU
uint32_t s16;
uint32_t s17;
uint32_t s18;
uint32_t s19;
uint32_t s20;
uint32_t s21;
uint32_t s22;
uint32_t s23;
uint32_t s24;
uint32_t s25;
uint32_t s26;
uint32_t s27;
uint32_t s28;
uint32_t s29;
uint32_t s30;
uint32_t s31;
#endif /* CORTEX_USE_FPU */
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
uint32_t r8;
uint32_t r9;
uint32_t r10;
uint32_t r11;
uint32_t lr;
};
struct port_context {
struct port_intctx *sp;
#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__)
struct {
uint32_t psp;
const void *p;
} syscall;
#endif
};
#endif /* !defined(__DOXYGEN__) */
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/* By default threads have no syscall context information.*/
#if (PORT_USE_SYSCALL == TRUE) || defined(__DOXYGEN__)
#define __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop) \
(tp)->ctx.syscall.psp = (uint32_t)(wtop); \
(tp)->ctx.syscall.p = NULL;
#else
#define __PORT_SETUP_CONTEXT_SYSCALL(tp, wtop)
#endif
/* By default threads have all regions disabled.*/
#if (PORT_SWITCHED_REGIONS_NUMBER == 0) || defined(__DOXYGEN__)
#define __PORT_SETUP_CONTEXT_MPU(tp)
#elif (PORT_SWITCHED_REGIONS_NUMBER == 1) || defined(__DOXYGEN__)
#define __PORT_SETUP_CONTEXT_MPU(tp) \
(tp)->ctx.sp->regions[0].rbar = 0U; \
(tp)->ctx.sp->regions[0].rasr = 0U
#elif (PORT_SWITCHED_REGIONS_NUMBER == 2) || defined(__DOXYGEN__)
#define __PORT_SETUP_CONTEXT_MPU(tp) \
(tp)->ctx.sp->regions[0].rbar = 0U; \
(tp)->ctx.sp->regions[0].rasr = 0U; \
(tp)->ctx.sp->regions[1].rbar = 0U; \
(tp)->ctx.sp->regions[1].rasr = 0U
#elif (PORT_SWITCHED_REGIONS_NUMBER == 3) || defined(__DOXYGEN__)
#define __PORT_SETUP_CONTEXT_MPU(tp) \
(tp)->ctx.sp->regions[0].rbar = 0U; \
(tp)->ctx.sp->regions[0].rasr = 0U; \
(tp)->ctx.sp->regions[1].rbar = 0U; \
(tp)->ctx.sp->regions[1].rasr = 0U; \
(tp)->ctx.sp->regions[2].rbar = 0U; \
(tp)->ctx.sp->regions[2].rasr = 0U
#elif (PORT_SWITCHED_REGIONS_NUMBER == 4) || defined(__DOXYGEN__)
#define __PORT_SETUP_CONTEXT_MPU(tp) \
(tp)->ctx.sp->regions[0].rbar = 0U; \
(tp)->ctx.sp->regions[0].rasr = 0U; \
(tp)->ctx.sp->regions[1].rbar = 0U; \
(tp)->ctx.sp->regions[1].rasr = 0U; \
(tp)->ctx.sp->regions[2].rbar = 0U; \
(tp)->ctx.sp->regions[2].rasr = 0U; \
(tp)->ctx.sp->regions[3].rbar = 0U; \
(tp)->ctx.sp->regions[3].rasr = 0U
#else
#endif
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p port_intctx structure.
*/
#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
sizeof (struct port_intctx)); \
(tp)->ctx.sp->r4 = (uint32_t)(pf); \
(tp)->ctx.sp->r5 = (uint32_t)(arg); \
(tp)->ctx.sp->lr = (uint32_t)_port_thread_start; \
__PORT_SETUP_CONTEXT_MPU(tp); \
__PORT_SETUP_CONTEXT_SYSCALL(tp, wtop); \
}
// __PORT_SETUP_CONTEXT_MPU(tp)
/**
* @brief Computes the thread working area global size.
* @note There is no need to perform alignments in this macro.
*/
#define PORT_WA_SIZE(n) (sizeof (struct port_intctx) + \
sizeof (struct port_extctx) + \
(size_t)(n) + \
(size_t)PORT_INT_REQUIRED_STACK)
/**
* @brief Static working area allocation.
* @details This macro is used to allocate a static thread working area
* aligned as both position and size.
*
* @param[in] s the name to be assigned to the stack array
* @param[in] n the stack size to be assigned to the thread
*/
#define PORT_WORKING_AREA(s, n) \
stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_PROLOGUE()
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#ifdef __cplusplus
#define PORT_IRQ_HANDLER(id) extern "C" void id(void)
#else
#define PORT_IRQ_HANDLER(id) void id(void)
#endif
/**
* @brief Fast IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#ifdef __cplusplus
#define PORT_FAST_IRQ_HANDLER(id) extern "C" void id(void)
#else
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
#endif
/**
* @brief Performs a context switch between two threads.
* @details This is the most critical code in any port, this function
* is responsible for the context switch between 2 threads.
* @note The implementation of this code affects <b>directly</b> the context
* switch performance so optimize here as much as you can.
*
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
if ((stkalign_t *)(r13 - 1) < (otp)->wabase) { \
chSysHalt("stack overflow"); \
} \
_port_switch(ntp, otp); \
}
#endif
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void port_init(void);
void _port_irq_epilogue(void);
void _port_switch(thread_t *ntp, thread_t *otp);
void _port_thread_start(void);
void _port_switch_from_isr(void);
void _port_exit_from_isr(void);
#if PORT_USE_SYSCALL == TRUE
void port_unprivileged_jump(uint32_t pc, uint32_t psp);
#endif
#ifdef __cplusplus
}
#endif
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
/**
* @brief Returns a word encoding the current interrupts status.
*
* @return The interrupts status.
*/
__STATIC_FORCEINLINE syssts_t port_get_irq_status(void) {
syssts_t sts;
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
sts = (syssts_t)__get_BASEPRI();
#else /* CORTEX_SIMPLIFIED_PRIORITY */
sts = (syssts_t)__get_PRIMASK();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
return sts;
}
/**
* @brief Checks the interrupt status.
*
* @param[in] sts the interrupt status word
*
* @return The interrupt status.
* @retval false the word specified a disabled interrupts status.
* @retval true the word specified an enabled interrupts status.
*/
__STATIC_FORCEINLINE bool port_irq_enabled(syssts_t sts) {
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
return sts == (syssts_t)CORTEX_BASEPRI_DISABLED;
#else /* CORTEX_SIMPLIFIED_PRIORITY */
return (sts & (syssts_t)1) == (syssts_t)0;
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
* @brief Determines the current execution context.
*
* @return The execution context.
* @retval false not running in ISR mode.
* @retval true running in ISR mode.
*/
__STATIC_FORCEINLINE bool port_is_isr_context(void) {
return (bool)((__get_IPSR() & 0x1FFU) != 0U);
}
/**
* @brief Kernel-lock action.
* @details In this port this function raises the base priority to kernel
* level.
*/
__STATIC_FORCEINLINE void port_lock(void) {
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
#else /* CORTEX_SIMPLIFIED_PRIORITY */
__disable_irq();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
* @brief Kernel-unlock action.
* @details In this port this function lowers the base priority to user
* level.
*/
__STATIC_FORCEINLINE void port_unlock(void) {
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
#else /* CORTEX_SIMPLIFIED_PRIORITY */
__enable_irq();
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
}
/**
* @brief Kernel-lock action from an interrupt handler.
* @details In this port this function raises the base priority to kernel
* level.
* @note Same as @p port_lock() in this port.
*/
__STATIC_FORCEINLINE void port_lock_from_isr(void) {
port_lock();
}
/**
* @brief Kernel-unlock action from an interrupt handler.
* @details In this port this function lowers the base priority to user
* level.
* @note Same as @p port_unlock() in this port.
*/
__STATIC_FORCEINLINE void port_unlock_from_isr(void) {
port_unlock();
}
/**
* @brief Disables all the interrupt sources.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
__STATIC_FORCEINLINE void port_disable(void) {
__disable_irq();
}
/**
* @brief Disables the interrupt sources below kernel-level priority.
* @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
__STATIC_FORCEINLINE void port_suspend(void) {
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
__enable_irq();
#else
__disable_irq();
#endif
}
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
__STATIC_FORCEINLINE void port_enable(void) {
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
#endif
__enable_irq();
}
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
* @details The function is meant to return when an interrupt becomes pending.
* The simplest implementation is an empty function or macro but this
* would not take advantage of architecture-specific power saving
* modes.
* @note Implemented as an inlined @p WFI instruction.
*/
__STATIC_FORCEINLINE void port_wait_for_interrupt(void) {
#if CORTEX_ENABLE_WFI_IDLE == TRUE
__WFI();
#endif
}
/**
* @brief Returns the current value of the realtime counter.
*
* @return The realtime counter value.
*/
__STATIC_FORCEINLINE rtcnt_t port_rt_get_counter_value(void) {
return DWT->CYCCNT;
}
#endif /* !defined(_FROM_ASM_) */
#endif /* CHCORE_V8M_MAINLINE_H */
/** @} */

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@ -1,196 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file chcore_v8m-mainline.c
* @brief ARMv7-M architecture port code.
*
* @addtogroup ARMCMx_V8M_MAINLINE_CORE
* @{
*/
#include <string.h>
#include "ch.h"
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Module local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Module interrupt handlers. */
/*===========================================================================*/
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)
/**
* @brief SVC vector.
* @details The SVC vector is used for exception mode re-entering after a
* context switch and, optionally, for system calls.
* @note The SVC vector is only used in advanced kernel mode.
*/
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
void SVC_Handler(void) {
/*lint -restore*/
uint32_t psp = __get_PSP();
{
/* From privileged mode, it is used for context discarding in the
preemption code.*/
/* Unstacking procedure, discarding the current exception context and
positioning the stack to point to the real one.*/
psp += sizeof (struct port_extctx);
#if CORTEX_USE_FPU == TRUE
/* Enforcing unstacking of the FP part of the context.*/
FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk;
#endif
/* Restoring real position of the original stack frame.*/
__set_PSP(psp);
/* Restoring the normal interrupts status.*/
port_unlock_from_isr();
}
}
#endif /* CORTEX_SIMPLIFIED_PRIORITY == FALSE */
#if (CORTEX_SIMPLIFIED_PRIORITY == TRUE) || defined(__DOXYGEN__)
/**
* @brief PendSV vector.
* @details The PendSV vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in compact kernel mode.
*/
/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
void PendSV_Handler(void) {
/*lint -restore*/
uint32_t psp = __get_PSP();
#if CORTEX_USE_FPU
/* Enforcing unstacking of the FP part of the context.*/
FPU->FPCCR &= ~FPU_FPCCR_LSPACT_Msk;
#endif
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
psp += sizeof (struct port_extctx);
/* Restoring real position of the original stack frame.*/
__set_PSP(psp);
}
#endif /* CORTEX_SIMPLIFIED_PRIORITY == TRUE */
/*===========================================================================*/
/* Module exported functions. */
/*===========================================================================*/
/**
* @brief Port-related initialization code.
*/
void port_init(void) {
/* Starting in a known IRQ configuration.*/
__set_BASEPRI(CORTEX_BASEPRI_DISABLED);
__enable_irq();
/* Initializing priority grouping.*/
NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT);
/* DWT cycle counter enable, note, the M7 requires DWT unlocking.*/
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
// DWT->LAR = 0xC5ACCE55U;
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
/* Initialization of the system vectors used by the port.*/
#if CORTEX_SIMPLIFIED_PRIORITY == FALSE
NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);
#endif
NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);
}
/**
* @brief Exception exit redirection to _port_switch_from_isr().
*/
void _port_irq_epilogue(void) {
port_lock_from_isr();
if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0U) {
struct port_extctx *ectxp;
uint32_t s_psp;
#if CORTEX_USE_FPU == TRUE
/* Enforcing a lazy FPU state save by accessing the FPCSR register.*/
(void) __get_FPSCR();
#endif
s_psp = __get_PSP();
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
s_psp -= sizeof (struct port_extctx);
/* The port_extctx structure is pointed by the S-PSP register.*/
ectxp = (struct port_extctx *)s_psp;
/* Setting up a fake XPSR register value.*/
ectxp->xpsr = 0x01000000U;
#if CORTEX_USE_FPU == TRUE
ectxp->fpscr = FPU->FPDSCR;
#endif
/* Writing back the modified S-PSP value.*/
__set_PSP(s_psp);
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsPreemptionRequired()) {
/* Preemption is required we need to enforce a context switch.*/
ectxp->pc = (uint32_t)_port_switch_from_isr;
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
ectxp->pc = (uint32_t)_port_exit_from_isr;
}
/* Note, returning without unlocking is intentional, this is done in
order to keep the rest of the context switch atomic.*/
return;
}
port_unlock_from_isr();
}
/** @} */

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@ -1,242 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file compilers/GCC/chcoreasm_v7m.S
* @brief ARMv7-M architecture port low level code.
*
* @addtogroup ARMCMx_GCC_CORE
* @{
*/
#if !defined(FALSE) || defined(__DOXYGEN__)
#define FALSE 0
#endif
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE 1
#endif
#define _FROM_ASM_
#include "chlicense.h"
#include "chconf.h"
#include "chcore.h"
#if !defined(__DOXYGEN__)
/*
* RTOS-specific context offset.
*/
#if defined(_CHIBIOS_RT_CONF_)
#define CONTEXT_OFFSET 12
#elif defined(_CHIBIOS_NIL_CONF_)
#define CONTEXT_OFFSET 0
#else
#error "invalid chconf.h"
#endif
/* MPU-related constants.*/
#define MPU_RBAR 0xE000ED9C
/* Other constants.*/
#define SCB_ICSR 0xE000ED04
#define ICSR_PENDSVSET 0x10000000
.syntax unified
.cpu cortex-m4
#if CORTEX_USE_FPU
.fpu fpv4-sp-d16
#else
.fpu softvfp
#endif
.thumb
.text
/*--------------------------------------------------------------------------*
* Performs a context switch between two threads.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_switch
_port_switch:
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
/* Saving FPU context.*/
vpush {s16-s31}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER > 0
/* Saving MPU context.*/
ldr r2, =MPU_RBAR
#if PORT_SWITCHED_REGIONS_NUMBER >= 1
mov r3, #0
str r3, [r2, #-4] /* RNR */
ldm r2, {r4, r5} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 2
add r3, #1
str r3, [r2, #-4] /* RNR */
ldm r2, {r6, r7} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 3
add r3, #1
str r3, [r2, #-4] /* RNR */
ldm r2, {r8, r9} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 4
add r3, #1
str r3, [r2, #-4] /* RNR */
ldm r2, {r10, r11} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 1
push {r4, r5}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 2
push {r4, r5, r6, r7}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 3
push {r4, r5, r6, r7, r8, r9}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 4
push {r4, r5, r6, r7, r8, r9, r10, r11}
#endif
#endif
str sp, [r1, #CONTEXT_OFFSET]
#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) && \
((CORTEX_MODEL == 3) || (CORTEX_MODEL == 4))
/* Workaround for ARM errata 752419, only applied if
condition exists for it to be triggered.*/
ldr r3, [r0, #CONTEXT_OFFSET]
mov sp, r3
#else
ldr sp, [r0, #CONTEXT_OFFSET]
#endif
#if PORT_SWITCHED_REGIONS_NUMBER > 0
/* Restoring MPU context.*/
#if PORT_SWITCHED_REGIONS_NUMBER == 1
pop {r4, r5}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 2
pop {r4, r5, r6, r7}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 3
pop {r4, r5, r6, r7, r8, r9}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER == 4
pop {r4, r5, r6, r7, r8, r9, r10, r11}
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 1
mov r3, #0
str r3, [r2, #-4] /* RNR */
stm r2, {r4, r5} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 2
add r3, #1
str r3, [r2, #-4] /* RNR */
stm r2, {r6, r7} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 3
add r3, #1
str r3, [r2, #-4] /* RNR */
stm r2, {r8, r9} /* RBAR, RASR */
#endif
#if PORT_SWITCHED_REGIONS_NUMBER >= 4
add r3, #1
str r3, [r2, #-4] /* RNR */
stm r2, {r10, r11} /* RBAR, RASR */
#endif
#endif
#if CORTEX_USE_FPU
/* Restoring FPU context.*/
vpop {s16-s31}
#endif
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
/*--------------------------------------------------------------------------*
* Start a thread by invoking its work function.
*
* Threads execution starts here, the code leaves the system critical zone
* and then jumps into the thread function passed in register R4. The
* register R5 contains the thread parameter. The function chThdExit() is
* called on thread function return.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_thread_start
_port_thread_start:
#if CH_DBG_ENABLE_STACK_CHECK && PORT_ENABLE_GUARD_PAGES
bl _port_set_region
#endif
#if CH_DBG_SYSTEM_STATE_CHECK
bl _dbg_check_unlock
#endif
#if CH_DBG_STATISTICS
bl _stats_stop_measure_crit_thd
#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
msr BASEPRI, r3
#endif
mov r0, r5
blx r4
movs r0, #0 /* MSG_OK */
bl chThdExit
_zombies: b _zombies
/*--------------------------------------------------------------------------*
* Post-IRQ switch code.
*
* Exception handlers return here for context switching.
*--------------------------------------------------------------------------*/
.thumb_func
.globl _port_switch_from_isr
_port_switch_from_isr:
#if CH_DBG_STATISTICS
bl _stats_start_measure_crit_thd
#endif
#if CH_DBG_SYSTEM_STATE_CHECK
bl _dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl _dbg_check_unlock
#endif
#if CH_DBG_STATISTICS
bl _stats_stop_measure_crit_thd
#endif
.globl _port_exit_from_isr
_port_exit_from_isr:
#if CORTEX_SIMPLIFIED_PRIORITY
movw r3, #:lower16:SCB_ICSR
movt r3, #:upper16:SCB_ICSR
mov r2, ICSR_PENDSVSET
str r2, [r3, #0]
cpsie i
#else /* !CORTEX_SIMPLIFIED_PRIORITY */
svc #0
#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
.L1: b .L1
#endif /* !defined(__DOXYGEN__) */
/** @} */

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@ -1,13 +0,0 @@
# List of the ChibiOS/RT ARMv8M-mainline generic port files.
PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \
$(CHIBIOS)/os/common/ports/ARMCMx/chcore_v8m_mainline.c
PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v8m-mainline.S
PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
# Shared variables
ALLXASMSRC += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

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@ -1,61 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file common/ARMCMx/mpu_v8m.h
* @brief ARMv8-M MPU support macros and structures.
*
* @addtogroup COMMON_ARMV8M_MPU
* @{
*/
#ifndef MPU_ARMV8M_H
#define MPU_ARMV8M_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* MPU_ARMV8M_H */
/** @} */

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@ -1,350 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file crt0_v7m.S
* @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
*
* @addtogroup ARMCMx_GCC_STARTUP_V7M
* @{
*/
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
#if !defined(FALSE) || defined(__DOXYGEN__)
#define FALSE 0
#endif
#if !defined(TRUE) || defined(__DOXYGEN__)
#define TRUE 1
#endif
#define CONTROL_MODE_PRIVILEGED 0
#define CONTROL_MODE_UNPRIVILEGED 1
#define CONTROL_USE_MSP 0
#define CONTROL_USE_PSP 2
#define CONTROL_FPCA 4
#define FPCCR_ASPEN (1 << 31)
#define FPCCR_LSPEN (1 << 30)
#define SCB_VTOR 0xE000ED08
#define SCB_CPACR 0xE000ED88
#define SCB_FPCCR 0xE000EF34
#define SCB_FPDSCR 0xE000EF3C
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Enforces initialization of MSP.
* @note This is required if the boot process is not reliable for whatever
* reason (bad ROMs, bad bootloaders, bad debuggers=.
*/
#if !defined(CRT0_FORCE_MSP_INIT) || defined(__DOXYGEN__)
#define CRT0_FORCE_MSP_INIT TRUE
#endif
/**
* @brief VTOR special register initialization.
* @details VTOR is initialized to point to the vectors table.
*/
#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
#define CRT0_VTOR_INIT TRUE
#endif
/**
* @brief FPU initialization switch.
*/
#if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
#if defined(CORTEX_USE_FPU) || defined(__DOXYGEN__)
#define CRT0_INIT_FPU CORTEX_USE_FPU
#else
#define CRT0_INIT_FPU FALSE
#endif
#endif
/**
* @brief Control special register initialization value.
* @details The system is setup to run in privileged mode using the PSP
* stack (dual stack mode).
*/
#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
CONTROL_MODE_PRIVILEGED)
#endif
/**
* @brief Core initialization switch.
*/
#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
#define CRT0_INIT_CORE TRUE
#endif
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
#define CRT0_STACKS_FILL_PATTERN 0x55555555
#endif
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
#define CRT0_INIT_STACKS TRUE
#endif
/**
* @brief DATA segment initialization switch.
*/
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
#define CRT0_INIT_DATA TRUE
#endif
/**
* @brief BSS segment initialization switch.
*/
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
#define CRT0_INIT_BSS TRUE
#endif
/**
* @brief RAM areas initialization switch.
*/
#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
#define CRT0_INIT_RAM_AREAS TRUE
#endif
/**
* @brief Constructors invocation switch.
*/
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_CONSTRUCTORS TRUE
#endif
/**
* @brief Destructors invocation switch.
*/
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_DESTRUCTORS TRUE
#endif
/**
* @brief FPU FPCCR register initialization value.
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
*/
#if !defined(CRT0_FPCCR_INIT) || defined(__DOXYGEN__)
#define CRT0_FPCCR_INIT (FPCCR_ASPEN | FPCCR_LSPEN)
#endif
/**
* @brief CPACR register initialization value.
* @note Only used if @p CRT0_INIT_FPU is equal to @p TRUE.
*/
#if !defined(CRT0_CPACR_INIT) || defined(__DOXYGEN__)
#define CRT0_CPACR_INIT 0x00F00000
#endif
/*===========================================================================*/
/* Code section. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
.syntax unified
.cpu cortex-m3
#if CRT0_INIT_FPU == TRUE
.fpu fpv4-sp-d16
#else
.fpu softvfp
#endif
.thumb
.text
/*
* CRT0 entry point.
*/
.align 2
.thumb_func
.global _crt0_entry
_crt0_entry:
/* Interrupts are globally masked initially.*/
cpsid i
#if CRT0_FORCE_MSP_INIT == TRUE
/* MSP stack pointers initialization.*/
ldr r0, =__main_stack_end__
msr MSP, r0
#endif
/* PSP stack pointers initialization.*/
ldr r0, =__process_stack_end__
msr PSP, r0
#if CRT0_VTOR_INIT == TRUE
ldr r0, =_vectors
movw r1, #SCB_VTOR & 0xFFFF
movt r1, #SCB_VTOR >> 16
str r0, [r1]
#endif
#if CRT0_INIT_FPU == TRUE
/* FPU FPCCR initialization.*/
movw r0, #CRT0_FPCCR_INIT & 0xFFFF
movt r0, #CRT0_FPCCR_INIT >> 16
movw r1, #SCB_FPCCR & 0xFFFF
movt r1, #SCB_FPCCR >> 16
str r0, [r1]
dsb
isb
/* CPACR initialization.*/
movw r0, #CRT0_CPACR_INIT & 0xFFFF
movt r0, #CRT0_CPACR_INIT >> 16
movw r1, #SCB_CPACR & 0xFFFF
movt r1, #SCB_CPACR >> 16
str r0, [r1]
dsb
isb
/* FPU FPSCR initially cleared.*/
mov r0, #0
vmsr FPSCR, r0
/* FPU FPDSCR initially cleared.*/
movw r1, #SCB_FPDSCR & 0xFFFF
movt r1, #SCB_FPDSCR >> 16
str r0, [r1]
/* Enforcing FPCA bit in the CONTROL register.*/
movs r0, #CRT0_CONTROL_INIT | CONTROL_FPCA
#else
movs r0, #CRT0_CONTROL_INIT
#endif
/* CONTROL register initialization as configured.*/
msr CONTROL, r0
isb
#if CRT0_INIT_CORE == TRUE
/* Core initialization.*/
bl __core_init
#endif
/* Early initialization.*/
bl __early_init
#if CRT0_INIT_STACKS == TRUE
ldr r0, =CRT0_STACKS_FILL_PATTERN
/* Main Stack initialization. Note, it assumes that the
stack size is a multiple of 4 so the linker file must
ensure this.*/
ldr r1, =__main_stack_base__
ldr r2, =__main_stack_end__
msloop:
cmp r1, r2
itt lo
strlo r0, [r1], #4
blo msloop
/* Process Stack initialization. Note, it assumes that the
stack size is a multiple of 4 so the linker file must
ensure this.*/
ldr r1, =__process_stack_base__
ldr r2, =__process_stack_end__
psloop:
cmp r1, r2
itt lo
strlo r0, [r1], #4
blo psloop
#endif
#if CRT0_INIT_DATA == TRUE
/* Data initialization. Note, it assumes that the DATA size
is a multiple of 4 so the linker file must ensure this.*/
ldr r1, =__textdata_base__
ldr r2, =__data_base__
ldr r3, =__data_end__
dloop:
cmp r2, r3
ittt lo
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo dloop
#endif
#if CRT0_INIT_BSS == TRUE
/* BSS initialization. Note, it assumes that the DATA size
is a multiple of 4 so the linker file must ensure this.*/
movs r0, #0
ldr r1, =__bss_base__
ldr r2, =__bss_end__
bloop:
cmp r1, r2
itt lo
strlo r0, [r1], #4
blo bloop
#endif
#if CRT0_INIT_RAM_AREAS == TRUE
/* RAM areas initialization.*/
bl __init_ram_areas
#endif
/* Late initialization..*/
bl __late_init
#if CRT0_CALL_CONSTRUCTORS == TRUE
/* Constructors invocation.*/
ldr r4, =__init_array_base__
ldr r5, =__init_array_end__
initloop:
cmp r4, r5
bge endinitloop
ldr r1, [r4], #4
blx r1
b initloop
endinitloop:
#endif
/* Main program invocation, r0 contains the returned value.*/
bl main
#if CRT0_CALL_DESTRUCTORS == TRUE
/* Destructors invocation.*/
ldr r4, =__fini_array_base__
ldr r5, =__fini_array_end__
finiloop:
cmp r4, r5
bge endfiniloop
ldr r1, [r4], #4
blx r1
b finiloop
endfiniloop:
#endif
/* Branching to the defined exit handler.*/
b __default_exit
#endif /* !defined(__DOXYGEN__) */
/** @} */

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@ -1,85 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32L4R9xI memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 2M
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
ram1 (wx) : org = 0x20000000, len = 192k /* SRAM1 */
ram2 (wx) : org = 0x00000000, len = 64k /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 384k /* SRAM3 */
ram4 (wx) : org = 0x10000000, len = 64k /* SRAM2 alias */
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

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@ -1,17 +0,0 @@
# List of the ChibiOS generic STM32L4xx startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-mainline.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L5xx \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS)/os/common/ext/ST/STM32L5xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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@ -62,7 +62,7 @@ _vectors:
.long MemManage_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long SecureFault_Handler
.long Vector1C
.long Vector20
.long Vector24
.long Vector28
@ -264,7 +264,7 @@ Reset_Handler:
.weak MemManage_Handler
.weak BusFault_Handler
.weak UsageFault_Handler
.weak SecureFault_Handler
.weak Vector1C
.weak Vector20
.weak Vector24
.weak Vector28
@ -463,7 +463,7 @@ BusFault_Handler:
.thumb_func
UsageFault_Handler:
.thumb_func
SecureFault_Handler:
Vector1C:
.thumb_func
Vector20:
.thumb_func

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@ -82,7 +82,7 @@ Reset_Handler PROC
isb
bl __early_init
IF {CPU} = "Cortex-M4.fp.sp"
IF {CPU} = "Cortex-M4.fp"
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1, [R0]
ORR R1, R1, #(0xF << 20)

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@ -1,88 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32L4xx/cmparams.h
* @brief ARM Cortex-M4 parameters for the STM32L4xx.
*
* @defgroup ARMCMx_STM32L4xx STM32L4xx Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M4 specific parameters for the
* STM32L4xx platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 33
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 1
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 4
/* If the device type is not externally defined, for example from the Makefile,
then a file named board.h is included. This file must contain a device
definition compatible with the vendor include file.*/
#if !defined(STM32L552xx) && !defined(STM32L562xx)
#include "board.h"
#endif
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 112
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "stm32l5xx.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_HAS_FPU != __FPU_PRESENT
#error "CMSIS __FPU_PRESENT mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

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@ -1,605 +0,0 @@
/*
ChibiOS - Copyright (C) 2016..2019 Rocco Marco Guglielmi
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file adxl355.c
* @brief ADXL355 MEMS interface module code.
*
* @addtogroup ADXL355
* @ingroup EX_ADI
* @{
*/
#include "hal.h"
#include "adxl355.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#if (ADXL355_USE_SPI) || defined(__DOXYGEN__)
/**
* @brief Reads a generic register value using SPI.
* @pre The SPI interface must be initialized and the driver started.
*
* @param[in] spip pointer to the SPI interface
* @param[in] reg starting register address
* @param[in] n number of consecutive registers to read
* @param[in] b pointer to an output buffer.
*/
static void adxl355SPIReadRegister(SPIDriver *spip, uint8_t reg, size_t n,
uint8_t* b) {
uint8_t cmd;
cmd = (reg << 1) | ADXL355_RW;
spiSelect(spip);
spiSend(spip, 1, &cmd);
spiReceive(spip, n, b);
spiUnselect(spip);
}
/**
* @brief Writes a value into a generic register using SPI.
* @pre The SPI interface must be initialized and the driver started.
*
* @param[in] spip pointer to the SPI interface
* @param[in] reg starting register address
* @param[in] n number of adjacent registers to write
* @param[in] b pointer to a buffer of values.
*/
static void adxl355SPIWriteRegister(SPIDriver *spip, uint8_t reg, size_t n,
uint8_t* b) {
uint8_t cmd;
cmd = (reg << 1);
spiSelect(spip);
spiSend(spip, 1, &cmd);
spiSend(spip, n, b);
spiUnselect(spip);
}
#endif /* ADXL355_USE_SPI */
/**
* @brief Return the number of axes of the BaseAccelerometer.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
*
* @return the number of axes.
*/
static size_t acc_get_axes_number(void *ip) {
(void)ip;
return ADXL355_ACC_NUMBER_OF_AXES;
}
/**
* @brief Retrieves raw data from the BaseAccelerometer.
* @note This data is retrieved from MEMS register without any algebraical
* manipulation.
* @note The axes array must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
* @param[out] axes a buffer which would be filled with raw data.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
* @retval MSG_TIMEOUT if a timeout occurred before operation end.
*/
static msg_t acc_read_raw(void *ip, int32_t axes[]) {
ADXL355Driver* devp;
uint8_t buff [ADXL355_ACC_NUMBER_OF_AXES * 3], i;
int32_t tmp;
msg_t msg = MSG_OK;
osalDbgCheck((ip != NULL) && (axes != NULL));
/* Getting parent instance pointer.*/
devp = objGetInstance(ADXL355Driver*, (BaseAccelerometer*)ip);
osalDbgAssert((devp->state == ADXL355_READY),
"acc_read_raw(), invalid state");
#if ADXL355_USE_SPI
#if ADXL355_SHARED_SPI
osalDbgAssert((devp->config->spip->state == SPI_READY),
"acc_read_raw(), channel not ready");
spiAcquireBus(devp->config->spip);
spiStart(devp->config->spip,
devp->config->spicfg);
#endif /* ADXL355_SHARED_SPI */
adxl355SPIReadRegister(devp->config->spip, ADXL355_AD_XDATA3,
ADXL355_ACC_NUMBER_OF_AXES * 3, buff);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++) {
tmp = (buff[3 * i] << 12) | (buff[3 * i + 1] << 4) | (buff[3 * i + 2] >> 4);
if(tmp & 0x80000) {
tmp |= 0xFFF00000U;
}
axes[i] = tmp;
}
return msg;
}
/**
* @brief Retrieves cooked data from the BaseAccelerometer.
* @note This data is manipulated according to the formula
* cooked = (raw * sensitivity) - bias.
* @note Final data is expressed as milli-G.
* @note The axes array must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
* @param[out] axes a buffer which would be filled with cooked data.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
* @retval MSG_TIMEOUT if a timeout occurred before operation end.
*/
static msg_t acc_read_cooked(void *ip, float axes[]) {
ADXL355Driver* devp;
uint32_t i;
int32_t raw[ADXL355_ACC_NUMBER_OF_AXES];
msg_t msg;
osalDbgCheck((ip != NULL) && (axes != NULL));
/* Getting parent instance pointer.*/
devp = objGetInstance(ADXL355Driver*, (BaseAccelerometer*)ip);
osalDbgAssert((devp->state == ADXL355_READY),
"acc_read_cooked(), invalid state");
msg = acc_read_raw(ip, raw);
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++) {
axes[i] = (raw[i] * devp->accsensitivity[i]) - devp->accbias[i];
}
return msg;
}
/**
* @brief Set bias values for the BaseAccelerometer.
* @note Bias must be expressed as milli-G.
* @note The bias buffer must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
* @param[in] bp a buffer which contains biases.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
*/
static msg_t acc_set_bias(void *ip, float *bp) {
ADXL355Driver* devp;
uint32_t i;
msg_t msg = MSG_OK;
osalDbgCheck((ip != NULL) && (bp != NULL));
/* Getting parent instance pointer.*/
devp = objGetInstance(ADXL355Driver*, (BaseAccelerometer*)ip);
osalDbgAssert((devp->state == ADXL355_READY),
"acc_set_bias(), invalid state");
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++) {
devp->accbias[i] = bp[i];
}
return msg;
}
/**
* @brief Reset bias values for the BaseAccelerometer.
* @note Default biases value are obtained from device datasheet when
* available otherwise they are considered zero.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
*/
static msg_t acc_reset_bias(void *ip) {
ADXL355Driver* devp;
uint32_t i;
msg_t msg = MSG_OK;
osalDbgCheck(ip != NULL);
/* Getting parent instance pointer.*/
devp = objGetInstance(ADXL355Driver*, (BaseAccelerometer*)ip);
osalDbgAssert((devp->state == ADXL355_READY),
"acc_reset_bias(), invalid state");
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accbias[i] = ADXL355_ACC_BIAS;
return msg;
}
/**
* @brief Set sensitivity values for the BaseAccelerometer.
* @note Sensitivity must be expressed as milli-G/LSB.
* @note The sensitivity buffer must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
* @param[in] sp a buffer which contains sensitivities.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
*/
static msg_t acc_set_sensivity(void *ip, float *sp) {
ADXL355Driver* devp;
uint32_t i;
msg_t msg = MSG_OK;
/* Getting parent instance pointer.*/
devp = objGetInstance(ADXL355Driver*, (BaseAccelerometer*)ip);
osalDbgCheck((ip != NULL) && (sp != NULL));
osalDbgAssert((devp->state == ADXL355_READY),
"acc_set_sensivity(), invalid state");
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++) {
devp->accsensitivity[i] = sp[i];
}
return msg;
}
/**
* @brief Reset sensitivity values for the BaseAccelerometer.
* @note Default sensitivities value are obtained from device datasheet.
*
* @param[in] ip pointer to @p BaseAccelerometer interface.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET otherwise.
*/
static msg_t acc_reset_sensivity(void *ip) {
ADXL355Driver* devp;
uint32_t i;
msg_t msg = MSG_OK;
osalDbgCheck(ip != NULL);
/* Getting parent instance pointer.*/
devp = objGetInstance(ADXL355Driver*, (BaseAccelerometer*)ip);
osalDbgAssert((devp->state == ADXL355_READY),
"acc_reset_sensivity(), invalid state");
if(devp->config->accfullscale == ADXL355_ACC_FS_2G)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = ADXL355_ACC_SENS_2G;
else if(devp->config->accfullscale == ADXL355_ACC_FS_4G)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = ADXL355_ACC_SENS_4G;
else if(devp->config->accfullscale == ADXL355_ACC_FS_8G)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = ADXL355_ACC_SENS_8G;
else {
osalDbgAssert(FALSE,
"acc_reset_sensivity(), accelerometer full scale issue");
return MSG_RESET;
}
return msg;
}
/**
* @brief Changes the ADXL355Driver accelerometer fullscale value.
* @note This function also rescale sensitivities and biases based on
* previous and next fullscale value.
* @note A recalibration is highly suggested after calling this function.
*
* @param[in] devp pointer to @p ADXL355Driver interface.
* @param[in] fs new fullscale value.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET otherwise.
*/
static msg_t acc_set_full_scale(ADXL355Driver *devp, adxl355_acc_fs_t fs) {
float newfs, scale;
uint8_t i, reg_val;
msg_t msg;
osalDbgCheck(devp != NULL);
osalDbgAssert((devp->state == ADXL355_READY),
"acc_set_full_scale(), invalid state");
osalDbgAssert((devp->config->spip->state == SPI_READY),
"acc_set_full_scale(), channel not ready");
/* Computing new fullscale value.*/
if(fs == ADXL355_ACC_FS_2G) {
newfs = ADXL355_ACC_2G;
}
else if(fs == ADXL355_ACC_FS_4G) {
newfs = ADXL355_ACC_4G;
}
else if(fs == ADXL355_ACC_FS_8G) {
newfs = ADXL355_ACC_8G;
}
else {
msg = MSG_RESET;
return msg;
}
if(newfs != devp->accfullscale) {
/* Computing scale value.*/
scale = newfs / devp->accfullscale;
devp->accfullscale = newfs;
#if ADXL355_USE_SPI
#if ADXL355_SHARED_SPI
spiAcquireBus(devp->config->spip);
spiStart(devp->config->spip,
devp->config->spicfg);
#endif /* ADXL355_SHARED_SPI */
/* Getting data from register.*/
adxl355SPIReadRegister(devp->config->spip, ADXL355_AD_RANGE, 1, &reg_val);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
reg_val &= ~(ADXL355_RANGE_RANGE_MASK);
reg_val |= fs;
#if ADXL355_USE_SPI
#if ADXL355_SHARED_SPI
spiAcquireBus(devp->config->spip);
spiStart(devp->config->spip,
devp->config->spicfg);
#endif /* ADXL355_SHARED_SPI */
/* Getting data from register.*/
adxl355SPIWriteRegister(devp->config->spip, ADXL355_AD_RANGE, 1, &reg_val);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
/* Scaling sensitivity and bias. Re-calibration is suggested anyway. */
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++) {
devp->accsensitivity[i] *= scale;
devp->accbias[i] *= scale;
}
}
return msg;
}
static const struct ADXL355VMT vmt_device = {
(size_t)0,
acc_set_full_scale
};
static const struct BaseAccelerometerVMT vmt_accelerometer = {
sizeof(struct ADXL355VMT*),
acc_get_axes_number, acc_read_raw, acc_read_cooked,
acc_set_bias, acc_reset_bias, acc_set_sensivity, acc_reset_sensivity
};
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Initializes an instance.
*
* @param[out] devp pointer to the @p ADXL355Driver object
*
* @init
*/
void adxl355ObjectInit(ADXL355Driver *devp) {
devp->vmt = &vmt_device;
devp->acc_if.vmt = &vmt_accelerometer;
devp->config = NULL;
devp->accaxes = ADXL355_ACC_NUMBER_OF_AXES;
devp->state = ADXL355_STOP;
}
/**
* @brief Configures and activates ADXL355 Complex Driver peripheral.
*
* @param[in] devp pointer to the @p ADXL355Driver object
* @param[in] config pointer to the @p ADXL355Config object
*
* @api
*/
void adxl355Start(ADXL355Driver *devp, const ADXL355Config *config) {
uint32_t i;
uint8_t reg_val;
osalDbgCheck((devp != NULL) && (config != NULL));
osalDbgAssert((devp->state == ADXL355_STOP) ||
(devp->state == ADXL355_READY),
"adxl355Start(), invalid state");
devp->config = config;
/* Range register configuration block.*/
{
reg_val = ADXL355_RANGE_I2C_HS | devp->config->accfullscale;
#if ADXL355_USE_SPI
#if ADXL355_SHARED_SPI
spiAcquireBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
spiStart(devp->config->spip, devp->config->spicfg);
adxl355SPIWriteRegister(devp->config->spip, ADXL355_AD_RANGE, 1, &reg_val);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
}
/* Filter register configuration block.*/
{
reg_val = devp->config->accoutputdatarate;
#if ADXL355_USE_ADVANCED || defined(__DOXYGEN__)
reg_val |= devp->config->acchighpass;
#endif
#if ADXL355_USE_SPI
#if ADXL355_SHARED_SPI
spiAcquireBus(devp->config->spip);
spiStart(devp->config->spip, devp->config->spicfg);
#endif /* ADXL355_SHARED_SPI */
adxl355SPIWriteRegister(devp->config->spip, ADXL355_AD_FILTER, 1, &reg_val);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
}
/* Power control configuration block.*/
{
reg_val = 0;
#if ADXL355_USE_SPI
#if ADXL355_SHARED_SPI
spiAcquireBus(devp->config->spip);
spiStart(devp->config->spip, devp->config->spicfg);
#endif /* ADXL355_SHARED_SPI */
adxl355SPIWriteRegister(devp->config->spip, ADXL355_AD_POWER_CTL, 1, &reg_val);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
}
/* Storing sensitivity information according to user setting */
if(devp->config->accfullscale == ADXL355_ACC_FS_2G) {
devp->accfullscale = ADXL355_ACC_2G;
if(devp->config->accsensitivity == NULL)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = ADXL355_ACC_SENS_2G;
else
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = devp->config->accsensitivity[i];
}
else if(devp->config->accfullscale == ADXL355_ACC_FS_4G) {
devp->accfullscale = ADXL355_ACC_4G;
if(devp->config->accsensitivity == NULL)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = ADXL355_ACC_SENS_4G;
else
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = devp->config->accsensitivity[i];
}
else if(devp->config->accfullscale == ADXL355_ACC_FS_8G) {
devp->accfullscale = ADXL355_ACC_8G;
if(devp->config->accsensitivity == NULL)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = ADXL355_ACC_SENS_8G;
else
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accsensitivity[i] = devp->config->accsensitivity[i];
}
else {
osalDbgAssert(FALSE, "adxl355Start(), accelerometer full scale issue");
}
/* Storing bias information according to user setting */
if(devp->config->accbias != NULL)
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accbias[i] = devp->config->accbias[i];
else
for(i = 0; i < ADXL355_ACC_NUMBER_OF_AXES; i++)
devp->accbias[i] = ADXL355_ACC_BIAS;
/* This is the Accelerometer transient recovery time */
osalThreadSleepMilliseconds(10);
devp->state = ADXL355_READY;
}
/**
* @brief Deactivates the ADXL355 Complex Driver peripheral.
*
* @param[in] devp pointer to the @p ADXL355Driver object
*
* @api
*/
void adxl355Stop(ADXL355Driver *devp) {
uint8_t reg_val;
osalDbgCheck(devp != NULL);
osalDbgAssert((devp->state == ADXL355_STOP) ||
(devp->state == ADXL355_READY),
"adxl355Stop(), invalid state");
if (devp->state == ADXL355_READY) {
#if (ADXL355_USE_SPI)
#if ADXL355_SHARED_SPI
spiAcquireBus(devp->config->spip);
spiStart(devp->config->spip,
devp->config->spicfg);
#endif /* ADXL355_SHARED_SPI */
/* Disabling all axes and enabling power down mode.*/
reg_val = 1;
adxl355SPIWriteRegister(devp->config->spip, ADXL355_AD_POWER_CTL,
1, &reg_val);
spiStop(devp->config->spip);
#if ADXL355_SHARED_SPI
spiReleaseBus(devp->config->spip);
#endif /* ADXL355_SHARED_SPI */
#endif /* ADXL355_USE_SPI */
}
devp->state = ADXL355_STOP;
}
/** @} */

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@ -1,633 +0,0 @@
/*
ChibiOS - Copyright (C) 2016..2019 Rocco Marco Guglielmi
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file adxl355.h
* @brief ADXL355 MEMS interface module header.
*
* @addtogroup ADXL355
* @ingroup EX_ADI
* @{
*/
#ifndef _ADXL355_H_
#define _ADXL355_H_
#include "ex_accelerometer.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name Version identification
* @{
*/
/**
* @brief ADXL355 driver version string.
*/
#define EX_ADXL355_VERSION "1.0.0"
/**
* @brief ADXL355 driver version major number.
*/
#define EX_ADXL355_MAJOR 1
/**
* @brief ADXL355 driver version minor number.
*/
#define EX_ADXL355_MINOR 0
/**
* @brief ADXL355 driver version patch number.
*/
#define EX_ADXL355_PATCH 0
/** @} */
/**
* @brief ADXL355 accelerometer subsystem characteristics.
* @note Sensitivity is expressed as milli-G/LSB whereas
* 1 milli-G = 0.00980665 m/s^2.
* @note Bias is expressed as milli-G.
*
* @{
*/
#define ADXL355_ACC_NUMBER_OF_AXES 3U
#define ADXL355_ACC_2G 2.048f
#define ADXL355_ACC_4G 4.096f
#define ADXL355_ACC_8G 8.0192f
#define ADXL355_ACC_SENS_2G 0.003906f
#define ADXL355_ACC_SENS_4G 0.007813f
#define ADXL355_ACC_SENS_8G 0.015625f
#define ADXL355_ACC_BIAS 0.0f
/** @} */
/**
* @name ADXL355 communication interfaces related bit masks
* @{
*/
#define ADXL355_DI_MASK 0xFF
#define ADXL355_DI(n) (1 << n)
#define ADXL355_AD_MASK 0xFE
#define ADXL355_RW (1 << 0)
#define ADXL355_AD(n) (1 << (n + 1))
/** @} */
/**
* @name ADXL355 register addresses
* @{
*/
#define ADXL355_AD_DEVID_AD 0x00
#define ADXL355_AD_DEVID_MST 0x01
#define ADXL355_AD_PARTID 0x02
#define ADXL355_AD_REVID 0x03
#define ADXL355_AD_STATUS 0x04
#define ADXL355_AD_FIFO_ENTRIES 0x05
#define ADXL355_AD_TEMP2 0x06
#define ADXL355_AD_TEMP1 0x07
#define ADXL355_AD_XDATA3 0x08
#define ADXL355_AD_XDATA2 0x09
#define ADXL355_AD_XDATA1 0x0A
#define ADXL355_AD_YDATA3 0x0B
#define ADXL355_AD_YDATA2 0x0C
#define ADXL355_AD_YDATA1 0x0D
#define ADXL355_AD_ZDATA3 0x0E
#define ADXL355_AD_ZDATA2 0x0F
#define ADXL355_AD_ZDATA1 0x10
#define ADXL355_AD_FIFO_DATA 0x11
#define ADXL355_AD_OFFSET_X_H 0x1E
#define ADXL355_AD_OFFSET_X_L 0x1F
#define ADXL355_AD_OFFSET_Y_H 0x20
#define ADXL355_AD_OFFSET_Y_L 0x21
#define ADXL355_AD_OFFSET_Z_H 0x22
#define ADXL355_AD_OFFSET_Z_L 0x23
#define ADXL355_AD_ACT_EN 0x24
#define ADXL355_AD_ACT_THRES_L 0x25
#define ADXL355_AD_ACT_THRES_H 0x26
#define ADXL355_AD_ACT_COUNTER 0x27
#define ADXL355_AD_FILTER 0x28
#define ADXL355_AD_FIFO_SAMPLES 0x29
#define ADXL355_AD_INT_MAP 0x2A
#define ADXL355_AD_SYNC 0x2B
#define ADXL355_AD_RANGE 0x2C
#define ADXL355_AD_POWER_CTL 0x2D
#define ADXL355_AD_SELF_TEST 0x2E
#define ADXL355_AD_RESET 0x2F
/** @} */
/**
* @name ADXL355_FILTER register bits definitions
* @{
*/
#define ADXL355_FILTER_MASK 0x7F
#define ADXL355_FILTER_ORD_LPF_0 (1 << 0)
#define ADXL355_FILTER_ORD_LPF_1 (1 << 1)
#define ADXL355_FILTER_ORD_LPF_2 (1 << 2)
#define ADXL355_FILTER_ORD_LPF_3 (1 << 3)
#define ADXL355_FILTER_HPF_CORNER_0 (1 << 4)
#define ADXL355_FILTER_HPF_CORNER_1 (1 << 5)
#define ADXL355_FILTER_HPF_CORNER_2 (1 << 6)
/** @} */
/**
* @name ADXL355_FIFO_SAMPLES register bits definitions
* @{
*/
#define ADXL355_FIFO_SAMPLES_MASK 0x7F
#define ADXL355_FIFO_SAMPLES_BIT_0 (1 << 0)
#define ADXL355_FIFO_SAMPLES_BIT_1 (1 << 1)
#define ADXL355_FIFO_SAMPLES_BIT_2 (1 << 2)
#define ADXL355_FIFO_SAMPLES_BIT_3 (1 << 3)
#define ADXL355_FIFO_SAMPLES_BIT_4 (1 << 4)
#define ADXL355_FIFO_SAMPLES_BIT_5 (1 << 5)
#define ADXL355_FIFO_SAMPLES_BIT_6 (1 << 6)
/** @} */
/**
* @name ADXL355_INT_MAP register bits definitions
* @{
*/
#define ADXL355_INT_MAP_MASK 0xFF
#define ADXL355_INT_MAP_RDY_EN1 (1 << 0)
#define ADXL355_INT_MAP_FULL_EN1 (1 << 1)
#define ADXL355_INT_MAP_OVR_EN1 (1 << 2)
#define ADXL355_INT_MAP_ACT_EN1 (1 << 3)
#define ADXL355_INT_MAP_RDY_EN2 (1 << 4)
#define ADXL355_INT_MAP_FULL_EN2 (1 << 5)
#define ADXL355_INT_MAP_OVR_EN2 (1 << 6)
#define ADXL355_INT_MAP_ACT_EN2 (1 << 7)
/** @} */
/**
* @name ADXL355_SYNC register bits definitions
* @{
*/
#define ADXL355_SYNC_MASK 0x07
#define ADXL355_SYNC_EXT_SYNC_0 (1 << 0)
#define ADXL355_SYNC_EXT_SYNC_1 (1 << 1)
#define ADXL355_SYNC_EXT_CLK (1 << 2)
/** @} */
/**
* @name ADXL355_RANGE register bits definitions
* @{
*/
#define ADXL355_RANGE_MASK 0xC3
#define ADXL355_RANGE_RANGE_MASK 0x03
#define ADXL355_RANGE_RANGE_1 (1 << 1)
#define ADXL355_RANGE_RANGE_0 (1 << 0)
#define ADXL355_RANGE_RANGE_1 (1 << 1)
#define ADXL355_RANGE_INT_POL (1 << 6)
#define ADXL355_RANGE_I2C_HS (1 << 7)
/** @} */
/**
* @name ADXL355_POWER_CTL register bits definitions
* @{
*/
#define ADXL355_POWER_CTL_MASK 0x07
#define ADXL355_POWER_CTL_STANDBY (1 << 0)
#define ADXL355_POWER_CTL_TEMP_OFF (1 << 1)
#define ADXL355_POWER_CTL_DRDY_OFF (1 << 2)
/** @} */
/**
* @name ADXL355_SELT_TEST register bits definitions
* @{
*/
#define ADXL355_SELF_TEST_MASK 0x03
#define ADXL355_SELF_TEST_ST1 (1 << 0)
#define ADXL355_SELF_TEST_ST2 (1 << 1)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief ADXL355 SPI interface switch.
* @details If set to @p TRUE the support for SPI is included.
* @note The default is @p TRUE.
*/
#if !defined(ADXL355_USE_SPI) || defined(__DOXYGEN__)
#define ADXL355_USE_SPI TRUE
#endif
/**
* @brief ADXL355 shared SPI switch.
* @details If set to @p TRUE the device acquires SPI bus ownership
* on each transaction.
* @note The default is @p FALSE. Requires SPI_USE_MUTUAL_EXCLUSION.
*/
#if !defined(ADXL355_SHARED_SPI) || defined(__DOXYGEN__)
#define ADXL355_SHARED_SPI FALSE
#endif
/**
* @brief ADXL355 I2C interface switch.
* @details If set to @p TRUE the support for I2C is included.
* @note The default is @p FALSE.
*/
#if !defined(ADXL355_USE_I2C) || defined(__DOXYGEN__)
#define ADXL355_USE_I2C FALSE
#endif
/**
* @brief ADXL355 shared I2C switch.
* @details If set to @p TRUE the device acquires I2C bus ownership
* on each transaction.
* @note The default is @p FALSE. Requires I2C_USE_MUTUAL_EXCLUSION.
*/
#if !defined(ADXL355_SHARED_I2C) || defined(__DOXYGEN__)
#define ADXL355_SHARED_I2C FALSE
#endif
/**
* @brief ADXL355 advanced configurations switch.
* @details If set to @p TRUE more configurations are available.
* @note The default is @p FALSE.
*/
#if !defined(ADXL355_USE_ADVANCED) || defined(__DOXYGEN__)
#define ADXL355_USE_ADVANCED FALSE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !(ADXL355_USE_SPI ^ ADXL355_USE_I2C)
#error "ADXL355_USE_SPI and ADXL355_USE_I2C cannot be both true or both false"
#endif
#if ADXL355_USE_SPI && !HAL_USE_SPI
#error "ADXL355_USE_SPI requires HAL_USE_SPI"
#endif
#if ADXL355_SHARED_SPI && !SPI_USE_MUTUAL_EXCLUSION
#error "ADXL355_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION"
#endif
#if ADXL355_USE_I2C && !HAL_USE_I2C
#error "ADXL355_USE_I2C requires HAL_USE_I2C"
#endif
#if ADXL355_SHARED_I2C && !I2C_USE_MUTUAL_EXCLUSION
#error "ADXL355_SHARED_I2C requires I2C_USE_MUTUAL_EXCLUSION"
#endif
/*
* CHTODO: Add support for ADXL355 over I2C.
*/
#if ADXL355_USE_I2C
#error "ADXL355 over I2C still not supported"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @name ADXL355 data structures and types
* @{
*/
/**
* @brief Structure representing a ADXL355 driver.
*/
typedef struct ADXL355Driver ADXL355Driver;
/**
* @brief ADXL355 full scale.
*/
typedef enum {
ADXL355_ACC_FS_2G = 0x01, /**< Full scale ±2g. */
ADXL355_ACC_FS_4G = 0x02, /**< Full scale ±4g. */
ADXL355_ACC_FS_8G = 0x03, /**< Full scale ±8g. */
}adxl355_acc_fs_t;
/**
* @brief ADXL355 output data rate.
*/
typedef enum {
ADXL355_ACC_ODR_4000HZ = 0x00, /**< ODR 4000 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_2000HZ = 0x01, /**< ODR 2000 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_1000HZ = 0x02, /**< ODR 1000 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_500HZ = 0x03, /**< ODR 500 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_250HZ = 0x04, /**< ODR 250 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_125HZ = 0x06, /**< ODR 125 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_62P5HZ = 0x06, /**< ODR 62.5 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_31P25HZ = 0x07, /**< ODR 31.25 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_15P625HZ = 0x08, /**< ODR 15.625 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_7P913HZ = 0x09, /**< ODR 7.913 Hz, LP cut-off ODR/4. */
ADXL355_ACC_ODR_3P906HZ = 0x0A /**< ODR 3.906 Hz, LP cut-off ODR/4. */
}adxl355_acc_odr_t;
/**
* @brief ADXL355 HP filter.
*/
typedef enum {
ADXL355_ACC_HP_DISABLED = 0x00, /**< HP disabled. */
ADXL355_ACC_HP_LEV_1 = 0x10, /**< HP cut-off 247 x 10^-3 x ODR. */
ADXL355_ACC_HP_LEV_2 = 0x20, /**< HP cut-off 62.084 x 10^-3 x ODR. */
ADXL355_ACC_HP_LEV_3 = 0x30, /**< HP cut-off 15.545 x 10^-3 x ODR. */
ADXL355_ACC_HP_LEV_4 = 0x40, /**< HP cut-off 3.892 x 10^-3 x ODR. */
ADXL355_ACC_HP_LEV_5 = 0x50, /**< HP cut-off 0.954 x 10^-3 x ODR. */
ADXL355_ACC_HP_LEV_6 = 0x60, /**< HP cut-off 0.238 x 10^-3 x ODR. */
}adxl355_acc_hp_t;
/**
* @brief Driver state machine possible states.
*/
typedef enum {
ADXL355_UNINIT = 0, /**< Not initialized. */
ADXL355_STOP = 1, /**< Stopped. */
ADXL355_READY = 2, /**< Ready. */
} adxl355_state_t;
/**
* @brief ADXL355 configuration structure.
*/
typedef struct {
#if (ADXL355_USE_SPI) || defined(__DOXYGEN__)
/**
* @brief SPI driver associated to this ADXL355.
*/
SPIDriver *spip;
/**
* @brief SPI configuration associated to this ADXL355.
*/
const SPIConfig *spicfg;
#endif /* ADXL355_USE_SPI */
#if (ADXL355_USE_I2C) || defined(__DOXYGEN__)
/**
* @brief I2C driver associated to this ADXL355.
*/
I2CDriver *i2cp;
/**
* @brief I2C configuration associated to this ADXL355.
*/
const I2CConfig *i2ccfg;
#endif /* ADXL355_USE_I2C */
/**
* @brief ADXL355 accelerometer subsystem initial sensitivity.
*/
float *accsensitivity;
/**
* @brief ADXL355 accelerometer subsystem initial bias.
*/
float *accbias;
/**
* @brief ADXL355 accelerometer subsystem initial full scale.
*/
adxl355_acc_fs_t accfullscale;
/**
* @brief ADXL355 output data rate selection.
*/
adxl355_acc_odr_t accoutputdatarate;
#if ADXL355_USE_ADVANCED || defined(__DOXYGEN__)
/**
* @brief ADXL355 HP filter bandwidth.
*/
adxl355_acc_hp_t acchighpass;
#endif
} ADXL355Config;
/**
* @brief @p ADXL355 specific methods.
*/
#define _adxl355_methods_alone \
/* Change full scale value of ADXL355 accelerometer subsystem.*/ \
msg_t (*acc_set_full_scale)(ADXL355Driver *devp, adxl355_acc_fs_t fs);
/**
* @brief @p ADXL355 specific methods with inherited ones.
*/
#define _adxl355_methods \
_base_object_methods \
_adxl355_methods_alone
/**
* @extends BaseObjectVMT
*
* @brief @p ADXL355 virtual methods table.
*/
struct ADXL355VMT {
_adxl355_methods
};
/**
* @brief @p ADXL355Driver specific data.
*/
#define _adxl355_data \
_base_sensor_data \
/* Driver state.*/ \
adxl355_state_t state; \
/* Current configuration data.*/ \
const ADXL355Config *config; \
/* Accelerometer subsystem axes number.*/ \
size_t accaxes; \
/* Accelerometer subsystem current sensitivity.*/ \
float accsensitivity[ADXL355_ACC_NUMBER_OF_AXES]; \
/* Accelerometer subsystem current bias .*/ \
float accbias[ADXL355_ACC_NUMBER_OF_AXES]; \
/* Accelerometer subsystem current full scale value.*/ \
float accfullscale;
/**
* @brief ADXL355 3-axis accelerometer class.
*/
struct ADXL355Driver {
/** @brief Virtual Methods Table.*/
const struct ADXL355VMT *vmt;
/** @brief Base accelerometer interface.*/
BaseAccelerometer acc_if;
_adxl355_data
};
/** @} */
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Return the number of axes of the BaseAccelerometer.
*
* @param[in] devp pointer to @p ADXL355Driver.
*
* @return the number of axes.
*
* @api
*/
#define adxl355AccelerometerGetAxesNumber(devp) \
accelerometerGetAxesNumber(&((devp)->acc_if))
/**
* @brief Retrieves raw data from the BaseAccelerometer.
* @note This data is retrieved from MEMS register without any algebraical
* manipulation.
* @note The axes array must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] devp pointer to @p ADXL355Driver.
* @param[out] axes a buffer which would be filled with raw data.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
* @retval MSG_TIMEOUT if a timeout occurred before operation end.
*
* @api
*/
#define adxl355AccelerometerReadRaw(devp, axes) \
accelerometerReadRaw(&((devp)->acc_if), axes)
/**
* @brief Retrieves cooked data from the BaseAccelerometer.
* @note This data is manipulated according to the formula
* cooked = (raw * sensitivity) - bias.
* @note Final data is expressed as milli-G.
* @note The axes array must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] devp pointer to @p ADXL355Driver.
* @param[out] axes a buffer which would be filled with cooked data.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET if one or more I2C errors occurred, the errors can
* be retrieved using @p i2cGetErrors().
* @retval MSG_TIMEOUT if a timeout occurred before operation end.
*
* @api
*/
#define adxl355AccelerometerReadCooked(devp, axes) \
accelerometerReadCooked(&((devp)->acc_if), axes)
/**
* @brief Set bias values for the BaseAccelerometer.
* @note Bias must be expressed as milli-G.
* @note The bias buffer must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] devp pointer to @p ADXL355Driver.
* @param[in] bp a buffer which contains biases.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
*
* @api
*/
#define adxl355AccelerometerSetBias(devp, bp) \
accelerometerSetBias(&((devp)->acc_if), bp)
/**
* @brief Reset bias values for the BaseAccelerometer.
* @note Default biases value are obtained from device datasheet when
* available otherwise they are considered zero.
*
* @param[in] devp pointer to @p ADXL355Driver.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
*
* @api
*/
#define adxl355AccelerometerResetBias(devp) \
accelerometerResetBias(&((devp)->acc_if))
/**
* @brief Set sensitivity values for the BaseAccelerometer.
* @note Sensitivity must be expressed as milli-G/LSB.
* @note The sensitivity buffer must be at least the same size of the
* BaseAccelerometer axes number.
*
* @param[in] devp pointer to @p ADXL355Driver.
* @param[in] sp a buffer which contains sensitivities.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
*
* @api
*/
#define adxl355AccelerometerSetSensitivity(devp, sp) \
accelerometerSetSensitivity(&((devp)->acc_if), sp)
/**
* @brief Reset sensitivity values for the BaseAccelerometer.
* @note Default sensitivities value are obtained from device datasheet.
*
* @param[in] devp pointer to @p ADXL355Driver.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET otherwise.
*
* @api
*/
#define adxl355AccelerometerResetSensitivity(devp) \
accelerometerResetSensitivity(&((devp)->acc_if))
/**
* @brief Changes the ADXL355Driver accelerometer fullscale value.
* @note This function also rescale sensitivities and biases based on
* previous and next fullscale value.
* @note A recalibration is highly suggested after calling this function.
*
* @param[in] devp pointer to @p ADXL355Driver.
* @param[in] fs new fullscale value.
*
* @return The operation status.
* @retval MSG_OK if the function succeeded.
* @retval MSG_RESET otherwise.
*
* @api
*/
#define adxl355AccelerometerSetFullScale(devp, fs) \
(devp)->vmt->acc_set_full_scale(devp, fs)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void adxl355ObjectInit(ADXL355Driver *devp);
void adxl355Start(ADXL355Driver *devp, const ADXL355Config *config);
void adxl355Stop(ADXL355Driver *devp);
#ifdef __cplusplus
}
#endif
#endif /* _ADXL355_H_ */
/** @} */

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@ -1,10 +0,0 @@
# List of all the ADX355 device files.
ADXL355SRC := $(CHIBIOS)/os/ex/devices/ADI/adxl355.c
# Required include directories
ADXL355INC := $(CHIBIOS)/os/ex/include \
$(CHIBIOS)/os/ex/devices/ADI
# Shared variables
ALLCSRC += $(ADXL355SRC)
ALLINC += $(ADXL355INC)

View File

@ -31,11 +31,6 @@
* - STMicroelectronics Devices
* .
*
* @section adi_devices Analog Devices Devices
* This section contains all the drivers of devices produced by ADI.
* Devices currently supported are MEMS and are:
* - @b ADXL355: Low Noise, Low Drift, Low Power, 3-Axis Accelerometers;
*
* @section bosch_devices Bosch Devices
* This section contains all the drivers of devices produced by Bosch.
* Devices currently supported are MEMS and are:
@ -81,12 +76,6 @@
*
* @ingroup EX
*/
/**
* @defgroup EX_ADI Analog Devices Devices
* @brief Analog Devices Devices.
*
* @ingroup EX_DEVICES
*/
/**
* @defgroup EX_BOSCH Bosch Devices

View File

@ -1,268 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
uint32_t lockr;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_LOCKR},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_LOCKR},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_LOCKR},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_LOCKR},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_LOCKR},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_LOCKR},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_LOCKR},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_LOCKR},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_LOCKR},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_LOCKR},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_LOCKR}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
gpiop->LOCKR = config->lockr;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB2(STM32_GPIO_EN_MASK);
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* CHTODO: Fill the implementation.*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* CHTODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* CHTODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* CHTODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @note You can add your board-specific code here.
*/
void boardInit(void) {
}

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@ -1,9 +0,0 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_L552ZE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_L552ZE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

File diff suppressed because it is too large Load Diff

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@ -1,15 +0,0 @@
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32l4xx/templates
outputRoot: ..
dataRoot: .
freemarkerLinks: {
lib: ../../../../../tools/ftl/libs
}
data : {
doc1:xml (
board.chcfg
{
}
)
}

View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi
ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi
ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi
ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2020 Rocco Marco Guglielmi
ChibiOS - Copyright (C) 2019 Rocco Marco Guglielmi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

Some files were not shown because too many files have changed in this diff Show More