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ChibiOS
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It compiles... 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13019 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-09-22 19:28:17 +00:00
parent 75d0dbad44
commit 9eed738e8f
8 changed files with 41 additions and 32 deletions
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2
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/halconf.h
View File

@ -142,7 +142,7 @@
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#define HAL_USE_SERIAL FALSE
#endif
/**

14
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
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@ -31,6 +31,7 @@
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32G4xx_MCUCONF
#define STM32G473_MCUCONF
#define STM32G483_MCUCONF
#define STM32G474_MCUCONF
@ -43,11 +44,11 @@
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (STM32_PLS_LEV0 | \
STM32_PVDE_DISABLED)
#define STM32_HSI16_ENABLED FALSE
#define STM32_HSI48_ENABLED FALSE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_PLLSRC STM32_PLLSRC_HSI16
#define STM32_PLLM_VALUE 4
@ -56,7 +57,8 @@
#define STM32_PLLQ_VALUE 8
#define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK

2
os/hal/ports/STM32/LLD/EXTIv1/stm32_exti.h
View File

@ -54,7 +54,7 @@
/* Handling differences in ST headers.*/
#if !defined(STM32H7XX) && !defined(STM32L4XX) && !defined(STM32L4XXP) && \
!defined(STM32G0XX)
!defined(STM32G0XX) && !defined(STM32G4XX)
#define EMR1 EMR
#define IMR1 IMR
#define PR1 PR

8
os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
View File

@ -55,7 +55,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM2(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
#elif defined(STM32G0XX)
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM2_STOP
@ -82,7 +82,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM3(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
#elif defined(STM32G0XX)
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP
@ -109,7 +109,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM4(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM4
@ -134,7 +134,7 @@
#define ST_ENABLE_CLOCK() rccEnableTIM5(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP)
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM5

35
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -464,10 +464,17 @@
#endif
/**
* @brief APB prescaler value.
* @brief APB1 prescaler value.
*/
#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
#define STM32_PPRE STM32_PPRE_DIV1
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
#define STM32_PPRE1 STM32_PPRE1_DIV1
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
#define STM32_PPRE2 STM32_PPRE2_DIV1
#endif
/**
@ -639,10 +646,10 @@
#if defined(STM32G431xx) && !defined(STM32G431_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32G431_MCUCONF not defined"
#if defined(STM32G441xx) && !defined(STM32G441_MCUCONF)
#elif defined(STM32G441xx) && !defined(STM32G441_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32G441_MCUCONF not defined"
#if defined(STM32G471xx) && !defined(STM32G471_MCUCONF)
#elif defined(STM32G471xx) && !defined(STM32G471_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32G471_MCUCONF not defined"
#elif defined(STM32G473xx) && !defined(STM32G473_MCUCONF)
@ -778,15 +785,15 @@
*/
#define STM32_PLLR_MIN 8000000
/**
* @brief Maximum APB clock frequency.
*/
#define STM32_PCLK1_MAX 170000000
/**
* @brief Maximum APB clock frequency.
*/
#define STM32_PCLK1_MAX 170000000
/**
* @brief Maximum APB clock frequency.
*/
#define STM32_PCLK2_MAX 170000000
/**
* @brief Maximum APB clock frequency.
*/
#define STM32_PCLK2_MAX 170000000
/**
* @brief Maximum ADC clock frequency.
@ -1161,7 +1168,7 @@
(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
(STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
(STM32_I2S23SELL == STM32_I2S23SEL__PLLQCLK) || \
(STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLQEN (1 << 20)
#else

2
os/hal/ports/STM32/STM32G4xx/platform.mk
View File

@ -33,7 +33,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
#include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
#include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
#include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
#include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
#include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk

8
os/hal/ports/STM32/STM32G4xx/stm32_isr.c
View File

@ -71,8 +71,8 @@ void irqInit(void) {
nvicEnableVector(STM32_EXTI_LINE2_NUMBER, STM32_IRQ_EXTI2_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE3_NUMBER, STM32_IRQ_EXTI3_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE4_NUMBER, STM32_IRQ_EXTI4_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE5_9_HANDLER, STM32_IRQ_EXTI5_9_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE10_15_HANDLER, STM32_IRQ_EXTI10_15_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE5_9_NUMBER, STM32_IRQ_EXTI5_9_PRIORITY);
nvicEnableVector(STM32_EXTI_LINE10_15_NUMBER, STM32_IRQ_EXTI10_15_PRIORITY);
#endif
#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
STM32_TIM1_TIM15_TIM16_TIM17_INIT();
@ -100,8 +100,8 @@ void irqDeinit(void) {
nvicDisableVector(STM32_EXTI_LINE2_NUMBER);
nvicDisableVector(STM32_EXTI_LINE3_NUMBER);
nvicDisableVector(STM32_EXTI_LINE4_NUMBER);
nvicDisableVector(STM32_EXTI_LINE5_9_HANDLER);
nvicDisableVector(STM32_EXTI_LINE10_15_HANDLER);
nvicDisableVector(STM32_EXTI_LINE5_9_NUMBER);
nvicDisableVector(STM32_EXTI_LINE10_15_NUMBER);
#endif
#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
STM32_TIM1_TIM15_TIM16_TIM17_DEINIT();

2
os/hal/ports/STM32/STM32G4xx/stm32_isr.h
View File

@ -108,7 +108,7 @@
#define STM32_DMA2_CH5_NUMBER 60
#define STM32_DMA2_CH6_NUMBER 97
#define STM32_DMA2_CH7_NUMBER 98
#define STM32_DMA2_CH7_NUMBER 99
#define STM32_DMA2_CH8_NUMBER 99
/*
* EXTI unit.