From 9f4fea96777a9a0fc3e6da73036b0ebe461c4fe9 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 14 Jul 2020 09:41:33 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13760 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- demos/STM32/RT-STM32L552ZE-NUCLEO144/Makefile | 2 +- os/common/ports/ARMv8-M-ML/chcore.h | 141 +++++++++++------- .../ARMv8-M-ML/compilers/GCC/chcoreasm.S | 18 ++- 3 files changed, 104 insertions(+), 57 deletions(-) diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144/Makefile b/demos/STM32/RT-STM32L552ZE-NUCLEO144/Makefile index 069f0204a..ff69995fb 100644 --- a/demos/STM32/RT-STM32L552ZE-NUCLEO144/Makefile +++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144/Makefile @@ -105,7 +105,7 @@ include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_L552ZE/board.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v8m-ml.mk +include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk # Auto-build files in ./source recursively. include $(CHIBIOS)/tools/mk/autobuild.mk # Other files (optional). diff --git a/os/common/ports/ARMv8-M-ML/chcore.h b/os/common/ports/ARMv8-M-ML/chcore.h index 24d00e7e0..7a8eb8c8a 100644 --- a/os/common/ports/ARMv8-M-ML/chcore.h +++ b/os/common/ports/ARMv8-M-ML/chcore.h @@ -314,34 +314,34 @@ typedef uint64_t stkalign_t; * @note It is implemented to match the Cortex-Mx exception context. */ struct port_extctx { - uint32_t r0; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r12; - uint32_t lr_thd; - uint32_t pc; - uint32_t xpsr; -#if CORTEX_USE_FPU - uint32_t s0; - uint32_t s1; - uint32_t s2; - uint32_t s3; - uint32_t s4; - uint32_t s5; - uint32_t s6; - uint32_t s7; - uint32_t s8; - uint32_t s9; - uint32_t s10; - uint32_t s11; - uint32_t s12; - uint32_t s13; - uint32_t s14; - uint32_t s15; - uint32_t fpscr; - uint32_t reserved; -#endif /* CORTEX_USE_FPU */ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr_thd; + uint32_t pc; + uint32_t xpsr; +#if (CORTEX_USE_FPU == TRUE) || defined(__DOXYGEN__) + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t s8; + uint32_t s9; + uint32_t s10; + uint32_t s11; + uint32_t s12; + uint32_t s13; + uint32_t s14; + uint32_t s15; + uint32_t fpscr; + uint32_t reserved; +#endif /* CORTEX_USE_FPU == TRUE */ }; /** @@ -350,33 +350,36 @@ struct port_extctx { * switch. */ struct port_intctx { -#if CORTEX_USE_FPU - uint32_t s16; - uint32_t s17; - uint32_t s18; - uint32_t s19; - uint32_t s20; - uint32_t s21; - uint32_t s22; - uint32_t s23; - uint32_t s24; - uint32_t s25; - uint32_t s26; - uint32_t s27; - uint32_t s28; - uint32_t s29; - uint32_t s30; - uint32_t s31; -#endif /* CORTEX_USE_FPU */ - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t lr; +#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__) + uint32_t splim; +#endif +#if (CORTEX_USE_FPU == TRUE) || defined(__DOXYGEN__) + uint32_t s16; + uint32_t s17; + uint32_t s18; + uint32_t s19; + uint32_t s20; + uint32_t s21; + uint32_t s22; + uint32_t s23; + uint32_t s24; + uint32_t s25; + uint32_t s26; + uint32_t s27; + uint32_t s28; + uint32_t s29; + uint32_t s30; + uint32_t s31; +#endif /* CORTEX_USE_FPU == TRUE */ + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t lr; }; /** @@ -407,6 +410,31 @@ struct port_context { #define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) +/** + * @brief Initialization of stack check part of thread context. + */ +#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__) + #define PORT_SETUP_CONTEXT_SPLIM(tp, wbase) \ + (tp)->ctx.sp->splim = (uint32_t)(wbase) +#else + #define PORT_SETUP_CONTEXT_SPLIM(tp, wbase) +#endif + +/** + * @brief Initialization of FPU part of thread context. + */ +#if (CORTEX_USE_FPU == TRUE) || defined(__DOXYGEN__) + #define PORT_SETUP_CONTEXT_FPU(tp) \ + (tp)->ctx.sp->fpscr = (uint32_t)0 +#else + #define PORT_SETUP_CONTEXT_FPU(tp) +#endif + +/** + * @brief Initialization of MPU part of thread context. + */ +#define PORT_SETUP_CONTEXT_MPU(tp) + /** * @brief Platform dependent part of the @p chThdCreateI() API. * @details This code usually setup the context switching frame represented @@ -418,6 +446,9 @@ struct port_context { (tp)->ctx.sp->r4 = (uint32_t)(pf); \ (tp)->ctx.sp->r5 = (uint32_t)(arg); \ (tp)->ctx.sp->lr = (uint32_t)__port_thread_start; \ + PORT_SETUP_CONTEXT_SPLIM(tp, wbase); \ + PORT_SETUP_CONTEXT_FPU(tp); \ + PORT_SETUP_CONTEXT_MPU(tp); \ } while (0) /** diff --git a/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S b/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S index 94b7160be..94afedd19 100644 --- a/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S +++ b/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S @@ -89,8 +89,24 @@ __port_switch: /* Saving FPU context.*/ vpush {s16-s31} #endif + +#if CH_DBG_ENABLE_STACK_CHECK + /* Saving stack limit register.*/ + mrs r3, PSPLIM + push {r3} + movs r3, #0 + msr PSPLIM, r3 /* Temporarily disabling stack check.*/ +#endif + + /* Switching stacks.*/ str sp, [r1, #CONTEXT_OFFSET] ldr sp, [r0, #CONTEXT_OFFSET] + +#if CH_DBG_ENABLE_STACK_CHECK + pop {r3} + msr PSPLIM, r3 +#endif + #if CORTEX_USE_FPU /* Restoring FPU context.*/ vpop {s16-s31} @@ -142,7 +158,7 @@ __port_switch_from_isr: #endif bl chSchDoPreemption #if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock + bl __dbg_check_unlock #endif #if CH_DBG_STATISTICS bl __stats_stop_measure_crit_thd