Various fixes to OCTOSPI e DMAv1 and MX25.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12401 110e8d01-0319-4d1e-a829-52ad28d1bb01

os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.c

@@ -352,8 +352,7 @@ void snor_device_init(SNORDriver *devp) {
   n25q_reset_memory(devp);
 
   /* Reading device ID and unique ID.*/
-  wspiReceive(devp->config->busp, &mx25_cmd_read_id,
+  wspiReceive(devp->config->busp, &mx25_cmd_read_id, 3U, devp->device_id);
-              sizeof devp->device_id, devp->device_id);
 #endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */
 
   /* Checking if the device is white listed.*/
@@ -382,7 +381,7 @@ void snor_device_init(SNORDriver *devp) {
     /* Reading ID again for confirmation, in DTR mode bytes are read twice,
        it needs adjusting.*/
 #if MX25_BUS_MODE == MX25_BUS_MODE_OPI_DTR
-    bus_cmd_dummy_receive(devp->config->busp, MX25_CMD_OPI_RDID, 6, id);
+    bus_cmd_dummy_receive(devp->config->busp, MX25_CMD_OPI_RDID, 6U, id);
     id[1] = id[2];
     id[2] = id[4];
 #else

os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c

@@ -545,6 +545,13 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
   }
 #endif
 
+#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
+  /* Enabling DMAMUX if present.*/
+  if (dma.streams_mask == 0U) {
+    rccEnableDMAMUX(true);
+  }
+#endif
+
   /* Putting the stream in a safe state.*/
   dmaStreamDisable(dmastp);
   dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
@@ -607,6 +614,13 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
     rccDisableDMA2();
   }
 #endif
+
+#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
+  /* Shutting down DMAMUX if present.*/
+  if (dma.streams_mask == 0U) {
+    rccDisableDMAMUX();
+  }
+#endif
 }
 
 #if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)

os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c

@@ -205,6 +205,7 @@ void wspi_lld_start(WSPIDriver *wspip) {
                                  (void *)wspip);
       osalDbgAssert(!b, "stream already allocated");
       rccEnableOCTOSPI1(true);
+      dmaSetRequestSource(wspip->dma, STM32_DMAMUX1_OCTOSPI1);
     }
 #endif
 
@@ -216,6 +217,7 @@ void wspi_lld_start(WSPIDriver *wspip) {
                                  (void *)wspip);
       osalDbgAssert(!b, "stream already allocated");
       rccEnableOCTOSPI2(true);
+      dmaSetRequestSource(wspip->dma, STM32_DMAMUX1_OCTOSPI2);
     }
 #endif
 
@@ -285,10 +287,10 @@ void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
 #endif
   wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
   wspip->ospi->DLR = 0U;
-  wspip->ospi->IR  = cmdp->cmd;
-  wspip->ospi->ABR = cmdp->alt;
   wspip->ospi->TCR = cmdp->dummy;
   wspip->ospi->CCR = cmdp->cfg;
+  wspip->ospi->ABR = cmdp->alt;
+  wspip->ospi->IR  = cmdp->cmd;
   if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
     wspip->ospi->AR  = cmdp->addr;
   }
@@ -314,10 +316,10 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
 
   wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
   wspip->ospi->DLR = n - 1;
-  wspip->ospi->IR  = cmdp->cmd;
-  wspip->ospi->ABR = cmdp->alt;
   wspip->ospi->TCR = cmdp->dummy;
   wspip->ospi->CCR = cmdp->cfg;
+  wspip->ospi->ABR = cmdp->alt;
+  wspip->ospi->IR  = cmdp->cmd;
   if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
     wspip->ospi->AR  = cmdp->addr;
   }
@@ -345,10 +347,10 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
 
   wspip->ospi->CR  = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) | OCTOSPI_CR_FMODE_0;
   wspip->ospi->DLR = n - 1;
-  wspip->ospi->IR  = cmdp->cmd;
-  wspip->ospi->ABR = cmdp->alt;
   wspip->ospi->TCR = cmdp->dummy;
   wspip->ospi->CCR = cmdp->cfg;
+  wspip->ospi->ABR = cmdp->alt;
+  wspip->ospi->IR  = cmdp->cmd;
   if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {
     wspip->ospi->AR  = cmdp->addr;
   }
@@ -380,11 +382,11 @@ void wspi_lld_map_flash(WSPIDriver *wspip,
   wspip->ospi->CR  = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) |
                      (OCTOSPI_CR_FMODE_1 | OCTOSPI_CR_FMODE_0);
   wspip->ospi->DLR = 0;
-  wspip->ospi->IR  = cmdp->cmd;
-  wspip->ospi->ABR = 0;
   wspip->ospi->TCR = cmdp->dummy;
-  wspip->ospi->AR  = 0;
   wspip->ospi->CCR = cmdp->cfg;
+  wspip->ospi->ABR = 0;
+  wspip->ospi->IR  = cmdp->cmd;
+  wspip->ospi->AR  = 0;
 
   /* Mapped flash absolute base address.*/
   if (addrp != NULL) {

os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h

@@ -416,6 +416,34 @@
 #define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
 /** @} */
 
+/**
+ * @name    DMAMUX peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the DMAMUX peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
+
+/**
+ * @brief   Disables the DMAMUX peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
+
+/**
+ * @brief   Resets the DMAMUX peripheral.
+ *
+ * @api
+ */
+#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
+/** @} */
+
 /**
  * @name    PWR interface specific RCC operations
  * @{