diff --git a/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h b/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h index 65e46bcc3..66ce1cfcf 100644 --- a/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/NIL-STM32G474RE-NUCLEO64/cfg/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h index 81331d88d..80a51c967 100644 --- a/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h @@ -39,6 +39,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h b/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h index 34a186346..e948fac0b 100644 --- a/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32G474RE-DISCOVERY-DPOW1/cfg/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h b/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h index c0bc6778c..6d7a7f0be 100644 --- a/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h b/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h index 65e46bcc3..66ce1cfcf 100644 --- a/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h +++ b/demos/various/RT-TEST-Latency/cfg/stm32g474re_nucleo64/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h index c093ae9c4..1c62622f9 100644 --- a/os/hal/include/hal.h +++ b/os/hal/include/hal.h @@ -42,10 +42,6 @@ #define HAL_USE_CAN FALSE #endif -#if !defined(HAL_USE_CLK) -#define HAL_USE_CLK FALSE -#endif - #if !defined(HAL_USE_CRY) #define HAL_USE_CRY FALSE #endif diff --git a/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h index 707cf6f67..7ef41e344 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32g474re_nucleo64/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h index d2094d046..0a2272a67 100644 --- a/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h +++ b/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h b/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h index f0eacce36..7eaeb6ab3 100644 --- a/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h +++ b/testrt/IRQ_STORM/cfg/stm32g474re_nucleo64/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h b/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h index f0eacce36..7eaeb6ab3 100644 --- a/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h +++ b/testrt/VT_STORM/cfg/stm32g474re_nucleo64/mcuconf.h @@ -41,6 +41,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_CLOCK_DYNAMIC FALSE #define STM32_VOS STM32_VOS_RANGE1 #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) diff --git a/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl index f13345a4f..e18ecc9cf 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32g4x1xx/mcuconf.h.ftl @@ -50,6 +50,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"} +#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"} #define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"} #define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"} #define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"} diff --git a/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl index e9b4abd88..c40a453df 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32g4x4xx/mcuconf.h.ftl @@ -52,6 +52,7 @@ * HAL driver system settings. */ #define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"} +#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"} #define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"} #define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"} #define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}