git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6183 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
79ad42bc2b
commit
a042a8234a
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@ -79,7 +79,7 @@
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<link>
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<link>
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<name>board</name>
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<name>board</name>
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<type>2</type>
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<type>2</type>
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||||||
<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
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</link>
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</link>
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<link>
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<link>
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||||||
<name>os</name>
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<name>os</name>
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||||||
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@ -79,7 +79,7 @@
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<link>
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<link>
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||||||
<name>board</name>
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<name>board</name>
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<type>2</type>
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<type>2</type>
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||||||
<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
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</link>
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</link>
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<link>
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<link>
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<name>os</name>
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<name>os</name>
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||||||
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@ -79,7 +79,7 @@
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<link>
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<link>
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||||||
<name>board</name>
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<name>board</name>
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||||||
<type>2</type>
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<type>2</type>
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||||||
<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
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</link>
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</link>
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||||||
<link>
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<link>
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||||||
<name>os</name>
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<name>os</name>
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||||||
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@ -32,16 +32,16 @@ static const CANConfig cancfg = {
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*/
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*/
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static WORKING_AREA(can_rx_wa, 256);
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static WORKING_AREA(can_rx_wa, 256);
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static msg_t can_rx(void *p) {
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static msg_t can_rx(void *p) {
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EventListener el;
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event_listener_t el;
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CANRxFrame rxmsg;
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CANRxFrame rxmsg;
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(void)p;
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(void)p;
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chRegSetThreadName("receiver");
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chRegSetThreadName("receiver");
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chEvtRegister(&CAND1.rxfull_event, &el, 0);
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chEvtRegister(&CAND1.rxfull_event, &el, 0);
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while(!chThdShouldTerminate()) {
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while(!chThdShouldTerminateX()) {
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if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0)
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if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0)
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continue;
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continue;
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while (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, TIME_IMMEDIATE) == RDY_OK) {
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while (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, TIME_IMMEDIATE) == MSG_OK) {
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/* Process message.*/
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/* Process message.*/
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palTogglePad(GPIOE, GPIOE_LED3_RED);
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palTogglePad(GPIOE, GPIOE_LED3_RED);
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}
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}
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@ -66,7 +66,7 @@ static msg_t can_tx(void * p) {
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txmsg.data32[0] = 0x55AA55AA;
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txmsg.data32[0] = 0x55AA55AA;
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txmsg.data32[1] = 0x00FF00FF;
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txmsg.data32[1] = 0x00FF00FF;
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while (!chThdShouldTerminate()) {
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while (!chThdShouldTerminateX()) {
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canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100));
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canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100));
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chThdSleepMilliseconds(500);
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chThdSleepMilliseconds(500);
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}
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}
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@ -79,7 +79,7 @@
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<link>
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<link>
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<name>board</name>
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<name>board</name>
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<type>2</type>
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<type>2</type>
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<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
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</link>
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</link>
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<link>
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<link>
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<name>os</name>
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<name>os</name>
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@ -25,19 +25,20 @@ static void led5off(void *arg) {
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/* Triggered when the button is pressed or released. The LED5 is set to ON.*/
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/* Triggered when the button is pressed or released. The LED5 is set to ON.*/
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static void extcb1(EXTDriver *extp, expchannel_t channel) {
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static void extcb1(EXTDriver *extp, expchannel_t channel) {
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static VirtualTimer vt4;
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static virtual_timer_t vt4;
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(void)extp;
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(void)extp;
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(void)channel;
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(void)channel;
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palSetPad(GPIOE, GPIOE_LED10_RED);
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palSetPad(GPIOE, GPIOE_LED10_RED);
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chSysLockFromIsr();
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chSysLockFromISR();
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if (chVTIsArmedI(&vt4))
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/* Timer reset, if still active.*/
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chVTResetI(&vt4);
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chVTResetI(&vt4);
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/* LED4 set to OFF after 200mS.*/
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/* LED4 set to OFF after 200mS.*/
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chVTSetI(&vt4, MS2ST(200), led5off, NULL);
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chVTSetI(&vt4, MS2ST(200), led5off, NULL);
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chSysUnlockFromIsr();
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chSysUnlockFromISR();
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}
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}
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static const EXTConfig extcfg = {
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static const EXTConfig extcfg = {
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@ -27,7 +27,7 @@
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<link>
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<link>
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||||||
<name>board</name>
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<name>board</name>
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<type>2</type>
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<type>2</type>
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<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
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</link>
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</link>
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<link>
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<link>
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<name>os</name>
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<name>os</name>
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@ -357,7 +357,7 @@
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* @note The default is @p FALSE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
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#define CH_DBG_STATISTICS TRUE
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#define CH_DBG_STATISTICS FALSE
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#endif
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#endif
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/**
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/**
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@ -368,7 +368,7 @@
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* @note The default is @p FALSE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
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#define CH_DBG_SYSTEM_STATE_CHECK TRUE
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#define CH_DBG_SYSTEM_STATE_CHECK FALSE
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#endif
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#endif
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/**
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/**
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@ -379,7 +379,7 @@
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* @note The default is @p FALSE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_CHECKS TRUE
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#define CH_DBG_ENABLE_CHECKS FALSE
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#endif
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#endif
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/**
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/**
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@ -391,7 +391,7 @@
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* @note The default is @p FALSE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_ASSERTS TRUE
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#define CH_DBG_ENABLE_ASSERTS FALSE
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#endif
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#endif
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/**
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/**
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@ -402,7 +402,7 @@
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* @note The default is @p FALSE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_TRACE TRUE
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#define CH_DBG_ENABLE_TRACE FALSE
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#endif
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#endif
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/**
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/**
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* @p panic_msg variable set to @p NULL.
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* @p panic_msg variable set to @p NULL.
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*/
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*/
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#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_STACK_CHECK TRUE
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#define CH_DBG_ENABLE_STACK_CHECK FALSE
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#endif
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#endif
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/**
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/**
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* @note The default is @p FALSE.
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* @note The default is @p FALSE.
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*/
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*/
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#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
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#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
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#define CH_DBG_FILL_THREADS TRUE
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#define CH_DBG_FILL_THREADS FALSE
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#endif
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#endif
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/**
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/**
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@ -46,12 +46,12 @@
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#define MSG_SEND_LEFT 0
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#define MSG_SEND_LEFT 0
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#define MSG_SEND_RIGHT 1
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#define MSG_SEND_RIGHT 1
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static bool_t saturated;
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static bool saturated;
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/*
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/*
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* Mailboxes and buffers.
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* Mailboxes and buffers.
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*/
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*/
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static Mailbox mb[NUM_THREADS];
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static mailbox_t mb[NUM_THREADS];
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static msg_t b[NUM_THREADS][MAILBOX_SIZE];
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static msg_t b[NUM_THREADS][MAILBOX_SIZE];
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/*
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/*
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@ -101,7 +101,7 @@ static msg_t WorkerThread(void *arg) {
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/* If this thread is not at the end of a chain re-sending the message,
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/* If this thread is not at the end of a chain re-sending the message,
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note this check works because the variable target is unsigned.*/
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note this check works because the variable target is unsigned.*/
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msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE);
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msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE);
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if (msg != RDY_OK)
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if (msg != MSG_OK)
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saturated = TRUE;
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saturated = TRUE;
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}
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}
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else {
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else {
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@ -121,11 +121,11 @@ static void gpt2cb(GPTDriver *gptp) {
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msg_t msg;
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msg_t msg;
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(void)gptp;
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(void)gptp;
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chSysLockFromIsr();
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chSysLockFromISR();
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msg = chMBPostI(&mb[0], MSG_SEND_RIGHT);
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msg = chMBPostI(&mb[0], MSG_SEND_RIGHT);
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if (msg != RDY_OK)
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if (msg != MSG_OK)
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saturated = TRUE;
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saturated = TRUE;
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chSysUnlockFromIsr();
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chSysUnlockFromISR();
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}
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}
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/*
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/*
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@ -135,11 +135,11 @@ static void gpt3cb(GPTDriver *gptp) {
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msg_t msg;
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msg_t msg;
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(void)gptp;
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(void)gptp;
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chSysLockFromIsr();
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chSysLockFromISR();
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msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT);
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msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT);
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if (msg != RDY_OK)
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if (msg != MSG_OK)
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saturated = TRUE;
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saturated = TRUE;
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chSysUnlockFromIsr();
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chSysUnlockFromISR();
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}
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}
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/*
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/*
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@ -221,14 +221,14 @@ int main(void) {
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/*
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/*
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* Activates GPTs.
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* Activates GPTs.
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*/
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*/
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gptStart(&GPTD2, &gpt2cfg);
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gptStart(&GPTD4, &gpt2cfg);
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gptStart(&GPTD3, &gpt3cfg);
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gptStart(&GPTD3, &gpt3cfg);
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/*
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/*
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* Initializes the mailboxes and creates the worker threads.
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* Initializes the mailboxes and creates the worker threads.
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*/
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*/
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for (i = 0; i < NUM_THREADS; i++) {
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for (i = 0; i < NUM_THREADS; i++) {
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chMBInit(&mb[i], b[i], MAILBOX_SIZE);
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chMBObjectInit(&mb[i], b[i], MAILBOX_SIZE);
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chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i],
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chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i],
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NORMALPRIO - 20, WorkerThread, (void *)i);
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NORMALPRIO - 20, WorkerThread, (void *)i);
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}
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}
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@ -291,10 +291,10 @@ int main(void) {
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saturated = FALSE;
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saturated = FALSE;
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threshold = 0;
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threshold = 0;
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for (interval = 2000; interval >= 10; interval -= interval / 10) {
|
for (interval = 2000; interval >= 10; interval -= interval / 10) {
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gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/
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gptStartContinuous(&GPTD4, interval - 1); /* Slightly out of phase.*/
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gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/
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gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/
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chThdSleepMilliseconds(1000);
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chThdSleepMilliseconds(1000);
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gptStopTimer(&GPTD2);
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gptStopTimer(&GPTD4);
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gptStopTimer(&GPTD3);
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gptStopTimer(&GPTD3);
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if (!saturated)
|
if (!saturated)
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print(".");
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print(".");
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|
@ -315,7 +315,7 @@ int main(void) {
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if (threshold > worst)
|
if (threshold > worst)
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worst = threshold;
|
worst = threshold;
|
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}
|
}
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gptStopTimer(&GPTD2);
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gptStopTimer(&GPTD4);
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gptStopTimer(&GPTD3);
|
gptStopTimer(&GPTD3);
|
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|
|
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print("Worst case at ");
|
print("Worst case at ");
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|
|
|
@ -107,16 +107,16 @@
|
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* GPT driver system settings.
|
* GPT driver system settings.
|
||||||
*/
|
*/
|
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#define STM32_GPT_USE_TIM1 TRUE
|
#define STM32_GPT_USE_TIM1 TRUE
|
||||||
#define STM32_GPT_USE_TIM2 TRUE
|
#define STM32_GPT_USE_TIM2 FALSE
|
||||||
#define STM32_GPT_USE_TIM3 TRUE
|
#define STM32_GPT_USE_TIM3 TRUE
|
||||||
#define STM32_GPT_USE_TIM4 TRUE
|
#define STM32_GPT_USE_TIM4 TRUE
|
||||||
#define STM32_GPT_USE_TIM6 TRUE
|
#define STM32_GPT_USE_TIM6 TRUE
|
||||||
#define STM32_GPT_USE_TIM7 TRUE
|
#define STM32_GPT_USE_TIM7 TRUE
|
||||||
#define STM32_GPT_USE_TIM8 TRUE
|
#define STM32_GPT_USE_TIM8 TRUE
|
||||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 6
|
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 10
|
#define STM32_GPT_TIM3_IRQ_PRIORITY 10
|
||||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
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#define STM32_GPT_TIM4_IRQ_PRIORITY 6
|
||||||
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
|
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
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#define STM32_GPT_TIM7_IRQ_PRIORITY 7
|
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
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||||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||||||
|
|
|
@ -27,7 +27,7 @@
|
||||||
<link>
|
<link>
|
||||||
<name>board</name>
|
<name>board</name>
|
||||||
<type>2</type>
|
<type>2</type>
|
||||||
<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
|
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
|
||||||
</link>
|
</link>
|
||||||
<link>
|
<link>
|
||||||
<name>os</name>
|
<name>os</name>
|
||||||
|
|
|
@ -83,13 +83,13 @@ int main(void) {
|
||||||
chSysInit();
|
chSysInit();
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Initializes the PWM driver 2 and ICU driver 3.
|
* Initializes the PWM driver 4 and ICU driver 3.
|
||||||
* GPIOA15 is the PWM output.
|
* GPIOD12 is the PWM output channel 0.
|
||||||
* GPIOC6 is the ICU input.
|
* GPIOC6 is the ICU input ICU_CHANNEL_1.
|
||||||
* The two pins have to be externally connected together.
|
* The two pins have to be externally connected together.
|
||||||
*/
|
*/
|
||||||
pwmStart(&PWMD2, &pwmcfg);
|
pwmStart(&PWMD4, &pwmcfg);
|
||||||
palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(1));
|
palSetPadMode(GPIOD, 12, PAL_MODE_ALTERNATE(2));
|
||||||
icuStart(&ICUD3, &icucfg);
|
icuStart(&ICUD3, &icucfg);
|
||||||
palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2));
|
palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2));
|
||||||
icuEnable(&ICUD3);
|
icuEnable(&ICUD3);
|
||||||
|
@ -98,33 +98,33 @@ int main(void) {
|
||||||
/*
|
/*
|
||||||
* Starts the PWM channel 0 using 75% duty cycle.
|
* Starts the PWM channel 0 using 75% duty cycle.
|
||||||
*/
|
*/
|
||||||
pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500));
|
pwmEnableChannel(&PWMD4, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD4, 7500));
|
||||||
chThdSleepMilliseconds(5000);
|
chThdSleepMilliseconds(5000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Changes the PWM channel 0 to 50% duty cycle.
|
* Changes the PWM channel 0 to 50% duty cycle.
|
||||||
*/
|
*/
|
||||||
pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000));
|
pwmEnableChannel(&PWMD4, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD4, 5000));
|
||||||
chThdSleepMilliseconds(5000);
|
chThdSleepMilliseconds(5000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Changes the PWM channel 0 to 25% duty cycle.
|
* Changes the PWM channel 0 to 25% duty cycle.
|
||||||
*/
|
*/
|
||||||
pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500));
|
pwmEnableChannel(&PWMD4, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD4, 2500));
|
||||||
chThdSleepMilliseconds(5000);
|
chThdSleepMilliseconds(5000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Changes PWM period to half second the duty cycle becomes 50%
|
* Changes PWM period to half second the duty cycle becomes 50%
|
||||||
* implicitly.
|
* implicitly.
|
||||||
*/
|
*/
|
||||||
pwmChangePeriod(&PWMD2, 5000);
|
pwmChangePeriod(&PWMD4, 5000);
|
||||||
chThdSleepMilliseconds(5000);
|
chThdSleepMilliseconds(5000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Disables channel 0 and stops the drivers.
|
* Disables channel 0 and stops the drivers.
|
||||||
*/
|
*/
|
||||||
pwmDisableChannel(&PWMD2, 0);
|
pwmDisableChannel(&PWMD4, 0);
|
||||||
pwmStop(&PWMD2);
|
pwmStop(&PWMD4);
|
||||||
icuDisable(&ICUD3);
|
icuDisable(&ICUD3);
|
||||||
icuStop(&ICUD3);
|
icuStop(&ICUD3);
|
||||||
palClearPad(GPIOE, GPIOE_LED4_BLUE);
|
palClearPad(GPIOE, GPIOE_LED4_BLUE);
|
||||||
|
|
|
@ -139,7 +139,7 @@
|
||||||
#define STM32_ICU_USE_TIM1 TRUE
|
#define STM32_ICU_USE_TIM1 TRUE
|
||||||
#define STM32_ICU_USE_TIM2 FALSE
|
#define STM32_ICU_USE_TIM2 FALSE
|
||||||
#define STM32_ICU_USE_TIM3 TRUE
|
#define STM32_ICU_USE_TIM3 TRUE
|
||||||
#define STM32_ICU_USE_TIM4 TRUE
|
#define STM32_ICU_USE_TIM4 FALSE
|
||||||
#define STM32_ICU_USE_TIM8 TRUE
|
#define STM32_ICU_USE_TIM8 TRUE
|
||||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||||
|
@ -152,9 +152,9 @@
|
||||||
*/
|
*/
|
||||||
#define STM32_PWM_USE_ADVANCED FALSE
|
#define STM32_PWM_USE_ADVANCED FALSE
|
||||||
#define STM32_PWM_USE_TIM1 FALSE
|
#define STM32_PWM_USE_TIM1 FALSE
|
||||||
#define STM32_PWM_USE_TIM2 TRUE
|
#define STM32_PWM_USE_TIM2 FALSE
|
||||||
#define STM32_PWM_USE_TIM3 FALSE
|
#define STM32_PWM_USE_TIM3 FALSE
|
||||||
#define STM32_PWM_USE_TIM4 FALSE
|
#define STM32_PWM_USE_TIM4 TRUE
|
||||||
#define STM32_PWM_USE_TIM8 FALSE
|
#define STM32_PWM_USE_TIM8 FALSE
|
||||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||||
|
|
|
@ -12,7 +12,7 @@ The application demonstrates the use of the STM32F30x PWM-ICU drivers.
|
||||||
|
|
||||||
** Board Setup **
|
** Board Setup **
|
||||||
|
|
||||||
- Connect PA15 and PC6 together.
|
- Connect PD12 (PWM output) and PC6 (ICU input) together.
|
||||||
|
|
||||||
** Build Procedure **
|
** Build Procedure **
|
||||||
|
|
||||||
|
|
|
@ -79,7 +79,7 @@
|
||||||
<link>
|
<link>
|
||||||
<name>board</name>
|
<name>board</name>
|
||||||
<type>2</type>
|
<type>2</type>
|
||||||
<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
|
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
|
||||||
</link>
|
</link>
|
||||||
<link>
|
<link>
|
||||||
<name>os</name>
|
<name>os</name>
|
||||||
|
|
|
@ -79,7 +79,7 @@
|
||||||
<link>
|
<link>
|
||||||
<name>board</name>
|
<name>board</name>
|
||||||
<type>2</type>
|
<type>2</type>
|
||||||
<locationURI>CHIBIOS/boards/ST_STM32F3_DISCOVERY</locationURI>
|
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
|
||||||
</link>
|
</link>
|
||||||
<link>
|
<link>
|
||||||
<name>os</name>
|
<name>os</name>
|
||||||
|
|
|
@ -17,15 +17,15 @@
|
||||||
#include "ch.h"
|
#include "ch.h"
|
||||||
#include "hal.h"
|
#include "hal.h"
|
||||||
|
|
||||||
static VirtualTimer vt1, vt2;
|
static virtual_timer_t vt1, vt2;
|
||||||
|
|
||||||
static void restart(void *p) {
|
static void restart(void *p) {
|
||||||
|
|
||||||
(void)p;
|
(void)p;
|
||||||
|
|
||||||
chSysLockFromIsr();
|
chSysLockFromISR();
|
||||||
uartStartSendI(&UARTD1, 14, "Hello World!\r\n");
|
uartStartSendI(&UARTD1, 14, "Hello World!\r\n");
|
||||||
chSysUnlockFromIsr();
|
chSysUnlockFromISR();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ledoff(void *p) {
|
static void ledoff(void *p) {
|
||||||
|
@ -51,11 +51,10 @@ static void txend2(UARTDriver *uartp) {
|
||||||
|
|
||||||
(void)uartp;
|
(void)uartp;
|
||||||
palClearPad(GPIOE, GPIOE_LED3_RED);
|
palClearPad(GPIOE, GPIOE_LED3_RED);
|
||||||
chSysLockFromIsr();
|
chSysLockFromISR();
|
||||||
if (chVTIsArmedI(&vt1))
|
|
||||||
chVTResetI(&vt1);
|
chVTResetI(&vt1);
|
||||||
chVTSetI(&vt1, MS2ST(5000), restart, NULL);
|
chVTSetI(&vt1, MS2ST(5000), restart, NULL);
|
||||||
chSysUnlockFromIsr();
|
chSysUnlockFromISR();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -78,11 +77,10 @@ static void rxchar(UARTDriver *uartp, uint16_t c) {
|
||||||
(void)c;
|
(void)c;
|
||||||
/* Flashing the LED each time a character is received.*/
|
/* Flashing the LED each time a character is received.*/
|
||||||
palSetPad(GPIOE, GPIOE_LED3_RED);
|
palSetPad(GPIOE, GPIOE_LED3_RED);
|
||||||
chSysLockFromIsr();
|
chSysLockFromISR();
|
||||||
if (chVTIsArmedI(&vt2))
|
|
||||||
chVTResetI(&vt2);
|
chVTResetI(&vt2);
|
||||||
chVTSetI(&vt2, MS2ST(200), ledoff, NULL);
|
chVTSetI(&vt2, MS2ST(200), ledoff, NULL);
|
||||||
chSysUnlockFromIsr();
|
chSysUnlockFromISR();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
Loading…
Reference in New Issue