andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed OTG regression on STM32H7xx. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13982 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-12-25 09:17:19 +00:00
parent 26a37f1bcb
commit a0b31ffd48
2 changed files with 8 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
View File

@ -229,14 +229,6 @@
#define STM32_USBCLK STM32_48CLK
#elif defined(STM32H7XX)
/* Defines directly STM32_USBCLK.*/
#define rccEnableOTG_FS rccEnableUSB2_OTG_FS
#define rccDisableOTG_FS rccDisableUSB2_OTG_FS
#define rccResetOTG_FS rccResetUSB2_OTG_FS
#define rccEnableOTG_HS rccEnableUSB1_OTG_HS
#define rccDisableOTG_HS rccDisableUSB1_OTG_HS
#define rccResetOTG_HS rccResetUSB1_OTG_HS
#define rccEnableOTG_HSULPI rccEnableUSB1_HSULPI
#define rccDisableOTG_HSULPI rccDisableUSB1_HSULPI
#else
#error "unsupported STM32 platform for OTG functionality"
#endif

16
os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
View File

@ -935,21 +935,21 @@
*
* @api
*/
#define rccEnableUSB1_OTG_FS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGFSEN, lp)
#define rccEnableOTG_FS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGFSEN, lp)
/**
* @brief Disables the USB1_OTG_FS peripheral clock.
*
* @api
*/
#define rccDisableUSB1_OTG_FS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGFSEN)
#define rccDisableOTG_FS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGFSEN)
/**
* @brief Resets the USB1_OTG_FS peripheral.
*
* @api
*/
#define rccResetUSB1_OTG_FS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGFSRST)
#define rccResetOTG_FS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGFSRST)
/**
* @brief Enables the USB2_OTG_HS peripheral clock.
@ -958,21 +958,21 @@
*
* @api
*/
#define rccEnableUSB2_OTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSEN, lp)
#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_USB2OTGHSEN, lp)
/**
* @brief Disables the USB2_OTG_HS peripheral clock.
*
* @api
*/
#define rccDisableUSB2_OTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSEN)
#define rccDisableOTG_HS() rccDisableAHB1(RCC_AHB1ENR_USB2OTGHSEN)
/**
* @brief Resets the USB2_OTG_HS peripheral.
*
* @api
*/
#define rccResetUSB2_OTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGHSRST)
#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_USB2OTGHSRST)
/**
* @brief Enables the USB1_OTG_HS ULPI peripheral clock.
@ -981,14 +981,14 @@
*
* @api
*/
#define rccEnableUSB1_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN, lp)
#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN, lp)
/**
* @brief Disables the USB1_OTG_HS peripheral clock.
*
* @api
*/
#define rccDisableUSB1_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN)
#define rccDisableOTG_HSULPI() rccDisableAHB1(RCC_AHB1ENR_USB1OTGHSULPIEN)
/**
* @brief Enables the USB2_OTG_HS ULPI peripheral clock.