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ChibiOS
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Bypass option for SDIOv1 driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12527 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2019-01-05 15:18:32 +00:00
parent b798346a97
commit a3653f3b16
4 changed files with 14 additions and 2 deletions
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3
os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
View File

@ -451,7 +451,8 @@ void sdc_lld_start_clk(SDCDriver *sdcp) {
* @notapi * @notapi
*/ */
void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
#if 0
#if STM32_SDC_SDIO_50MHZ
if (SDC_CLK_50MHz == clk) { if (SDC_CLK_50MHz == clk) {
sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS
| SDIO_CLKCR_BYPASS; | SDIO_CLKCR_BYPASS;

8
os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
View File

@ -91,6 +91,14 @@
#define STM32_SDC_SDIO_IRQ_PRIORITY 9 #define STM32_SDC_SDIO_IRQ_PRIORITY 9
#endif #endif
/**
* @brief Enable clock bypass.
* @note Allow clock speed up to 50 Mhz.
*/
#if !defined(STM32_SDC_SDIO_50MHZ) || defined(__DOXYGEN__)
#define STM32_SDC_SDIO_50MHZ FALSE
#endif
/** /**
* @brief Write timeout in milliseconds. * @brief Write timeout in milliseconds.
*/ */

3
os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
View File

@ -548,7 +548,8 @@ void sdc_lld_start_clk(SDCDriver *sdcp) {
* @notapi * @notapi
*/ */
void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
#if STM32_SDC_SDMMC_50MHZ && defined(STM32F7XX)
#if STM32_SDC_SDMMC_50MHZ
if (SDC_CLK_50MHz == clk) { if (SDC_CLK_50MHz == clk) {
sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) |
#if STM32_SDC_SDMMC_PWRSAV #if STM32_SDC_SDMMC_PWRSAV

2
readme.txt
View File

@ -75,6 +75,8 @@
***************************************************************************** *****************************************************************************
*** Next *** *** Next ***
- NEW: Added option to enable bypass on SDIOv1 driver allowing to use a
50MHz clock.
- NEW: Added TIM15, TIM16 and TIM17 support on GPT, ICU and PWM drivers, - NEW: Added TIM15, TIM16 and TIM17 support on GPT, ICU and PWM drivers,
limited to STM32F3, L4 and L4+ platforms. limited to STM32F3, L4 and L4+ platforms.
- NEW: STM32H7xx and STM32L4+ ports reworked to support dynamic DMA - NEW: STM32H7xx and STM32L4+ ports reworked to support dynamic DMA