git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16407 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
f0daea9c01
commit
a3b2b44a9c
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@ -163,7 +163,7 @@
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* @brief Enables the SPI subsystem.
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*/
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#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
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#define HAL_USE_SPI FALSE
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#define HAL_USE_SPI TRUE
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#endif
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/**
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@ -320,6 +320,35 @@
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 TRUE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_USE_SPI4 FALSE
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#define STM32_SPI_SPI1_RX_GPDMA_CHANNEL STM32_GPDMA1_MASK_FIFO2
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#define STM32_SPI_SPI1_TX_GPDMA_CHANNEL STM32_GPDMA1_MASK_FIFO2
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#define STM32_SPI_SPI2_RX_GPDMA_CHANNEL STM32_GPDMA2_MASK_FIFO2
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#define STM32_SPI_SPI2_TX_GPDMA_CHANNEL STM32_GPDMA2_MASK_FIFO2
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#define STM32_SPI_SPI3_RX_GPDMA_CHANNEL STM32_GPDMA1_MASK_FIFO2
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#define STM32_SPI_SPI3_TX_GPDMA_CHANNEL STM32_GPDMA1_MASK_FIFO2
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#define STM32_SPI_SPI4_RX_GPDMA_CHANNEL STM32_GPDMA2_MASK_FIFO2
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#define STM32_SPI_SPI4_TX_GPDMA_CHANNEL STM32_GPDMA2_MASK_FIFO2
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#define STM32_SPI_SPI5_RX_GPDMA_CHANNEL STM32_GPDMA1_MASK_FIFO2
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#define STM32_SPI_SPI5_TX_GPDMA_CHANNEL STM32_GPDMA1_MASK_FIFO2
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#define STM32_SPI_SPI6_RX_GPDMA_CHANNEL STM32_GPDMA2_MASK_FIFO2
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#define STM32_SPI_SPI6_TX_GPDMA_CHANNEL STM32_GPDMA2_MASK_FIFO2
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI5_DMA_PRIORITY 1
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#define STM32_SPI_SPI6_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#define STM32_SPI_SPI6_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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@ -50,7 +50,7 @@
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* @note Don't use this array directly, use the appropriate wrapper macros
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* instead: @p STM32_GPDMA1_CHANNEL1, @p STM32_GPDMA1_CHANNEL2 etc.
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*/
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const stm32_gpdma_channel_t __stm32_gpdma_channels[STM32_GPDMA_CHANNELS] = {
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const stm32_gpdma_channel_t __stm32_gpdma_channels[STM32_GPDMA_NUM_CHANNELS] = {
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#if STM32_GPDMA1_NUM_CHANNELS > 0
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{GPDMA1_Channel0, STM32_GPDMA1_CH0_NUMBER},
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#endif
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@ -125,7 +125,7 @@ static struct {
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* @brief GPDMA callback parameter.
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*/
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void *param;
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} channels[STM32_GPDMA_CHANNELS];
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} channels[STM32_GPDMA_NUM_CHANNELS];
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} gpdma;
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/*===========================================================================*/
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@ -405,7 +405,7 @@ void dmaInit(void) {
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unsigned i;
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gpdma.allocated_mask = 0U;
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for (i = 0; i < STM32_GPDMA_CHANNELS; i++) {
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for (i = 0; i < STM32_GPDMA_NUM_CHANNELS; i++) {
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__stm32_gpdma_channels[i].channel->CCR = 0U;
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gpdma.channels[i].func = NULL;
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}
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@ -442,7 +442,7 @@ const stm32_gpdma_channel_t *gpdmaChannelAllocI(uint32_t cmask,
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available = gpdma.allocated_mask & cmask;
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/* Searching for a free channel.*/
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for (i = 0U; i <= STM32_GPDMA_CHANNELS; i++) {
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for (i = 0U; i <= STM32_GPDMA_NUM_CHANNELS; i++) {
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uint32_t mask = (uint32_t)(1U << i);
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if ((available & mask) == 0U) {
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/* Channel found.*/
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@ -62,6 +62,8 @@
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#define STM32_GPDMA_CSR_HTF DMA_CSR_HTF
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#define STM32_GPDMA_CSR_TCF DMA_CSR_TCF
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#define STM32_GPDMA_CSR_IDLEF DMA_CSR_IDLEF
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#define STM32_GPDMA_CSR_ERRORS (DMA_CSR_TOF | DMA_CSR_USEF | \
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DMA_CSR_ULEF | DMA_CSR_DTEF)
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#define STM32_GPDMA_CSR_ALL (DMA_CSR_TOF | DMA_CSR_SUSPF | \
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DMA_CSR_USEF | DMA_CSR_ULEF | \
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DMA_CSR_DTEF | DMA_CSR_HTF | \
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@ -84,7 +86,11 @@
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#define STM32_GPDMA_CCR_EN DMA_CCR_EN
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#define STM32_GPDMA_CTR1_DSEC DMA_CTR1_DSEC
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#define STM32_GPDMA_CTR1_DAP DMA_CTR1_DAP
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#define STM32_GPDMA_CTR1_DAP_POS DMA_CTR1_DAP_Pos
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#define STM32_GPDMA_CTR1_DAP_MASK (1U << STM32_GPDMA_CTR1_DAP_POS)
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#define STM32_GPDMA_CTR1_DAP(n) ((n) << STM32_GPDMA_CTR1_DAP_POS)
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#define STM32_GPDMA_CTR1_DAP_MEM STM32_GPDMA_CTR1_DAP(STM32_GPDMA_MEMORY_PORT)
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#define STM32_GPDMA_CTR1_DAP_PER STM32_GPDMA_CTR1_DAP(STM32_GPDMA_PERIPHERAL_PORT)
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#define STM32_GPDMA_CTR1_DHX DMA_CTR1_DHX
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#define STM32_GPDMA_CTR1_DBX DMA_CTR1_DBX
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#define STM32_GPDMA_CTR1_DBL_POS DMA_CTR1_DBL_1_Pos
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@ -94,11 +100,15 @@
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#define STM32_GPDMA_CTR1_DDW_LOG2_POS DMA_CTR1_DDW_LOG2_Pos
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#define STM32_GPDMA_CTR1_DDW_LOG2_MASK (3U << STM32_GPDMA_CTR1_DDW_LOG2_POS)
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#define STM32_GPDMA_CTR1_DDW_LOG2(n) ((n) << STM32_GPDMA_CTR1_DDW_LOG2_POS)
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#define STM32_GPDMA_CTR1_DDW_BYTE(n) STM32_GPDMA_CTR1_DDW_LOG2(0U)
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#define STM32_GPDMA_CTR1_DDW_HALF(n) STM32_GPDMA_CTR1_DDW_LOG2(1U)
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#define STM32_GPDMA_CTR1_DDW_WORD(n) STM32_GPDMA_CTR1_DDW_LOG2(2U)
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#define STM32_GPDMA_CTR1_DDW_BYTE STM32_GPDMA_CTR1_DDW_LOG2(0U)
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#define STM32_GPDMA_CTR1_DDW_HALF STM32_GPDMA_CTR1_DDW_LOG2(1U)
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#define STM32_GPDMA_CTR1_DDW_WORD STM32_GPDMA_CTR1_DDW_LOG2(2U)
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#define STM32_GPDMA_CTR1_SSEC DMA_CTR1_SSEC
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#define STM32_GPDMA_CTR1_SAP DMA_CTR1_SAP
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#define STM32_GPDMA_CTR1_SAP_POS DMA_CTR1_SAP_Pos
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#define STM32_GPDMA_CTR1_SAP_MASK (1U << STM32_GPDMA_CTR1_SAP_POS)
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#define STM32_GPDMA_CTR1_SAP(n) ((n) << STM32_GPDMA_CTR1_SAP_POS)
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#define STM32_GPDMA_CTR1_SAP_MEM STM32_GPDMA_CTR1_SAP(STM32_GPDMA_MEMORY_PORT)
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#define STM32_GPDMA_CTR1_SAP_PER STM32_GPDMA_CTR1_SAP(STM32_GPDMA_PERIPHERAL_PORT)
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#define STM32_GPDMA_CTR1_SBX DMA_CTR1_SBX
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#define STM32_GPDMA_CTR1_PAM_POS DMA_CTR1_PAM_Pos
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#define STM32_GPDMA_CTR1_PAM_MASK (3U << STM32_GPDMA_CTR1_PAM_POS)
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@ -131,6 +141,7 @@
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#define STM32_GPDMA_CTR2_TRIGM(n) ((n) << STM32_GPDMA_CTR2_TRIGM_POS)
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#define STM32_GPDMA_CTR2_PFREQ DMA_CTR2_PFREQ
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#define STM32_GPDMA_CTR2_BREQ DMA_CTR2_BREQ
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#define STM32_GPDMA_CTR2_DREQ DMA_CTR2_DREQ
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#define STM32_GPDMA_CTR2_SWREQ DMA_CTR2_SWREQ
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#define STM32_GPDMA_CTR2_REQSEL_POS DMA_CTR2_REQSEL_Pos
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#define STM32_GPDMA_CTR2_REQSEL_MASK (0xFFU << STM32_GPDMA_CTR2_REQSEL_POS)
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@ -194,6 +205,17 @@
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#define STM32_GPDMA_IS_VALID_PRIORITY(prio) \
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(((prio) >= 0U) && ((prio) <= 3U))
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/**
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* @brief Checks if a GPDMA channel id is within the valid range.
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*
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* @param[in] id GPDMA channel id
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* @retval The check result.
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* @retval false invalid GPDMA channel.
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* @retval true correct GPDMA channel.
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*/
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#define STM32_GPDMA_IS_VALID_CHANNEL(id) (((id) >= 0U) && \
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((id) <= STM32_GPDMA_NUM_CHANNELS))
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/**
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* @brief Returns an unique numeric identifier for a GPDMA channel.
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*
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@ -273,7 +295,7 @@
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/**
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* @brief Total number of channels among all GPDMAs.
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*/
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#define STM32_GPDMA_CHANNELS \
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#define STM32_GPDMA_NUM_CHANNELS \
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(STM32_GPDMA1_NUM_CHANNELS + STM32_GPDMA2_NUM_CHANNELS)
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#if STM32_GPDMA1_NUM_CHANNELS > 0
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@ -532,7 +554,7 @@ typedef struct {
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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extern const stm32_gpdma_channel_t __stm32_gpdma_channels[STM32_GPDMA_CHANNELS];
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extern const stm32_gpdma_channel_t __stm32_gpdma_channels[STM32_GPDMA_NUM_CHANNELS];
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#endif
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#ifdef __cplusplus
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@ -0,0 +1,9 @@
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ifeq ($(USE_SMART_BUILD),yes)
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ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv4/hal_spi_v2_lld.c
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endif
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else
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv4/hal_spi_v2_lld.c
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endif
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PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv4
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,546 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPIv4/hal_spi_v2_lld.h
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* @brief STM32 SPI (v2) subsystem low level driver header.
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*
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* @addtogroup SPI
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* @{
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*/
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#ifndef HAL_SPI_V2_LLD_H
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#define HAL_SPI_V2_LLD_H
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Circular mode support flag.
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*/
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#define SPI_SUPPORTS_CIRCULAR FALSE
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/**
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* @brief Slave mode support flag.
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*/
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#define SPI_SUPPORTS_SLAVE_MODE TRUE
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/**
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* @name Register helpers not found in ST headers
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* @{
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*/
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#define SPI_CFG1_MBR_VALUE(n) ((n) << SPI_CFG1_MBR_Pos)
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#define SPI_CFG1_MBR_DIV2 SPI_CFG1_MBR_VALUE(0)
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#define SPI_CFG1_MBR_DIV4 SPI_CFG1_MBR_VALUE(1)
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#define SPI_CFG1_MBR_DIV8 SPI_CFG1_MBR_VALUE(2)
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#define SPI_CFG1_MBR_DIV16 SPI_CFG1_MBR_VALUE(3)
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#define SPI_CFG1_MBR_DIV32 SPI_CFG1_MBR_VALUE(4)
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#define SPI_CFG1_MBR_DIV64 SPI_CFG1_MBR_VALUE(5)
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#define SPI_CFG1_MBR_DIV128 SPI_CFG1_MBR_VALUE(6)
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#define SPI_CFG1_MBR_DIV256 SPI_CFG1_MBR_VALUE(7)
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#define SPI_CFG1_CRCSIZE_VALUE(n) ((n) << SPI_CFG1_CRCSIZE_Pos)
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#define SPI_CFG1_UDRDET_VALUE(n) ((n) << SPI_CFG1_UDRDET_Pos)
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#define SPI_CFG1_UDRCFG_VALUE(n) ((n) << SPI_CFG1_UDRCFG_Pos)
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#define SPI_CFG1_FTHLV_VALUE(n) ((n) << SPI_CFG1_FTHLV_Pos)
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#define SPI_CFG1_DSIZE_VALUE(n) ((n) << SPI_CFG1_DSIZE_Pos)
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#define SPI_CFG2_SP_VALUE(n) ((n) << SPI_CFG2_SP_Pos)
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#define SPI_CFG2_COMM_VALUE(n) ((n) << SPI_CFG2_COMM_Pos)
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#define SPI_CFG2_COMM_FULL_DUPLEX SPI_CFG2_COMM_VALUE(0)
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#define SPI_CFG2_COMM_TRANSMITTER SPI_CFG2_COMM_VALUE(1)
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#define SPI_CFG2_COMM_RECEIVER SPI_CFG2_COMM_VALUE(2)
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#define SPI_CFG2_COMM_HALF_DUPLEX SPI_CFG2_COMM_VALUE(3)
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#define SPI_CFG2_MIDI_VALUE(n) ((n) << SPI_CFG2_MIDI_Pos)
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#define SPI_CFG2_MSSI_VALUE(n) ((n) << SPI_CFG2_MSSI_Pos)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief SPI1 driver enable switch.
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* @details If set to @p TRUE the support for SPI1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI1 FALSE
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#endif
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/**
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* @brief SPI2 driver enable switch.
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* @details If set to @p TRUE the support for SPI2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI2 FALSE
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#endif
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/**
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* @brief SPI3 driver enable switch.
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* @details If set to @p TRUE the support for SPI3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI3 FALSE
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#endif
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/**
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* @brief SPI4 driver enable switch.
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* @details If set to @p TRUE the support for SPI4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI4 FALSE
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#endif
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/**
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* @brief SPI5 driver enable switch.
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* @details If set to @p TRUE the support for SPI5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI5 FALSE
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#endif
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/**
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* @brief SPI6 driver enable switch.
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* @details If set to @p TRUE the support for SPI6 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI6 FALSE
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#endif
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/**
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* @brief Filler pattern used when there is nothing to transmit.
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*/
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#if !defined(STM32_SPI_FILLER_PATTERN) || defined(__DOXYGEN__)
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#define STM32_SPI_FILLER_PATTERN 0xFFFFFFFFU
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#endif
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/**
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* @brief SPI1 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI2 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI3 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI4 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI5 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#endif
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/**
|
||||
* @brief SPI6 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI1 GPDMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX GPDMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI2 GPDMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX GPDMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI3 GPDMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX GPDMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI4 GPDMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX GPDMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI5 GPDMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX GPDMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI6 GPDMA priority (0..3|lowest..highest).
|
||||
* @note The priority level is used for both the TX and RX GPDMA channels but
|
||||
* because of the channels ordering the RX channel has always priority
|
||||
* over the TX channel.
|
||||
*/
|
||||
#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI GPDMA error hook.
|
||||
*/
|
||||
#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
|
||||
#error "SPI1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
|
||||
#error "SPI2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
|
||||
#error "SPI3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
|
||||
#error "SPI4 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
|
||||
#error "SPI5 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
|
||||
#error "SPI6 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
|
||||
!STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
|
||||
#error "SPI driver activated but no SPI peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI2"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI3"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI4"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI5"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to SPI6"
|
||||
#endif
|
||||
|
||||
/* Check on the presence of the GPDMA channels settings in mcuconf.h.*/
|
||||
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_GPDMA_CHANNEL) || \
|
||||
!defined(STM32_SPI_SPI1_TX_GPDMA_CHANNEL))
|
||||
#error "SPI1 GPDMA channels not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_GPDMA_CHANNEL) || \
|
||||
!defined(STM32_SPI_SPI2_TX_GPDMA_CHANNEL))
|
||||
#error "SPI2 GPDMA channels not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_GPDMA_CHANNEL) || \
|
||||
!defined(STM32_SPI_SPI3_TX_GPDMA_CHANNEL))
|
||||
#error "SPI3 GPDMA channels not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_GPDMA_CHANNEL) || \
|
||||
!defined(STM32_SPI_SPI4_TX_GPDMA_CHANNEL))
|
||||
#error "SPI4 GPDMA channels not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_GPDMA_CHANNEL) || \
|
||||
!defined(STM32_SPI_SPI5_TX_GPDMA_CHANNEL))
|
||||
#error "SPI5 GPDMA channels not defined"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_GPDMA_CHANNEL) || \
|
||||
!defined(STM32_SPI_SPI6_TX_GPDMA_CHANNEL))
|
||||
#error "SPI6 GPDMA channels not defined"
|
||||
#endif
|
||||
|
||||
/* Check on the validity of the assigned GPDMA channels.*/
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_RX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI1 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_TX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI1 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_RX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI2 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_TX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI2 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_RX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI3 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_TX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI3 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_RX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI4 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_TX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI4 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_RX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI5 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_TX_GPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI5 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_RX_BGPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI6 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_GPDMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_TX_BGPDMA_CHANNEL)
|
||||
#error "Invalid GPDMA channel assigned to SPI6 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_GPDMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
|
||||
#error "Invalid GPDMA priority assigned to SPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_GPDMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
|
||||
#error "Invalid GPDMA priority assigned to SPI2"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_GPDMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
|
||||
#error "Invalid GPDMA priority assigned to SPI3"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_GPDMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
|
||||
#error "Invalid GPDMA priority assigned to SPI4"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_GPDMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
|
||||
#error "Invalid GPDMA priority assigned to SPI5"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_GPDMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
|
||||
#error "Invalid GPDMA priority assigned to SPI6"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 || STM32_SPI_USE_SPI2 || STM32_SPI_USE_SPI3 || \
|
||||
STM32_SPI_USE_SPI4 || STM32_SPI_USE_SPI5 || STM32_SPI_USE_SPI6
|
||||
#if !defined(STM32_GPDMA_REQUIRED)
|
||||
#define STM32_GPDMA_REQUIRED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD
|
||||
#error "SPI_SELECT_MODE_LLD not supported by this driver"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define spi_lld_driver_fields \
|
||||
/* Pointer to the SPIx registers block.*/ \
|
||||
SPI_TypeDef *spi; \
|
||||
/** Union of the RX GPDMA channels.*/ \
|
||||
union { \
|
||||
/* Receive GPDMA channel.*/ \
|
||||
const stm32_gpdma_channel_t *dma; \
|
||||
} rx; \
|
||||
/* Union of the TX GPDMA channels.*/ \
|
||||
union { \
|
||||
/* Transmit GPDMA channel.*/ \
|
||||
const stm32_gpdma_channel_t *dma; \
|
||||
} tx; \
|
||||
/* DMA request line for RX.*/ \
|
||||
uint8_t dreqrx; \
|
||||
/* DMA request line for TX.*/ \
|
||||
uint8_t dreqtx; \
|
||||
/* DMA priority.*/ \
|
||||
uint8_t dprio; \
|
||||
/* DMA RX settings.*/ \
|
||||
uint32_t dtr1rx; \
|
||||
/* DMA TX settings.*/ \
|
||||
uint32_t dtr1tx; \
|
||||
/* Sink for discarded data.*/ \
|
||||
uint32_t rxsink; \
|
||||
/* Source for default TX pattern.*/ \
|
||||
uint32_t txsource
|
||||
|
||||
/**
|
||||
* @brief Low level fields of the SPI configuration structure.
|
||||
*/
|
||||
#define spi_lld_config_fields \
|
||||
/* SPI CFG1 register initialization data.*/ \
|
||||
uint32_t cfg1; \
|
||||
/* SPI CFG2 register initialization data.*/ \
|
||||
uint32_t cfg2
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID1;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID2;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID3;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID4;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID5;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID6;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void spi_lld_init(void);
|
||||
msg_t spi_lld_start(SPIDriver *spip);
|
||||
void spi_lld_stop(SPIDriver *spip);
|
||||
#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
|
||||
void spi_lld_select(SPIDriver *spip);
|
||||
void spi_lld_unselect(SPIDriver *spip);
|
||||
#endif
|
||||
msg_t spi_lld_ignore(SPIDriver *spip, size_t n);
|
||||
msg_t spi_lld_exchange(SPIDriver *spip, size_t n,
|
||||
const void *txbuf, void *rxbuf);
|
||||
msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
|
||||
msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
|
||||
msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep);
|
||||
uint32_t spi_lld_polled_exchange(SPIDriver *spip, uint32_t frame);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_SPI */
|
||||
|
||||
#endif /* HAL_SPI_V2_LLD_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -30,6 +30,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPDMAv1/driver.mk
|
|||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ICACHEv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv4/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3/driver.mk
|
||||
|
|
|
|||
|
|
@ -80,6 +80,143 @@
|
|||
#define STM32_GPDMA2_MASK_FIFO4 0x00003000U
|
||||
#define STM32_GPDMA2_MASK_FIFO4_2D 0x0000C000U
|
||||
|
||||
#define STM32_GPDMA_REQ_ADC1 0U
|
||||
#define STM32_GPDMA_REQ_ADC2 1U
|
||||
#define STM32_GPDMA_REQ_DAC1_CH1 2U
|
||||
#define STM32_GPDMA_REQ_DAC1_CH2 3U
|
||||
#define STM32_GPDMA_REQ_TIM6_UPD 4U
|
||||
#define STM32_GPDMA_REQ_TIM7_UPD 5U
|
||||
#define STM32_GPDMA_REQ_SPI1_RX 6U
|
||||
#define STM32_GPDMA_REQ_SPI1_TX 7U
|
||||
#define STM32_GPDMA_REQ_SPI2_RX 8U
|
||||
#define STM32_GPDMA_REQ_SPI2_TX 9U
|
||||
#define STM32_GPDMA_REQ_SPI3_RX 10U
|
||||
#define STM32_GPDMA_REQ_SPI3_TX 11U
|
||||
#define STM32_GPDMA_REQ_I2C1_RX 12U
|
||||
#define STM32_GPDMA_REQ_I2C1_TX 13U
|
||||
#define STM32_GPDMA_REQ_RESERVED14 14U
|
||||
#define STM32_GPDMA_REQ_I2C2_RX 15U
|
||||
#define STM32_GPDMA_REQ_I2C2_TX 16U
|
||||
#define STM32_GPDMA_REQ_RESERVED17 17U
|
||||
#define STM32_GPDMA_REQ_I2C3_RX 18U
|
||||
#define STM32_GPDMA_REQ_I2C3_TX 19U
|
||||
#define STM32_GPDMA_REQ_RESERVED20 20U
|
||||
#define STM32_GPDMA_REQ_USART1_RX 21U
|
||||
#define STM32_GPDMA_REQ_USART1_TX 22U
|
||||
#define STM32_GPDMA_REQ_USART2_RX 23U
|
||||
#define STM32_GPDMA_REQ_USART2_TX 24U
|
||||
#define STM32_GPDMA_REQ_USART3_RX 25U
|
||||
#define STM32_GPDMA_REQ_USART3_TX 26U
|
||||
#define STM32_GPDMA_REQ_UART4_RX 27U
|
||||
#define STM32_GPDMA_REQ_UART4_TX 28U
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#define STM32_GPDMA_REQ_UART5_RX 29U
|
||||
#define STM32_GPDMA_REQ_UART5_TX 30U
|
||||
#define STM32_GPDMA_REQ_USART6_RX 31U
|
||||
#define STM32_GPDMA_REQ_USART6_TX 32U
|
||||
#define STM32_GPDMA_REQ_UART7_RX 33U
|
||||
#define STM32_GPDMA_REQ_UART7_TX 34U
|
||||
#define STM32_GPDMA_REQ_UART8_RX 35U
|
||||
#define STM32_GPDMA_REQ_UART8_TX 36U
|
||||
#define STM32_GPDMA_REQ_UART9_RX 37U
|
||||
#define STM32_GPDMA_REQ_UART9_TX 38U
|
||||
#define STM32_GPDMA_REQ_USART10_RX 39U
|
||||
#define STM32_GPDMA_REQ_USART10_TX 40U
|
||||
#define STM32_GPDMA_REQ_USART11_RX 41U
|
||||
#define STM32_GPDMA_REQ_USART11_TX 42U
|
||||
#define STM32_GPDMA_REQ_UART12_RX 43U
|
||||
#define STM32_GPDMA_REQ_UART12_TX 44U
|
||||
#define STM32_GPDMA_REQ_LPUART1_RX 45U
|
||||
#define STM32_GPDMA_REQ_LPUART1_TX 46U
|
||||
#define STM32_GPDMA_REQ_SPI4_RX 47U
|
||||
#define STM32_GPDMA_REQ_SPI4_TX 48U
|
||||
#define STM32_GPDMA_REQ_SPI5_RX 49U
|
||||
#define STM32_GPDMA_REQ_SPI5_TX 50U
|
||||
#define STM32_GPDMA_REQ_SPI6_RX 51U
|
||||
#define STM32_GPDMA_REQ_SPI6_TX 52U
|
||||
#define STM32_GPDMA_REQ_SAI1_A 53U
|
||||
#define STM32_GPDMA_REQ_SAI1_B 54U
|
||||
#define STM32_GPDMA_REQ_SAI2_A 55U
|
||||
#define STM32_GPDMA_REQ_SAI2_B 56U
|
||||
#define STM32_GPDMA_REQ_OSPI1 57U
|
||||
#define STM32_GPDMA_REQ_TIM1_CC1 58U
|
||||
#define STM32_GPDMA_REQ_TIM1_CC2 59U
|
||||
#define STM32_GPDMA_REQ_TIM1_CC3 60U
|
||||
#define STM32_GPDMA_REQ_TIM1_CC4 61U
|
||||
#define STM32_GPDMA_REQ_TIM1_UPD 62U
|
||||
#define STM32_GPDMA_REQ_TIM1_TRG 63U
|
||||
#define STM32_GPDMA_REQ_TIM1_COM 64U
|
||||
#define STM32_GPDMA_REQ_TIM8_CC1 65U
|
||||
#define STM32_GPDMA_REQ_TIM8_CC2 66U
|
||||
#define STM32_GPDMA_REQ_TIM8_CC3 67U
|
||||
#define STM32_GPDMA_REQ_TIM8_CC4 68U
|
||||
#define STM32_GPDMA_REQ_TIM8_UPD 69U
|
||||
#define STM32_GPDMA_REQ_TIM8_TRG 70U
|
||||
#define STM32_GPDMA_REQ_TIM8_COM 71U
|
||||
#define STM32_GPDMA_REQ_TIM2_CC1 72U
|
||||
#define STM32_GPDMA_REQ_TIM2_CC2 73U
|
||||
#define STM32_GPDMA_REQ_TIM2_CC3 74U
|
||||
#define STM32_GPDMA_REQ_TIM2_CC4 75U
|
||||
#define STM32_GPDMA_REQ_TIM2_UPD 76U
|
||||
#define STM32_GPDMA_REQ_TIM3_CC1 77U
|
||||
#define STM32_GPDMA_REQ_TIM3_CC2 78U
|
||||
#define STM32_GPDMA_REQ_TIM3_CC3 79U
|
||||
#define STM32_GPDMA_REQ_TIM3_CC4 80U
|
||||
#define STM32_GPDMA_REQ_TIM3_UPD 81U
|
||||
#define STM32_GPDMA_REQ_TIM3_TRG 82U
|
||||
#define STM32_GPDMA_REQ_TIM4_CC1 83U
|
||||
#define STM32_GPDMA_REQ_TIM4_CC2 84U
|
||||
#define STM32_GPDMA_REQ_TIM4_CC3 85U
|
||||
#define STM32_GPDMA_REQ_TIM4_CC4 86U
|
||||
#define STM32_GPDMA_REQ_TIM4_UPD 87U
|
||||
#define STM32_GPDMA_REQ_TIM5_CC1 88U
|
||||
#define STM32_GPDMA_REQ_TIM5_CC2 89U
|
||||
#define STM32_GPDMA_REQ_TIM5_CC3 90U
|
||||
#define STM32_GPDMA_REQ_TIM5_CC4 91U
|
||||
#define STM32_GPDMA_REQ_TIM5_UPD 92U
|
||||
#define STM32_GPDMA_REQ_TIM5_TRG 93U
|
||||
#define STM32_GPDMA_REQ_TIM15_CC1 94U
|
||||
#define STM32_GPDMA_REQ_TIM15_UPD 95U
|
||||
#define STM32_GPDMA_REQ_TIM15_TRG 96U
|
||||
#define STM32_GPDMA_REQ_TIM15_COM 97U
|
||||
#define STM32_GPDMA_REQ_TIM16_CC1 98U
|
||||
#define STM32_GPDMA_REQ_TIM16_UPD 99U
|
||||
#define STM32_GPDMA_REQ_TIM17_CC1 100U
|
||||
#define STM32_GPDMA_REQ_TIM17_UPD 101U
|
||||
#define STM32_GPDMA_REQ_LPTIM1_IC1 102U
|
||||
#define STM32_GPDMA_REQ_LPTIM1_IC2 103U
|
||||
#define STM32_GPDMA_REQ_LPTIM1_UE 104U
|
||||
#define STM32_GPDMA_REQ_LPTIM2_IC1 105U
|
||||
#define STM32_GPDMA_REQ_LPTIM2_IC2 106U
|
||||
#define STM32_GPDMA_REQ_LPTIM2_UE 107U
|
||||
#define STM32_GPDMA_REQ_DCMI 108U
|
||||
#define STM32_GPDMA_REQ_AES_OUT 109U
|
||||
#define STM32_GPDMA_REQ_AES_IN 110U
|
||||
#define STM32_GPDMA_REQ_HASH_IN 111U
|
||||
#define STM32_GPDMA_REQ_UCPD1_RX 112U
|
||||
#define STM32_GPDMA_REQ_UCPD1_TX 113U
|
||||
#define STM32_GPDMA_REQ_CORDIC_READ 114U
|
||||
#define STM32_GPDMA_REQ_CORDIC_WRITE 115U
|
||||
#define STM32_GPDMA_REQ_FMAC_READ 116U
|
||||
#define STM32_GPDMA_REQ_FMAC_WRITE 117U
|
||||
#define STM32_GPDMA_REQ_SAES_OUT 118U
|
||||
#define STM32_GPDMA_REQ_SAES_IN 119U
|
||||
#define STM32_GPDMA_REQ_I3C_RX 120U
|
||||
#define STM32_GPDMA_REQ_I3C_TX 121U
|
||||
#define STM32_GPDMA_REQ_I3C_TC 122U
|
||||
#define STM32_GPDMA_REQ_I3C_RS 123U
|
||||
#define STM32_GPDMA_REQ_I2C4_RX 124U
|
||||
#define STM32_GPDMA_REQ_I2C4_TX 125U
|
||||
#define STM32_GPDMA_REQ_RESERVED126 126U
|
||||
#define STM32_GPDMA_REQ_LPTIM3_IC1 127U
|
||||
#define STM32_GPDMA_REQ_LPTIM3_IC2 128U
|
||||
#define STM32_GPDMA_REQ_LPTIM3_UE 129U
|
||||
#define STM32_GPDMA_REQ_LPTIM5_IC1 130U
|
||||
#define STM32_GPDMA_REQ_LPTIM5_IC2 131U
|
||||
#define STM32_GPDMA_REQ_LPTIM5_UE 132U
|
||||
#define STM32_GPDMA_REQ_LPTIM6_IC1 133U
|
||||
#define STM32_GPDMA_REQ_LPTIM6_IC2 134U
|
||||
#define STM32_GPDMA_REQ_LPTIM6_UE 135U
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32H562xx, STM32H563xx, STM32H573xx. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue