git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9508 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
b36f9f5585
commit
a3c37f98cc
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@ -25,8 +25,9 @@
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* @{
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*/
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#include "hal.h"
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#include <string.h>
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#include "hal.h"
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#include "m25q.h"
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/*===========================================================================*/
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@ -82,11 +83,7 @@ static flash_descriptor_t descriptor = {
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.attributes = FLASH_ATTR_ERASED_IS_ONE | FLASH_ATTR_REWRITABLE |
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FLASH_ATTR_SUSPEND_ERASE_CAPABLE,
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.page_size = 256U,
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#if M25Q_USE_SUB_SECTORS == TRUE
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.sectors_count = 4096U,
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#else
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.sectors_count = 256U,
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#endif
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.sectors_count = 0U, /* It is overwritten.*/
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.sectors = NULL,
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.sectors_size = SECTOR_SIZE,
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.address = 0U
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@ -209,9 +206,11 @@ static const uint8_t evconf_value[1] = {0xCF};
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#elif M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI2L
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static const uint8_t evconf_value[1] = {0x8F};
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#else
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static const uint8_t evconf_value[1] = {0xCF};//{0x4F};
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static const uint8_t evconf_value[1] = {0x4F};
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#endif
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static const uint8_t flash_status[1] = {(M25Q_READ_DUMMY_CYCLES << 4U) | 0x0FU};
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#endif /* M25Q_BUS_MODE != M25Q_BUS_MODE_SPI */
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/*===========================================================================*/
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@ -314,6 +313,39 @@ static void flash_cmd_receive(M25QDriver *devp,
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#endif
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}
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static void flash_cmd_send(M25QDriver *devp,
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uint8_t cmd,
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size_t n,
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const uint8_t *p) {
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#if M25Q_BUS_MODE != M25Q_BUS_MODE_SPI
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qspi_command_t mode;
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mode.cfg = QSPI_CFG_CMD(cmd) |
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#if M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI1L
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QSPI_CFG_CMD_MODE_ONE_LINE |
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QSPI_CFG_DATA_MODE_ONE_LINE;
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#elif M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI2L
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QSPI_CFG_CMD_MODE_TWO_LINES |
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QSPI_CFG_DATA_MODE_TWO_LINES;
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#else
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QSPI_CFG_CMD_MODE_FOUR_LINES |
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QSPI_CFG_DATA_MODE_FOUR_LINES;
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#endif
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mode.addr = 0U;
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mode.alt = 0U;
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qspiSend(devp->config->qspip, &mode, n, p);
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#else
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uint8_t buf[1];
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spiSelect(devp->config->spip);
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buf[0] = cmd;
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spiSend(devp->config->spip, 1, buf);
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spiSend(devp->config->spip, n, p);
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spiUnselect(devp->config->spip);
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#endif
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}
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static void flash_cmd_addr(M25QDriver *devp,
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uint8_t cmd,
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flash_address_t addr) {
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@ -437,6 +469,42 @@ static void flash_cmd_addr_receive(M25QDriver *devp,
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#endif
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}
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#if (M25Q_BUS_MODE != M25Q_BUS_MODE_SPI) || defined(__DOXYGEN__)
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static void flash_cmd_addr_dummy_receive(M25QDriver *devp,
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uint8_t cmd,
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flash_address_t addr,
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uint8_t dummy,
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size_t n,
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uint8_t *p) {
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qspi_command_t mode;
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mode.cfg = QSPI_CFG_CMD(cmd) |
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#if M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI1L
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QSPI_CFG_CMD_MODE_ONE_LINE |
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QSPI_CFG_ADDR_MODE_ONE_LINE |
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QSPI_CFG_ADDR_SIZE_24 |
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QSPI_CFG_DUMMY_CYCLES(dummy) |
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QSPI_CFG_DATA_MODE_ONE_LINE;
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#elif M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI2L
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QSPI_CFG_CMD_MODE_TWO_LINES |
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QSPI_CFG_ADDR_MODE_TWO_LINES |
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QSPI_CFG_ADDR_SIZE_24 |
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QSPI_CFG_DUMMY_CYCLES(dummy) |
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QSPI_CFG_DATA_MODE_TWO_LINES;
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#else
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QSPI_CFG_CMD_MODE_FOUR_LINES |
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QSPI_CFG_ADDR_MODE_FOUR_LINES |
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QSPI_CFG_ADDR_SIZE_24 |
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QSPI_CFG_DUMMY_CYCLES(dummy) |
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QSPI_CFG_DATA_MODE_FOUR_LINES;
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#endif
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mode.addr = addr;
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mode.alt = 0U;
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qspiReceive(devp->config->qspip, &mode, n, p);
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}
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#endif /* M25Q_BUS_MODE != M25Q_BUS_MODE_SPI */
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static flash_error_t flash_poll_status(M25QDriver *devp) {
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return FLASH_NO_ERROR;
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@ -454,6 +522,38 @@ static const flash_descriptor_t *get_descriptor(void *instance) {
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static flash_error_t read(void *instance, flash_address_t addr,
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uint8_t *rp, size_t n) {
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M25QDriver *devp = (M25QDriver *)instance;
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osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
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osalDbgCheck((size_t)addr + n <= (size_t)descriptor.sectors_count *
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(size_t)descriptor.sectors_size);
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osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
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"invalid state");
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if (devp->state == FLASH_ERASE) {
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return FLASH_BUSY_ERASING;
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}
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/* Bus acquired.*/
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flash_bus_acquire(devp);
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/* FLASH_READY state while the operation is performed.*/
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devp->state = FLASH_READ;
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#if M25Q_BUS_MODE != M25Q_BUS_MODE_SPI
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/* Fast read command in QSPI mode.*/
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flash_cmd_addr_dummy_receive(devp, M25Q_CMD_FAST_READ,
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addr, M25Q_READ_DUMMY_CYCLES,
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n, rp);
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#else
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/* Normal read command in SPI mode.*/
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#endif
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/* Ready state again.*/
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devp->state = FLASH_READY;
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/* Bus released.*/
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flash_bus_release(devp);
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return FLASH_NO_ERROR;
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}
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@ -516,6 +616,18 @@ void m25qObjectInit(M25QDriver *devp) {
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#endif
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}
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static const qspi_command_t cmd_test_reset_enable_4 = {
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.cfg = QSPI_CFG_ALT_MODE_FOUR_LINES,
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.addr = 0,
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.alt = M25Q_CMD_RESET_ENABLE
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};
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static const qspi_command_t cmd_test_reset_memory_4 = {
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.cfg = QSPI_CFG_ALT_MODE_FOUR_LINES,
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.addr = 0,
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.alt = M25Q_CMD_RESET_MEMORY
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};
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/**
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* @brief Configures and activates N25Q128 driver.
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*
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@ -532,7 +644,6 @@ void m25qStart(M25QDriver *devp, const M25QConfig *config) {
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devp->config = config;
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if (devp->state == FLASH_STOP) {
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uint8_t id[3];
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/* Bus acquisition.*/
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flash_bus_acquire(devp);
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@ -546,46 +657,62 @@ void m25qStart(M25QDriver *devp, const M25QConfig *config) {
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/* QSPI initialization.*/
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qspiStart(devp->config->qspip, devp->config->qspicfg);
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/* Reading device ID and unique ID.*/
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#if M25Q_SWITCH_WIDTH == TRUE
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/* Attempting a device reset with decreasing bus widths, commands
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/* Attempting a device reset with different bus widths, commands
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shorter than 8 bits are ignored.*/
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qspiCommand(devp->config->qspip, &cmd_reset_enable_4);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_4);
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qspiCommand(devp->config->qspip, &cmd_reset_enable_2);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_2);
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qspiCommand(devp->config->qspip, &cmd_reset_enable_1);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_1);
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qspiCommand(devp->config->qspip, &cmd_reset_enable_2);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_2);
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qspiCommand(devp->config->qspip, &cmd_reset_enable_4);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_4);
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#endif
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/* Reading device ID.*/
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qspiReceive(devp->config->qspip, &cmd_read_id, 3, id);
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/* Reading device ID and unique ID.*/
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qspiReceive(devp->config->qspip, &cmd_read_id,
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sizeof devp->device_id, devp->device_id);
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#endif /* M25Q_BUS_MODE != M25Q_BUS_MODE_SPI */
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/* Checking if the device is white listed.*/
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osalDbgAssert(find_id(manufacturer_ids, sizeof manufacturer_ids, id[0]),
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osalDbgAssert(find_id(manufacturer_ids,
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sizeof manufacturer_ids,
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devp->device_id[0]),
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"invalid manufacturer id");
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osalDbgAssert(find_id(memory_type_ids, sizeof memory_type_ids, id[1]),
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osalDbgAssert(find_id(memory_type_ids,
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sizeof memory_type_ids,
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devp->device_id[1]),
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"invalid memory type id");
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#if (M25Q_BUS_MODE != M25Q_BUS_MODE_SPI) && (M25Q_SWITCH_WIDTH == TRUE)
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/* Setting up final bus width.*/
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qspiCommand(devp->config->qspip, &cmd_write_enable);
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qspiSend(devp->config->qspip, &cmd_write_evconf, 1, evconf_value);
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{
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uint8_t id[3];
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/* Reading ID again for confirmation.*/
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flash_cmd_receive(devp, M25Q_CMD_MULTIPLE_IO_READ_ID, 3, id);
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/* Checking if the device is white listed.*/
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osalDbgAssert(memcmp(id, devp->device_id, 3) == 0,
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"id confirmation failed");
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}
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#endif
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flash_cmd_receive(devp, M25Q_CMD_READ_ID, 3, id);
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/* Setting up the device size.*/
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descriptor.sectors_count = (1U << (size_t)devp->device_id[2]) / SECTOR_SIZE;
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flash_cmd_receive(devp, M25Q_CMD_READ_ID, 3, id);
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/* Reading device ID.*/
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qspiReceive(devp->config->qspip, &cmd_read_id, 3, id);
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/* Reset Enable command.*/
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// flash_short_cmd(devp, M25Q_CMD_RESET_ENABLE);
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/* Reset Memory command.*/
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// flash_short_cmd(devp, M25Q_CMD_RESET_MEMORY);
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#if (M25Q_BUS_MODE != M25Q_BUS_MODE_SPI)
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/* Setting up the dummy cycles to be used for rast read operations.*/
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flash_cmd(devp, M25Q_CMD_WRITE_ENABLE);
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flash_cmd_send(devp, M25Q_CMD_WRITE_V_CONF_REGISTER,
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1, flash_status);
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#endif
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/* Driver in ready state.*/
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devp->state = FLASH_READY;
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/* Bus release.*/
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@ -617,6 +744,8 @@ void m25qStop(M25QDriver *devp) {
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#endif
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devp->config = NULL;
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/* Driver stopped.*/
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devp->state = FLASH_STOP;
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/* Bus release.*/
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@ -41,9 +41,10 @@
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#define M25Q_CMD_RESET_ENABLE 0x66
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#define M25Q_CMD_RESET_MEMORY 0x99
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#define M25Q_CMD_READ_ID 0x9F
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#define M25Q_CMD_MULTIPLE_IO_READ_ID 0xAF
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#define M25Q_CMD_READ_DISCOVERY_PARAMETER 0x5A
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#define M25Q_CMD_READ 0x03
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#define M25Q_CMD_FAST_READ 0x08
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#define M25Q_CMD_FAST_READ 0x0B
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#define M25Q_CMD_WRITE_ENABLE 0x06
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#define M25Q_CMD_WRITE_DISABLE 0x04
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#define M25Q_CMD_READ_STATUS_REGISTER 0x05
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@ -111,6 +112,15 @@
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#define M25Q_BUS_MODE M25Q_BUS_MODE_QSPI4L
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#endif
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/**
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* @brief Number of dummy cycles for fast read (1..15).
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* @details This is the number of dummy cycles to be used for fast read
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* operations.
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*/
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#if !defined(M25Q_READ_DUMMY_CYCLES) || defined(__DOXYGEN__)
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#define M25Q_READ_DUMMY_CYCLES 8
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#endif
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/**
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* @brief Switch QSPI bus width on initialization.
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* @details A bus width initialization is performed by writing the
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@ -185,6 +195,17 @@
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#error "M25Q_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION"
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#endif
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#if (M25Q_BUS_MODE != M25Q_BUS_MODE_SPI) && \
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(M25Q_BUS_MODE != M25Q_BUS_MODE_QSPI1L) && \
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(M25Q_BUS_MODE != M25Q_BUS_MODE_QSPI2L) && \
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(M25Q_BUS_MODE != M25Q_BUS_MODE_QSPI4L)
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#error "invalid M25Q_BUS_MODE selected"
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#endif
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#if (M25Q_READ_DUMMY_CYCLES < 1) || (M25Q_READ_DUMMY_CYCLES > 15)
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#error "invalid M25Q_READ_DUMMY_CYCLES value (1..15)"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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@ -250,6 +271,10 @@ typedef struct {
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*/
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uint32_t qspi_mode;
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#endif
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/**
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* @brief Device ID and unique ID.
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*/
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uint8_t device_id[20];
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} M25QDriver;
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/*===========================================================================*/
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@ -211,6 +211,22 @@ void qspi_lld_stop(QSPIDriver *qspip) {
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*/
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void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {
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#if STM32_USE_STM32_D1_WORKAROUND == TRUE
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/* If it is a command without address and alternate phases then the command
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is sent as an alternate byte, the command phase is suppressed.*/
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if ((cmdp->cfg & (QSPI_CFG_ADDR_MODE_MASK | QSPI_CFG_ALT_MODE_MASK)) == 0U) {
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uint32_t cfg;
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/* The command mode field is copied in the alternate mode field. All
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other fields are not used in this scenario.*/
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cfg = (cmdp->cfg & QSPI_CFG_CMD_MODE_MASK) << 6U;
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qspip->qspi->DLR = 0U;
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qspip->qspi->ABR = cmdp->cfg & QSPI_CFG_CMD_MASK;
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qspip->qspi->CCR = cfg;
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return;
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}
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#endif
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qspip->qspi->DLR = 0U;
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qspip->qspi->ABR = cmdp->alt;
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qspip->qspi->CCR = cmdp->cfg;
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@ -31,6 +31,17 @@
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name DCR register options
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* @{
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*/
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#define STM32_DCR_CK_MODE (1U << 0U)
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#define STM32_DCR_CSHT_MASK (7U << 8U)
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#define STM32_DCR_CSHT(n) ((n) << 8U)
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#define STM32_DCR_FSIZE_MASK (31U << 16U)
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#define STM32_DCR_FSIZE(n) ((n) << 16U)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -85,6 +96,17 @@
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#if !defined(STM32_QSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_QSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
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#endif
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/**
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* @brief Enables a workaround for a STM32L476 QUADSPI errata.
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* @details The document DM00111498 states: "QUADSPI_BK1_IO1 is always an
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* input when the command is sent in dual or quad SPI mode".
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* This workaround makes commands without address or data phases
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* to be sent as alternate bytes.
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*/
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#if !defined(STM32_USE_STM32_D1_WORKAROUND) || defined(__DOXYGEN__)
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#define STM32_USE_STM32_D1_WORKAROUND TRUE
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#endif
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/** @} */
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/*===========================================================================*/
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@ -33,7 +33,7 @@
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<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
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<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
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<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="id[2]-id-m25qStart-(format)" val="4"/><content id="id[1]-id-m25qStart-(format)" val="4"/><content id="id[0]-id-m25qStart-(format)" val="4"/><content id="cr2-adc_lld_start_conversion-(format)" val="4"/><content id="CR2-adc-null-port_wait_for_interrupt-(format)" val="4"/><content id="CR2-adc-adcp-adc_lld_start_conversion-(format)" val="4"/><content id="cfg-cmdp-qspiSend-(format)" val="4"/><content id="CR-qspi-qspip-qspi_lld_send-(format)" val="4"/><content id="CCR-qspi-qspip-qspi_lld_send-(format)" val="4"/><content id="cfg-cmdp-qspiReceive-(format)" val="4"/><content id="r2-(format)" val="4"/></contentList>"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="CCR-qspi-qspip-qspi_lld_receive-(format)" val="4"/><content id="cfg-cmdp-qspi_lld_receive-(format)" val="4"/><content id="id[2]-id-m25qStart-(format)" val="4"/><content id="id[1]-id-m25qStart-(format)" val="4"/><content id="id[0]-id-m25qStart-(format)" val="4"/><content id="AFRL-gpiop-initgpio-(format)" val="4"/><content id="AFRH-gpiop-initgpio-(format)" val="4"/><content id="ODR-gpiop-initgpio-(format)" val="4"/><content id="IDR-gpiop-initgpio-(format)" val="4"/><content id="PUPDR-gpiop-initgpio-(format)" val="4"/><content id="OSPEEDR-gpiop-initgpio-(format)" val="4"/><content id="MODER-gpiop-initgpio-(format)" val="4"/><content id="afrh-config-initgpio-(format)" val="4"/><content id="moder-config-initgpio-(format)" val="4"/><content id="config-initgpio-(format)" val="4"/><content id="r2-(format)" val="4"/><content id="cfg-cmdp-qspiReceive-(format)" val="4"/><content id="CCR-qspi-qspip-qspi_lld_send-(format)" val="4"/><content id="CR-qspi-qspip-qspi_lld_send-(format)" val="4"/><content id="cfg-cmdp-qspiSend-(format)" val="4"/><content id="CR2-adc-adcp-adc_lld_start_conversion-(format)" val="4"/><content id="CR2-adc-null-port_wait_for_interrupt-(format)" val="4"/><content id="cr2-adc_lld_start_conversion-(format)" val="4"/><content id="cmd-flash_cmd_receive-(format)" val="4"/></contentList>"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
|
||||
const QSPIConfig qspicfg1 = {
|
||||
NULL,
|
||||
0
|
||||
STM32_DCR_FSIZE(24) | STM32_DCR_CSHT(1)
|
||||
};
|
||||
|
||||
qspi_command_t cmd_read_id = {
|
||||
|
|
@ -63,6 +63,7 @@ static THD_FUNCTION(Thread1, arg) {
|
|||
* Application entry point.
|
||||
*/
|
||||
int main(void) {
|
||||
flash_error_t err;
|
||||
|
||||
/*
|
||||
* System initializations.
|
||||
|
|
@ -89,8 +90,11 @@ int main(void) {
|
|||
*/
|
||||
m25qObjectInit(&m25q);
|
||||
m25qStart(&m25q, &m25qcfg1);
|
||||
// qspiStart(&QSPID1, &qspicfg1);
|
||||
// qspiReceive(&QSPID1, &cmd_read_id, 17, buffer);
|
||||
|
||||
/* Reading it back.*/
|
||||
err = flashRead(&m25q, 0, buffer, 128);
|
||||
if (err != FLASH_NO_ERROR)
|
||||
chSysHalt("read error");
|
||||
|
||||
/*
|
||||
* Normal main() thread activity, in this demo it does nothing.
|
||||
|
|
|
|||
Loading…
Reference in New Issue