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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7810 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
Giovanni Di Sirio 2015-03-26 11:12:55 +00:00
parent e54e465a69
commit a3e2fd3089
19 changed files with 146 additions and 100 deletions
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6
os/common/ports/ARMCMx/devices/K20x/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M4
#define CORTEX_MODEL 4
/**
* @brief Systick unit presence.
@ -67,6 +67,10 @@
assembler source files. We verify that the info matches instead.*/
#include "mk20d5.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif

6
os/common/ports/ARMCMx/devices/KL2x/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M0PLUS
#define CORTEX_MODEL 0
/**
* @brief Systick unit presence.
@ -67,6 +67,10 @@
assembler source files. We verify that the info matches instead.*/
#include "kl25z.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif

6
os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M0
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
@ -74,6 +74,10 @@
assembler source files. We verify that the info matches instead.*/
#include "stm32f0xx.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif

6
os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
#define CORTEX_MODEL 3
/**
* @brief Floating Point unit presence.
@ -65,8 +65,8 @@
assembler source files. We verify that the info matches instead.*/
#include "stm32f10x.h"
#if !CORTEX_HAS_FPU != !__FPU_PRESENT
#error "CMSIS __FPU_PRESENT mismatch"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

6
os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M4
#define CORTEX_MODEL 4
/**
* @brief Floating Point unit presence.
@ -74,6 +74,10 @@
assembler source files. We verify that the info matches instead.*/
#include "stm32f3xx.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_HAS_FPU != __FPU_PRESENT
#error "CMSIS __FPU_PRESENT mismatch"
#endif

6
os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M4
#define CORTEX_MODEL 4
/**
* @brief Floating Point unit presence.
@ -74,6 +74,10 @@
assembler source files. We verify that the info matches instead.*/
#include "stm32f4xx.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_HAS_FPU != __FPU_PRESENT
#error "CMSIS __FPU_PRESENT mismatch"
#endif

6
os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M0PLUS
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
@ -71,6 +71,10 @@
assembler source files. We verify that the info matches instead.*/
#include "stm32l0xx.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif

6
os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h
View File

@ -34,7 +34,7 @@
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
#define CORTEX_MODEL 3
/**
* @brief Floating Point unit presence.
@ -69,8 +69,8 @@
assembler source files. We verify that the info matches instead.*/
#include "stm32l1xx.h"
#if !CORTEX_HAS_FPU != !__FPU_PRESENT
#error "CMSIS __FPU_PRESENT mismatch"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

20
os/hal/osal/nil/osal.h
View File

@ -109,6 +109,21 @@
#endif
/** @} */
/**
* @name IRQ-related constants
* @{
*/
/**
* @brief Total priority levels.
*/
#define OSAL_IRQ_PRIORITY_LEVELS CORTEX_PRIORITY_LEVELS
/**
* @brief Highest IRQ priority for HAL drivers.
*/
#define OSAL_IRQ_MAXIMUM_PRIORITY CORTEX_MAX_KERNEL_PRIORITY
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
@ -277,6 +292,11 @@ typedef struct {
* @name IRQ service routines wrappers
* @{
*/
/**
* @brief Priority level verification macro.
*/
#define OSAL_IRQ_IS_VALID_PRIORITY(n) CORTEX_IS_VALID_KERNEL_PRIORITY(n)
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers.

2
os/hal/osal/os-less/ARMCMx/osal.c
View File

@ -368,7 +368,7 @@ msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
osalDbgCheck(tqp != NULL);
(void)time;
(void)timeout;
return MSG_OK;
}

43
os/hal/osal/os-less/ARMCMx/osal.h
View File

@ -99,6 +99,25 @@
#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
/** @} */
/**
* @name IRQ-related constants
* @{
*/
/**
* @brief Total priority levels.
*/
#define OSAL_IRQ_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS)
/**
* @brief Highest IRQ priority for HAL drivers.
*/
#if (CORTEX_MODEL == 0) || defined(__DOXYGEN__)
#define OSAL_IRQ_MAXIMUM_PRIORITY 0
#else
#define OSAL_IRQ_MAXIMUM_PRIORITY 1
#endif
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
@ -333,6 +352,12 @@ typedef struct {
* @name IRQ service routines wrappers
* @{
*/
/**
* @brief Priority level verification macro.
*/
#define OSAL_IRQ_IS_VALID_PRIORITY(n) \
(((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers.
@ -510,10 +535,10 @@ static inline void osalSysEnable(void) {
*/
static inline void osalSysLock(void) {
#if CORTEX_MODEL == CORTEX_M0
#if CORTEX_MODEL == 0
__disable_irq();
#else
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
__set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);
#endif
}
@ -525,7 +550,7 @@ static inline void osalSysLock(void) {
*/
static inline void osalSysUnlock(void) {
#if CORTEX_MODEL == CORTEX_M0
#if CORTEX_MODEL == 0
__enable_irq();
#else
__set_BASEPRI(0);
@ -540,10 +565,10 @@ static inline void osalSysUnlock(void) {
*/
static inline void osalSysLockFromISR(void) {
#if CORTEX_MODEL == CORTEX_M0
#if CORTEX_MODEL == 0
__disable_irq();
#else
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
__set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);
#endif
}
@ -555,7 +580,7 @@ static inline void osalSysLockFromISR(void) {
*/
static inline void osalSysUnlockFromISR(void) {
#if CORTEX_MODEL == CORTEX_M0
#if CORTEX_MODEL == 0
__enable_irq();
#else
__set_BASEPRI(0);
@ -578,12 +603,12 @@ static inline void osalSysUnlockFromISR(void) {
static inline syssts_t osalSysGetStatusAndLockX(void) {
syssts_t sts;
#if CORTEX_MODEL == CORTEX_M0
#if CORTEX_MODEL == 0
sts = (syssts_t)__get_PRIMASK();
__disable_irq();
#else
sts = (syssts_t)__get_BASEPRI();
__set_BASEPRI(CORTEX_BASEPRI_KERNEL);
__set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);
#endif
return sts;
}
@ -599,7 +624,7 @@ static inline syssts_t osalSysGetStatusAndLockX(void) {
*/
static inline void osalSysRestoreStatusX(syssts_t sts) {
#if CORTEX_MODEL == CORTEX_M0
#if CORTEX_MODEL == 0
if ((sts & (syssts_t)1) == (syssts_t)0) {
__enable_irq();
}

20
os/hal/osal/rt/osal.h
View File

@ -105,6 +105,21 @@
#endif
/** @} */
/**
* @name IRQ-related constants
* @{
*/
/**
* @brief Total priority levels.
*/
#define OSAL_IRQ_PRIORITY_LEVELS CORTEX_PRIORITY_LEVELS
/**
* @brief Highest IRQ priority for HAL drivers.
*/
#define OSAL_IRQ_MAXIMUM_PRIORITY CORTEX_MAX_KERNEL_PRIORITY
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
@ -269,6 +284,11 @@ typedef struct {
* @name IRQ service routines wrappers
* @{
*/
/**
* @brief Priority level verification macro.
*/
#define OSAL_IRQ_IS_VALID_PRIORITY(n) CORTEX_IS_VALID_KERNEL_PRIORITY(n)
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers.

21
os/hal/templates/osal/osal.h
View File

@ -96,6 +96,21 @@
#define OSAL_ST_MODE OSAL_ST_MODE_PERIODIC
/** @} */
/**
* @name IRQ-related constants
* @{
*/
/**
* @brief Total priority levels.
*/
#define OSAL_IRQ_PRIORITY_LEVELS 16U
/**
* @brief Highest IRQ priority for HAL drivers.
*/
#define OSAL_IRQ_MAXIMUM_PRIORITY 0U
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
@ -272,6 +287,12 @@ typedef struct {
* @name IRQ service routines wrappers
* @{
*/
/**
* @brief Priority level verification macro.
*/
#define OSAL_IRQ_IS_VALID_PRIORITY(n) \
(((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers.

37
os/nil/ports/ARMCMx/nilcore.h
View File

@ -66,17 +66,6 @@
/** @} */
/**
* @name Cortex-M variants
* @{
*/
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
#define CORTEX_M0PLUS 1 /**< @brief Cortex-M0+ variant. */
#define CORTEX_M1 10 /**< @brief Cortex-M1 variant. */
#define CORTEX_M3 30 /**< @brief Cortex-M3 variant. */
#define CORTEX_M4 40 /**< @brief Cortex-M4 variant. */
/** @} */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
@ -98,27 +87,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/*
* Inclusion of the appropriate CMSIS header for the selected device.
*/
#if CORTEX_MODEL == CORTEX_M0
#include "core_cm0.h"
#elif CORTEX_MODEL == CORTEX_M0PLUS
#include "core_cm0plus.h"
#elif CORTEX_MODEL == CORTEX_M3
#include "core_cm3.h"
#elif CORTEX_MODEL == CORTEX_M4
#include "core_cm4.h"
#else
#error "unknown or unsupported Cortex-M model"
#endif
#endif /* !defined(_FROM_ASM_) */
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
@ -211,10 +179,9 @@ struct port_intctx {};
/*===========================================================================*/
/* Includes the sub-architecture-specific part.*/
#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) || \
(CORTEX_MODEL == CORTEX_M1)
#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1)
#include "nilcore_v6m.h"
#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)
#include "nilcore_v7m.h"
#endif

5
os/nil/ports/ARMCMx/nilcore_v6m.h
View File

@ -99,7 +99,8 @@
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \
defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
@ -115,7 +116,7 @@
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M0"
#elif (CORTEX_MODEL == CORTEX_M0PLUS)
#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT)
#define PORT_ARCHITECTURE_ARM_v6M
#define PORT_ARCHITECTURE_NAME "ARMv6-M"
#define PORT_CORE_VARIANT_NAME "Cortex-M0+"

4
os/nil/ports/ARMCMx/nilcore_v7m.h
View File

@ -139,7 +139,7 @@
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
@ -155,7 +155,7 @@
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M4)
#elif (CORTEX_MODEL == 4)
#define PORT_ARCHITECTURE_ARM_v7ME
#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
#if CORTEX_USE_FPU

37
os/rt/ports/ARMCMx/chcore.h
View File

@ -66,17 +66,6 @@
/** @} */
/**
* @name Cortex-M variants
* @{
*/
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
#define CORTEX_M0PLUS 1 /**< @brief Cortex-M0+ variant. */
#define CORTEX_M1 10 /**< @brief Cortex-M1 variant. */
#define CORTEX_M3 30 /**< @brief Cortex-M3 variant. */
#define CORTEX_M4 40 /**< @brief Cortex-M4 variant. */
/** @} */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
@ -98,27 +87,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/*
* Inclusion of the appropriate CMSIS header for the selected device.
*/
#if CORTEX_MODEL == CORTEX_M0
#include "core_cm0.h"
#elif CORTEX_MODEL == CORTEX_M0PLUS
#include "core_cm0plus.h"
#elif CORTEX_MODEL == CORTEX_M3
#include "core_cm3.h"
#elif CORTEX_MODEL == CORTEX_M4
#include "core_cm4.h"
#else
#error "unknown or unsupported Cortex-M model"
#endif
#endif /* !defined(_FROM_ASM_) */
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
@ -221,10 +189,9 @@ struct context {
/*===========================================================================*/
/* Includes the sub-architecture-specific part.*/
#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) || \
(CORTEX_MODEL == CORTEX_M1)
#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1)
#include "chcore_v6m.h"
#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)
#include "chcore_v7m.h"
#endif

5
os/rt/ports/ARMCMx/chcore_v6m.h
View File

@ -99,7 +99,8 @@
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \
defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
@ -115,7 +116,7 @@
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M0"
#elif (CORTEX_MODEL == CORTEX_M0PLUS)
#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT)
#define PORT_ARCHITECTURE_ARM_v6M
#define PORT_ARCHITECTURE_NAME "ARMv6-M"
#define PORT_CORE_VARIANT_NAME "Cortex-M0+"

4
os/rt/ports/ARMCMx/chcore_v7m.h
View File

@ -139,7 +139,7 @@
* @name Architecture and Compiler
* @{
*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
@ -155,7 +155,7 @@
*/
#define PORT_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M4)
#elif (CORTEX_MODEL == 4)
#define PORT_ARCHITECTURE_ARM_v7ME
#define PORT_ARCHITECTURE_NAME "ARMv7-ME"
#if CORTEX_USE_FPU