From a41f12ad8a925c8baaaeb826e63589721f942f4a Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 14 Jan 2012 12:23:42 +0000 Subject: [PATCH] RTC. Added possibility of changing RTC clock source. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3809 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/RTCv1/rtc_lld.c | 4 +++ os/hal/platforms/STM32F1xx/hal_lld.c | 29 ++++++++++--------- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 1 + os/hal/platforms/STM32F1xx/hal_lld_f103.h | 1 + .../platforms/STM32F1xx/hal_lld_f105_f107.h | 1 + testhal/STM32F1xx/RTC/main.c | 10 +------ 6 files changed, 24 insertions(+), 22 deletions(-) diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c index 811920e06..4344f17bb 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -101,6 +101,10 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { CH_IRQ_PROLOGUE(); + /* This wait works only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases it does nothing.*/ + rtc_lld_apb1_sync(); + /* Mask of all enabled and pending sources.*/ flags = RTC->CRH & RTC->CRL; RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index f903106cb..75afa0a84 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -43,22 +43,25 @@ /** * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. */ static void hal_lld_backup_domain_init(void) { /* Backup domain access enabled and left open.*/ - PWR->CR = PWR_CR_DBP; + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } /* If enabled then the LSE is started.*/ #if STM32_LSE_ENABLED - if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - RCC->BDCR = RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ - } + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ #endif #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK @@ -66,7 +69,7 @@ static void hal_lld_backup_domain_init(void) { initialization.*/ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { /* Selects clock source.*/ - RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL; + RCC->BDCR |= STM32_RTCSEL; /* RTC clock enabled.*/ RCC->BDCR |= RCC_BDCR_RTCEN; @@ -213,7 +216,7 @@ void stm32_clock_init(void) { /* HSE activation.*/ RCC->CR |= RCC_CR_HSEON; while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ + ; /* Waits until HSE is stable. */ #endif #if STM32_LSI_ENABLED @@ -231,14 +234,14 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLL2 RCC->CR |= RCC_CR_PLL2ON; while (!(RCC->CR & RCC_CR_PLL2RDY)) - ; /* Waits until PLL2 is stable. */ + ; /* Waits until PLL2 is stable. */ #endif /* PLL3 setup, if activated.*/ #if STM32_ACTIVATE_PLL3 RCC->CR |= RCC_CR_PLL3ON; while (!(RCC->CR & RCC_CR_PLL3RDY)) - ; /* Waits until PLL3 is stable. */ + ; /* Waits until PLL3 is stable. */ #endif /* PLL1 setup, if activated.*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 766e9e48a..c30f2a7dc 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -174,6 +174,7 @@ #define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as RTC clock. */ +#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */ /** @} */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 39b13cf38..b8aa67374 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -184,6 +184,7 @@ #define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as RTC clock. */ +#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */ /** @} */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 8e63ebaf3..53bebc3b2 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -194,6 +194,7 @@ #define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as RTC clock. */ +#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */ /** @} */ /** diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c index 5797f4235..fb58594ae 100644 --- a/testhal/STM32F1xx/RTC/main.c +++ b/testhal/STM32F1xx/RTC/main.c @@ -26,13 +26,8 @@ RTCAlarm alarmspec; #define TEST_ALARM_WAKEUP FALSE -#if TEST_ALARM_WAKEUP -static void my_cb(RTCDriver *rtcp, rtcevent_t event) { - (void)rtcp; - (void)event; - return; -} +#if TEST_ALARM_WAKEUP /* sleep indicator thread */ static WORKING_AREA(blinkWA, 128); @@ -55,9 +50,6 @@ int main(void) { alarmspec.tv_sec = timespec.tv_sec + 30; rtcSetAlarm(&RTCD1, 0, &alarmspec); - /* Needed just to switch interrupts on.*/ - rtcSetCallback(&RTCD1, my_cb); - while (TRUE){ chThdSleepSeconds(10); chSysLock();