andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Renamed Clock Control API for ADuCM36x 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13106 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Rocco Marco Guglielmi 2019-10-16 12:51:17 +00:00
parent cff2f67711
commit a4caa90fb3
1 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
os/hal/ports/ADUCM/ADUCM36x/aducm_cc.h
View File

@ -113,18 +113,18 @@
* @{
*/
/**
* @brief Enables the UART peripheral clock.
* @brief Enables the UART0 peripheral clock.
*
* @api
*/
#define ccEnableUART() ccEnableClk(CLKDIS_DISUARTCLK)
#define ccEnableUART0() ccEnableClk(CLKDIS_DISUARTCLK)
/**
* @brief Disables the UART peripheral clock.
* @brief Disables the UART0 peripheral clock.
*
* @api
*/
#define ccDisableUART() ccDisableClk(CLKDIS_DISUARTCLK)
#define ccDisableUART0() ccDisableClk(CLKDIS_DISUARTCLK)
/** @} */
/**
@ -132,18 +132,18 @@
* @{
*/
/**
* @brief Enables the PWM peripheral clock.
* @brief Enables the PWM0 peripheral clock.
*
* @api
*/
#define ccEnablePWM() ccEnableClk(CLKDIS_DISPWMCLK)
#define ccEnablePWM0() ccEnableClk(CLKDIS_DISPWMCLK)
/**
* @brief Disables the PWM peripheral clock.
* @brief Disables the PWM0 peripheral clock.
*
* @api
*/
#define ccDisablePWM() ccDisableClk(CLKDIS_DISPWMCLK)
#define ccDisablePWM0() ccDisableClk(CLKDIS_DISPWMCLK)
/** @} */
/**
@ -184,18 +184,18 @@
* @{
*/
/**
* @brief Enables the DAC peripheral clock.
* @brief Enables the DAC0 peripheral clock.
*
* @api
*/
#define ccEnableDAC() ccEnableClk(CLKDIS_DISDACCLK)
#define ccEnableDAC0() ccEnableClk(CLKDIS_DISDACCLK)
/**
* @brief Disables the DAC peripheral clock.
* @brief Disables the DAC0 peripheral clock.
*
* @api
*/
#define ccDisableDAC() ccDisableClk(CLKDIS_DISDACCLK)
#define ccDisableDAC0() ccDisableClk(CLKDIS_DISDACCLK)
/** @} */
/**
@ -203,18 +203,18 @@
* @{
*/
/**
* @brief Enables the DMA peripheral clock.
* @brief Enables the DMA0 peripheral clock.
*
* @api
*/
#define ccEnableDMA() ccEnableClk(CLKDIS_DISDMACLK)
#define ccEnableDMA0() ccEnableClk(CLKDIS_DISDMACLK)
/**
* @brief Disables the DMA peripheral clock.
* @brief Disables the DMA0 peripheral clock.
*
* @api
*/
#define ccDisableDMA() ccDisableClk(CLKDIS_DISDMACLK)
#define ccDisableDMA0() ccDisableClk(CLKDIS_DISDMACLK)
/** @} */
/**
@ -222,18 +222,18 @@
* @{
*/
/**
* @brief Enables the ADC peripheral clock.
* @brief Enables the ADCs peripheral clock.
*
* @api
*/
#define ccEnableADC() ccEnableClk(CLKDIS_DISADCCLK)
#define ccEnableADCs() ccEnableClk(CLKDIS_DISADCCLK)
/**
* @brief Disables the ADC peripheral clock.
* @brief Disables the ADCs peripheral clock.
*
* @api
*/
#define ccDisableADC() ccDisableClk(CLKDIS_DISADCCLK)
#define ccDisableADCs() ccDisableClk(CLKDIS_DISADCCLK)
/** @} */
/*===========================================================================*/