From a593b93b1933061f49b6898996bd0a642186d834 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 25 Oct 2023 14:55:44 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16402 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h | 89 +++++++++++++++++++- 1 file changed, 85 insertions(+), 4 deletions(-) diff --git a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h index abedfe5b1..ea1c08333 100644 --- a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h +++ b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h @@ -35,9 +35,9 @@ * @name GPDMA registers helpers * @{ */ -#define STM32_GPDMA_CLBAR_CLA_POS DMA_CLBAR_LBA_Pos -#define STM32_GPDMA_CLBAR_CLA_MASK (1U << STM32_GPDMA_CLBAR_CLA_POS) -#define STM32_GPDMA_CLBAR_CLA(n) ((n) << STM32_GPDMA_CLBAR_CLA_POS) +#define STM32_GPDMA_CLBAR_LBA_POS DMA_CLBAR_LBA_Pos +#define STM32_GPDMA_CLBAR_LBA_MASK (0xFFFFU << STM32_GPDMA_CLBAR_LBA_POS) +#define STM32_GPDMA_CLBAR_LBA(n) ((n) << STM32_GPDMA_CLBAR_LBA_POS) #define STM32_GPDMA_CFCR_TOF DMA_CFCR_TOF #define STM32_GPDMA_CFCR_SUSPF DMA_CFCR_SUSPF @@ -48,7 +48,7 @@ #define STM32_GPDMA_CFCR_TCF DMA_CFCR_TCF #define STM32_GPDMA_CSR_FIFOL_POS DMA_CSR_FIFOL_Pos -#define STM32_GPDMA_CSR_FIFOL_MASK (1U << STM32_GPDMA_CSR_FIFOL_POS) +#define STM32_GPDMA_CSR_FIFOL_MASK (0x7FU << STM32_GPDMA_CSR_FIFOL_POS) #define STM32_GPDMA_CSR_FIFOL(n) ((n) << STM32_GPDMA_CSR_FIFOL_POS) #define STM32_GPDMA_CSR_TOF DMA_CSR_TOF #define STM32_GPDMA_CSR_SUSPF DMA_CSR_SUSPF @@ -62,6 +62,87 @@ DMA_CSR_USEF | DMA_CSR_ULEF | \ DMA_CSR_DTEF | DMA_CSR_HTF | \ DMA_CSR_TCF) + +#define STM32_GPDMA_CR_PRIO_POS DMA_CCR_PRIO_Pos +#define STM32_GPDMA_CR_PRIO_MASK (3U << STM32_GPDMA_CR_PRIO_POS) +#define STM32_GPDMA_CR_PRIO(n) ((n) << STM32_GPDMA_CR_PRIO_POS) +#define STM32_GPDMA_CR_LAP DMA_CCR_LAP +#define STM32_GPDMA_CR_LSM DMA_CCR_LSM +#define STM32_GPDMA_CR_TOIE DMA_CCR_TOIE +#define STM32_GPDMA_CR_SUSPIE DMA_CCR_SUSPIE +#define STM32_GPDMA_CR_USEIE DMA_CCR_USEIE +#define STM32_GPDMA_CR_ULEIE DMA_CCR_ULEIE +#define STM32_GPDMA_CR_DTEIE DMA_CCR_DTEIE +#define STM32_GPDMA_CR_HTIE DMA_CCR_HTIE +#define STM32_GPDMA_CR_TCIE DMA_CCR_TCIE +#define STM32_GPDMA_CR_SUSP DMA_CCR_SUSP +#define STM32_GPDMA_CR_RESET DMA_CCR_RESET +#define STM32_GPDMA_CR_EN DMA_CCR_EN + +#define STM32_GPDMA_CTR1_DSEC DMA_CTR1_DSEC +#define STM32_GPDMA_CTR1_DAP DMA_CTR1_DAP +#define STM32_GPDMA_CTR1_DHX DMA_CTR1_DHX +#define STM32_GPDMA_CTR1_DBX DMA_CTR1_DBX +#define STM32_GPDMA_CTR1_DBL_POS DMA_CTR1_DBL_1_Pos +#define STM32_GPDMA_CTR1_DBL_MASK (0x3FU << STM32_GPDMA_CTR1_DBL_POS) +#define STM32_GPDMA_CTR1_DBL(n) ((n) << STM32_GPDMA_CTR1_DBL_POS) +#define STM32_GPDMA_CTR1_DINC DMA_CTR1_DINC +#define STM32_GPDMA_CTR1_DDW_LOG2_POS DMA_CTR1_DDW_LOG2_Pos +#define STM32_GPDMA_CTR1_DDW_LOG2_MASK (3U << STM32_GPDMA_CTR1_DDW_LOG2_POS) +#define STM32_GPDMA_CTR1_DDW_LOG2(n) ((n) << STM32_GPDMA_CTR1_DDW_LOG2_POS) +#define STM32_GPDMA_CTR1_DDW_BYTE(n) STM32_GPDMA_CTR1_DDW_LOG2(0U) +#define STM32_GPDMA_CTR1_DDW_HALF(n) STM32_GPDMA_CTR1_DDW_LOG2(1U) +#define STM32_GPDMA_CTR1_DDW_WORD(n) STM32_GPDMA_CTR1_DDW_LOG2(2U) +#define STM32_GPDMA_CTR1_SSEC DMA_CTR1_SSEC +#define STM32_GPDMA_CTR1_SAP DMA_CTR1_SAP +#define STM32_GPDMA_CTR1_SBX DMA_CTR1_SBX +#define STM32_GPDMA_CTR1_PAM_POS DMA_CTR1_PAM_Pos +#define STM32_GPDMA_CTR1_PAM_MASK (3U << STM32_GPDMA_CTR1_PAM_POS) +#define STM32_GPDMA_CTR1_PAM(n) ((n) << STM32_GPDMA_CTR1_PAM_POS) +#define STM32_GPDMA_CTR1_SBL_POS DMA_CTR1_SBL_1_Pos +#define STM32_GPDMA_CTR1_SBL_MASK (0x3FU << STM32_GPDMA_CTR1_SBL_POS) +#define STM32_GPDMA_CTR1_SBL(n) ((n) << STM32_GPDMA_CTR1_SBL_POS) +#define STM32_GPDMA_CTR1_SINC DMA_CTR1_SINC +#define STM32_GPDMA_CTR1_SDW_LOG2_POS DMA_CTR1_SDW_LOG2_Pos +#define STM32_GPDMA_CTR1_SDW_LOG2_MASK (3U << STM32_GPDMA_CTR1_SDW_LOG2_POS) +#define STM32_GPDMA_CTR1_SDW_LOG2(n) ((n) << STM32_GPDMA_CTR1_SDW_LOG2_POS) +#define STM32_GPDMA_CTR1_SDW_BYTE(n) STM32_GPDMA_CTR1_SDW_LOG2(0U) +#define STM32_GPDMA_CTR1_SDW_HALF(n) STM32_GPDMA_CTR1_SDW_LOG2(1U) +#define STM32_GPDMA_CTR1_SDW_WORD(n) STM32_GPDMA_CTR1_SDW_LOG2(2U) + +#define STM32_GPDMA_CTR2_TCEM_POS DMA_CTR2_TCEM_Pos +#define STM32_GPDMA_CTR2_TCEM_MASK (3U << STM32_GPDMA_CTR2_TCEM_POS) +#define STM32_GPDMA_CTR2_TCEM(n) ((n) << STM32_GPDMA_CTR2_TCEM_POS) +#define STM32_GPDMA_CTR2_TRIGPOL_POS DMA_CTR2_TRIGPOL_Pos +#define STM32_GPDMA_CTR2_TRIGPOL_MASK (3U << STM32_GPDMA_CTR2_TRIGPOL_POS) +#define STM32_GPDMA_CTR2_TRIGPOL(n) ((n) << STM32_GPDMA_CTR2_TRIGPOL_POS) +#define STM32_GPDMA_CTR2_TRIGPOL_NOTRIG STM32_GPDMA_CTR2_TRIGPOL(0U) +#define STM32_GPDMA_CTR2_TRIGPOL_RISING STM32_GPDMA_CTR2_TRIGPOL(1U) +#define STM32_GPDMA_CTR2_TRIGPOL_FALLING STM32_GPDMA_CTR2_TRIGPOL(2U) +#define STM32_GPDMA_CTR2_TRIGSEL_POS DMA_CTR2_TRIGSEL_Pos +#define STM32_GPDMA_CTR2_TRIGSEL_MASK (0x3FU << STM32_GPDMA_CTR2_TRIGSEL_POS) +#define STM32_GPDMA_CTR2_TRIGSEL(n) ((n) << STM32_GPDMA_CTR2_TRIGSEL_POS) +#define STM32_GPDMA_CTR2_TRIGM_POS DMA_CTR2_TRIGM_Pos +#define STM32_GPDMA_CTR2_TRIGM_MASK (3U << STM32_GPDMA_CTR2_TRIGM_POS) +#define STM32_GPDMA_CTR2_TRIGM(n) ((n) << STM32_GPDMA_CTR2_TRIGM_POS) +#define STM32_GPDMA_CTR2_PFREQ DMA_CTR2_PFREQ +#define STM32_GPDMA_CTR2_BREQ DMA_CTR2_BREQ +#define STM32_GPDMA_CTR2_SWREQ DMA_CTR2_SWREQ +#define STM32_GPDMA_CTR2_REQSEL_POS DMA_CTR2_REQSEL_Pos +#define STM32_GPDMA_CTR2_REQSEL_MASK (0xFFU << STM32_GPDMA_CTR2_REQSEL_POS) +#define STM32_GPDMA_CTR2_REQSEL(n) ((n) << STM32_GPDMA_CTR2_REQSEL_POS) + +#define STM32_GPDMA_CBR1_BRDDEC DMA_CBR1_BRDDEC +#define STM32_GPDMA_CBR1_BRSDEC DMA_CBR1_BRSDEC +#define STM32_GPDMA_CBR1_DDEC DMA_CBR1_DDEC +#define STM32_GPDMA_CBR1_SDEC DMA_CBR1_SDEC +#define STM32_GPDMA_CBR1_BRC_POS DMA_CBR1_BRC_Pos +#define STM32_GPDMA_CBR1_BRC_MASK (0x7FFU << STM32_GPDMA_CBR1_BRC_POS) +#define STM32_GPDMA_CBR1_BRC(n) ((n) << STM32_GPDMA_CBR1_BRC_POS) +#define STM32_GPDMA_CBR1_BNDT_POS DMA_CBR1_BNDT_Pos +#define STM32_GPDMA_CBR1_BNDT_MASK (3U << STM32_GPDMA_CBR1_BNDT_POS) +#define STM32_GPDMA_CBR1_BNDT(n) ((n) << STM32_GPDMA_CBR1_BNDT_POS) + /** @< */ /**