andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8211 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2015-08-13 10:04:56 +00:00
parent d676c45571
commit a59a43bc28
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
os/hal/ports/STM32/STM32F7xx/hal_lld.c
View File

@ -133,13 +133,15 @@ void hal_lld_init(void) {
/* If the DMA is in use then the DMA-accessible RAM must be programmed as /* If the DMA is in use then the DMA-accessible RAM must be programmed as
Write Through using the MPU, region zero is used with a size of 512kB, Write Through using the MPU, region zero is used with a size of 512kB,
the sub-regions are programmed as follow: the sub-regions are programmed as follow:
- 0..4, enabled, it is the normal, DMA-accessible, RAM. - 0,, disabled, it is the normal the DTCM RAM.
- 1..4, enabled, it is the normal, DMA-accessible, RAM.
- 5..7, disabled, beyond RAM area. - 5..7, disabled, beyond RAM area.
The system memory layout is used as "background" for the MPU regions.*/ The system memory layout is used as "background" for the MPU regions.*/
mpuConfigureRegion(MPU_REGION_0, mpuConfigureRegion(MPU_REGION_0,
0x20000000U, 0x20000000U,
MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_CACHEABLE_WT_NWA | MPU_RASR_ATTR_CACHEABLE_WT_NWA |
MPU_RNR_REGION(1) |
MPU_RNR_REGION(5) | MPU_RNR_REGION(5) |
MPU_RNR_REGION(6) | MPU_RNR_REGION(6) |
MPU_RNR_REGION(7) | MPU_RNR_REGION(7) |