andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16342 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2023-07-26 09:33:27 +00:00
parent 4bd9b7adac
commit a9114efef8
8 changed files with 1157 additions and 1111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

553
demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/halconf.h Normal file
View File

@ -0,0 +1,553 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef HALCONF_H
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_8_4_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the cryptographic subsystem.
*/
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
#define HAL_USE_CRY FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EFlash subsystem.
*/
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
#define HAL_USE_EFL FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SIO subsystem.
*/
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
#define HAL_USE_SIO FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the TRNG subsystem.
*/
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
#define HAL_USE_TRNG FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/**
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#endif
/*===========================================================================*/
/* PAL driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
#define PAL_USE_CALLBACKS TRUE
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
#define PAL_USE_WAIT TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/**
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
*/
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
#define CAN_ENFORCE_USE_CALLBACKS FALSE
#endif
/*===========================================================================*/
/* CRY driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the SW fall-back of the cryptographic driver.
* @details When enabled, this option, activates a fall-back software
* implementation for algorithms not supported by the underlying
* hardware.
* @note Fall-back implementations may not be present for all algorithms.
*/
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_USE_FALLBACK FALSE
#endif
/**
* @brief Makes the driver forcibly use the fall-back implementations.
*/
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
#define HAL_CRY_ENFORCE_FALLBACK FALSE
#endif
/*===========================================================================*/
/* DAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
#define DAC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DAC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the zero-copy API.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Timeout before assuming a failure while waiting for card idle.
* @note Time is in milliseconds.
*/
#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__)
#define MMC_IDLE_TIMEOUT_MS 1000
#endif
/**
* @brief Mutual exclusion on the SPI bus.
*/
#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define MMC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/**
* @brief OCR initialization constant for V20 cards.
*/
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
#define SDC_INIT_OCR_V20 0x50FF8000U
#endif
/**
* @brief OCR initialization constant for non-V20 cards.
*/
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
#define SDC_INIT_OCR 0x80100000U
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SIO driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SIO_DEFAULT_BITRATE 38400
#endif
/**
* @brief Support for thread synchronization API.
*/
#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
#define SIO_USE_SYNCHRONIZATION TRUE
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Inserts an assertion on function errors before returning.
*/
#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__)
#define SPI_USE_ASSERT_ON_ERROR TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Handling method for SPI CS line.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
/*===========================================================================*/
/* WSPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
#define WSPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* HALCONF_H */
/** @} */

190
demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h Normal file
View File

@ -0,0 +1,190 @@
/*
ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32C0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32C0xx_MCUCONF
#define STM32C011_MCUCONF
#define STM32C031_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PWR_CR3 (PWR_CR3_EIWUL)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRD (0U)
#define STM32_PWR_PDCRD (0U)
#define STM32_PWR_PUCRF (0U)
#define STM32_PWR_PDCRF (0U)
#define STM32_HSIDIV_VALUE 1
#define STM32_HSIKER_VALUE 1
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_SW STM32_SW_PLLRCLK
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_MCO2SEL STM32_MCOSEL_NOCLOCK
#define STM32_MCO2PRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clocks and sources.
*/
#define STM32_USART1SEL STM32_USART1SEL_PCLK
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
/*
* Shared IRQ settings.
*/
#define STM32_IRQ_EXTI0_1_PRIORITY 3
#define STM32_IRQ_EXTI2_3_PRIORITY 3
#define STM32_IRQ_EXTI4_15_PRIORITY 3
#define STM32_IRQ_USART1_PRIORITY 2
#define STM32_IRQ_USART2_PRIORITY 2
#define STM32_IRQ_TIM1_UP_PRIORITY 1
#define STM32_IRQ_TIM1_CC_PRIORITY 1
#define STM32_IRQ_TIM3_PRIORITY 1
#define STM32_IRQ_TIM14_PRIORITY 1
#define STM32_IRQ_TIM16_PRIORITY 1
#define STM32_IRQ_TIM17_PRIORITY 1
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM3 FALSE
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM14 FALSE
#define STM32_PWM_USE_TIM16 FALSE
#define STM32_PWM_USE_TIM17 FALSE
/*
* RTC driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 2
#define STM32_ST_USE_TIMER 17
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */

623
os/hal/ports/STM32/STM32C0xx/hal_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file STM32G0xx+/hal_lld.c
* @brief STM32G0xx+ HAL subsystem low level driver source.
* @file STM32C0xx+/hal_lld.c
* @brief STM32C0xx+ HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
@ -31,27 +31,27 @@
/**
* @brief Number of thresholds in the wait states array.
*/
#define STM32_WS_THRESHOLDS 5
#define STM32_WS_THRESHOLDS 1
/**
* @brief Flash ACR reset value.
*/
#define STM32_FLASH_ACR_RESET (FLASH_ACR_DBG_SWEN | \
FLASH_ACR_ICEN | \
FLASH_ACR_LATENCY_0WS)
#define STM32_FLASH_ACR_RESET 0x00040600U
/**
* @brief RCC CR reset value.
*/
#define STM32_RCC_CR_RESET (RCC_CR_HSION)
#define STM32_RCC_CR_RESET 0x00000500U
/**
* @brief PWR CR bits safe for fast switch.
* @brief RCC CFGR reset value.
*/
#define STM32_PWR_CR1_SAFE_ONLY_MASK (PWR_CR1_FPD_LPSLP | \
PWR_CR1_FPD_LPRUN | \
PWR_CR1_FPD_STOP | \
PWR_CR1_LPMS_Msk)
#define STM32_RCC_CFGR_RESET 0x00000000U
/**
* @brief PWR CR1 reset value.
*/
#define STM32_PWR_CR1_RESET 0x00000208U
/*===========================================================================*/
/* Driver exported variables. */
@ -63,139 +63,10 @@
*/
uint32_t SystemCoreClock = STM32_HCLK;
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/**
* @brief Post-reset clock configuration.
*/
const halclkcfg_t hal_clkcfg_reset = {
.pwr_cr1 = PWR_CR1_VOS_0 | PWR_CR1_FPD_STOP,
#if defined (PWR_CR2_PVMEN_USB)
.pwr_cr2 = PWR_CR2_PVMEN_USB,
#else
.pwr_cr2 = 0U,
#endif
.rcc_cr = STM32_RCC_CR_RESET,
.rcc_cfgr = RCC_CFGR_SW_HSI,
.rcc_pllcfgr = 0U,
.flash_acr = STM32_FLASH_ACR_RESET
};
/**
* @brief Default clock configuration.
*/
const halclkcfg_t hal_clkcfg_default = {
.pwr_cr1 = STM32_VOS_RANGE1 | PWR_CR1_DBP,
#if defined (PWR_CR2_PVMEN_USB)
.pwr_cr2 = PWR_CR2_PVMEN_USB,
#else
.pwr_cr2 = 0U,
#endif
.rcc_cr = STM32_HSIDIV
#if STM32_HSI16_ENABLED
| RCC_CR_HSIKERON | RCC_CR_HSION
#endif
#if STM32_HSI48_ENABLED
| RCC_CR_HSI48ON
#endif
#if STM32_HSE_ENABLED
| RCC_CR_HSEON
#endif
#if STM32_ACTIVATE_PLL
| RCC_CR_PLLON
#endif
,
.rcc_cfgr = STM32_MCOPRE | STM32_MCOSEL |
STM32_PPRE | STM32_HPRE |
STM32_SW,
.rcc_pllcfgr = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC,
.flash_acr = FLASH_ACR_DBG_SWEN | FLASH_ACR_ICEN |
FLASH_ACR_PRFTEN | STM32_FLASHBITS
};
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/**
* @brief Dynamic clock points for this device.
*/
static halfreq_t clock_points[CLK_ARRAY_SIZE] = {
[CLK_SYSCLK] = STM32_SYSCLK,
[CLK_HSISYSCLK] = STM32_HSISYSCLK,
[CLK_PLLPCLK] = STM32_PLL_P_CLKOUT,
[CLK_PLLQCLK] = STM32_PLL_Q_CLKOUT,
[CLK_PLLRCLK] = STM32_PLL_R_CLKOUT,
[CLK_HCLK] = STM32_HCLK,
[CLK_PCLK] = STM32_PCLK,
[CLK_PCLKTIM] = STM32_TIMPCLK,
[CLK_MCO] = STM32_MCOCLK,
};
/**
* @brief Type of a structure representing system limits.
*/
typedef struct {
halfreq_t sysclk_max;
halfreq_t pllin_max;
halfreq_t pllin_min;
halfreq_t pllvco_max;
halfreq_t pllvco_min;
halfreq_t pllp_max;
halfreq_t pllp_min;
halfreq_t pllq_max;
halfreq_t pllq_min;
halfreq_t pllr_max;
halfreq_t pllr_min;
halfreq_t flash_thresholds[STM32_WS_THRESHOLDS];
} system_limits_t;
/**
* @brief System limits for VOS range 1.
*/
static const system_limits_t vos_range1 = {
.sysclk_max = STM32_VOS1_SYSCLK_MAX,
.pllin_max = STM32_VOS1_PLLIN_MAX,
.pllin_min = STM32_VOS1_PLLIN_MIN,
.pllvco_max = STM32_VOS1_PLLVCO_MAX,
.pllvco_min = STM32_VOS1_PLLVCO_MIN,
.pllp_max = STM32_VOS1_PLLP_MAX,
.pllp_min = STM32_VOS1_PLLP_MIN,
.pllq_max = STM32_VOS1_PLLQ_MAX,
.pllq_min = STM32_VOS1_PLLQ_MIN,
.pllr_max = STM32_VOS1_PLLR_MAX,
.pllr_min = STM32_VOS1_PLLR_MIN,
.flash_thresholds = {STM32_VOS1_0WS_THRESHOLD, STM32_VOS1_1WS_THRESHOLD,
STM32_VOS1_2WS_THRESHOLD, STM32_VOS1_3WS_THRESHOLD,
STM32_VOS1_4WS_THRESHOLD}
};
/**
* @brief System limits for VOS range 2.
*/
static const system_limits_t vos_range2 = {
.sysclk_max = STM32_VOS2_SYSCLK_MAX,
.pllin_max = STM32_VOS2_PLLIN_MAX,
.pllin_min = STM32_VOS2_PLLIN_MIN,
.pllvco_max = STM32_VOS2_PLLVCO_MAX,
.pllvco_min = STM32_VOS2_PLLVCO_MIN,
.pllp_max = STM32_VOS2_PLLP_MAX,
.pllp_min = STM32_VOS2_PLLP_MIN,
.pllq_max = STM32_VOS2_PLLQ_MAX,
.pllq_min = STM32_VOS2_PLLQ_MIN,
.pllr_max = STM32_VOS2_PLLR_MAX,
.pllr_min = STM32_VOS2_PLLR_MIN,
.flash_thresholds = {STM32_VOS2_0WS_THRESHOLD, STM32_VOS2_1WS_THRESHOLD,
STM32_VOS2_2WS_THRESHOLD, STM32_VOS2_3WS_THRESHOLD,
STM32_VOS2_4WS_THRESHOLD}
};
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
@ -217,7 +88,7 @@ __STATIC_INLINE void flash_set_acr(uint32_t acr) {
/**
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
* @note CR1 is not initialized inside this function.
*/
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
@ -265,370 +136,19 @@ __STATIC_INLINE void hal_lld_set_static_pwr(void) {
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL |
STM32_MCO2PRE | STM32_MCO2SEL |
STM32_PPRE | STM32_HPRE;
/* Set HSISYS divisor.*/
RCC->CR = (RCC->CR & ~STM32_HSIDIV_MASK) | STM32_HSIDIV;
/* Set HSISYS, HSIKER divisors.*/
RCC->CR = (RCC->CR & ~(STM32_HSIDIV_MASK | STM32_HSIKER_MASK)) |
STM32_HSIDIV | STM32_HSIKER;
#if STM32_RCC_HAS_CCIPR2
/* CCIPR register initialization.*/
RCC->CCIPR = STM32_ADCSEL | STM32_RNGDIV | STM32_RNGSEL |
STM32_TIM15SEL | STM32_TIM1SEL | STM32_LPTIM2SEL |
STM32_LPTIM1SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_CECSEL | STM32_USART3SEL | STM32_USART2SEL |
STM32_USART1SEL | STM32_LPUART2SEL | STM32_LPUART1SEL;
/* CCIPR2 register initialization.*/
RCC->CCIPR2 = STM32_USBSEL | STM32_FDCANSEL | STM32_I2S2SEL |
STM32_I2S1SEL;
#else
/* CCIPR register initialization.*/
RCC->CCIPR = STM32_ADCSEL | STM32_RNGDIV | STM32_RNGSEL |
STM32_TIM15SEL | STM32_TIM1SEL | STM32_LPTIM2SEL |
STM32_LPTIM1SEL | STM32_I2S1SEL | STM32_I2C1SEL |
STM32_CECSEL | STM32_USART3SEL | STM32_USART2SEL |
STM32_USART1SEL | STM32_LPUART2SEL | STM32_LPUART1SEL;
#endif
RCC->CCIPR = STM32_ADCSEL | STM32_I2S1SEL | STM32_I2C1SEL |
STM32_USART1SEL;
}
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/**
* @brief Recalculates the clock tree frequencies.
*
* @param[in] ccp pointer to clock a @p halclkcfg_t structure
* @return The frequency calculation result.
* @retval false if the clock settings look valid
* @retval true if the clock settings look invalid
*
* @notapi
*/
static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
static const uint32_t hprediv[16] = {1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U,
2U, 4U, 8U, 16U, 64U, 128U, 256U, 512U};
static const uint32_t pprediv[16] = {1U, 1U, 1U, 1U, 2U, 4U, 8U, 16U};
const system_limits_t *slp;
halfreq_t hsi16clk = 0U, hseclk = 0U, pllselclk, hsisysclk;
halfreq_t pllpclk = 0U, pllqclk = 0U, pllrclk = 0U;
halfreq_t sysclk, hclk, pclk, pclktim, mcoclk;
uint32_t mcodiv, flashws, hsidiv;
/* System limits based on desired VOS settings.*/
if ((ccp->pwr_cr1 & PWR_CR1_VOS_Msk) == PWR_CR1_VOS_1) {
slp = &vos_range2;
}
else if ((ccp->pwr_cr1 & PWR_CR1_VOS_Msk) == PWR_CR1_VOS_0) {
slp = &vos_range1;
}
else {
return true;
}
/* HSI16 clock.*/
if ((ccp->rcc_cr & RCC_CR_HSION) != 0U) {
hsi16clk = STM32_HSI16CLK;
}
/* HSISYS clock.*/
hsidiv = 1U << ((ccp->rcc_cr & RCC_CR_HSIDIV_Msk) >> RCC_CR_HSIDIV_Pos);
hsisysclk = hsi16clk / hsidiv;
/* HSE clock.*/
if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) {
hseclk = STM32_HSECLK;
}
/* PLL MUX clock.*/
switch (ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLSRC_Msk) {
case RCC_PLLCFGR_PLLSRC_HSI:
pllselclk = hsi16clk;
break;
case RCC_PLLCFGR_PLLSRC_HSE:
pllselclk = hseclk;
break;
default:
pllselclk = 0U;
}
/* PLL outputs.*/
if ((ccp->rcc_cr & RCC_CR_PLLON) != 0U) {
uint32_t pllmdiv, pllndiv, pllpdiv, pllqdiv, pllrdiv;
halfreq_t pllvcoclk;
/* PLL M divider.*/
pllmdiv = ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLM_Msk) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
/* PLL N divider.*/
pllndiv = (ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLN_Msk) >> RCC_PLLCFGR_PLLN_Pos;
if (pllndiv < 8) {
return true;
}
/* PLL VCO frequency.*/
pllvcoclk = (pllselclk / (halfreq_t)pllmdiv) * (halfreq_t)pllndiv;
if ((pllvcoclk < slp->pllvco_min) || (pllvcoclk > slp->pllvco_max)) {
return true;
}
/* PLL P output frequency.*/
pllpdiv = 1U + ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLP_Msk) >> RCC_PLLCFGR_PLLP_Pos);
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLPEN) != 0U) {
pllpclk = pllvcoclk / pllpdiv;
if ((pllpclk < slp->pllp_min) || (pllpclk > slp->pllp_max)) {
return true;
}
}
/* PLL Q output frequency.*/
pllqdiv = 1U + ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQ_Msk) >> RCC_PLLCFGR_PLLQ_Pos);
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLQEN) != 0U) {
pllqclk = pllvcoclk / pllqdiv;
if ((pllqclk < slp->pllq_min) || (pllqclk > slp->pllq_max)) {
return true;
}
}
/* PLL R output frequency.*/
pllrdiv = 1U + ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLR_Msk) >> RCC_PLLCFGR_PLLR_Pos);
if ((ccp->rcc_pllcfgr & RCC_PLLCFGR_PLLREN) != 0U) {
pllrclk = pllvcoclk / pllrdiv;
if ((pllrclk < slp->pllr_min) || (pllrclk > slp->pllr_max)) {
return true;
}
}
}
/* SYSCLK frequency.*/
switch (ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_HSI:
sysclk = hsisysclk;
break;
case RCC_CFGR_SW_HSE:
sysclk = hseclk;
break;
case RCC_CFGR_SW_PLL:
sysclk = pllrclk;
break;
case RCC_CFGR_SW_LSI:
sysclk = STM32_LSICLK;
break;
case RCC_CFGR_SW_LSE:
sysclk = STM32_LSECLK;
break;
default:
sysclk = 0U;
}
if (sysclk > slp->sysclk_max) {
return true;
}
/* HCLK frequency.*/
hclk = sysclk / hprediv[(ccp->rcc_cfgr & RCC_CFGR_HPRE_Msk) >> RCC_CFGR_HPRE_Pos];
/* PPRE frequency.*/
pclk = hclk / pprediv[(ccp->rcc_cfgr & RCC_CFGR_PPRE_Msk) >> RCC_CFGR_PPRE_Pos];
if ((ccp->rcc_cfgr & RCC_CFGR_PPRE_Msk) < RCC_CFGR_PPRE_DIV2) {
pclktim = pclk;
}
else {
pclktim = pclk * 2U;
}
/* MCO clock.*/
switch (ccp->rcc_cfgr & RCC_CFGR_MCOSEL_Msk) {
case STM32_MCOSEL_NOCLOCK:
mcoclk = 0U;
break;
case STM32_MCOSEL_SYSCLK:
mcoclk = sysclk;
break;
case STM32_MCOSEL_HSI16:
mcoclk = hsi16clk;
break;
case STM32_MCOSEL_HSE:
mcoclk = hseclk;
break;
case STM32_MCOSEL_PLLRCLK:
mcoclk = pllrclk;
break;
case STM32_MCOSEL_LSI:
mcoclk = STM32_LSICLK;
break;
case STM32_MCOSEL_LSE:
mcoclk = STM32_LSECLK;
break;
default:
mcoclk = 0U;
}
mcodiv = 1U << ((ccp->rcc_cfgr & RCC_CFGR_MCOPRE_Msk) >> RCC_CFGR_MCOPRE_Pos);
if (mcodiv > 16U) {
return true;
}
mcoclk /= mcodiv;
/* Flash settings.*/
flashws = ((ccp->flash_acr & FLASH_ACR_LATENCY_Msk) >> FLASH_ACR_LATENCY_Pos);
if (flashws >= STM32_WS_THRESHOLDS) {
return true;
}
if (hclk > slp->flash_thresholds[flashws]) {
return true;
}
/* Writing out results.*/
clock_points[CLK_SYSCLK] = sysclk;
clock_points[CLK_HSISYSCLK] = hsisysclk;
clock_points[CLK_PLLPCLK] = pllpclk;
clock_points[CLK_PLLQCLK] = pllqclk;
clock_points[CLK_PLLRCLK] = pllrclk;
clock_points[CLK_HCLK] = hclk;
clock_points[CLK_PCLK] = pclk;
clock_points[CLK_PCLKTIM] = pclktim;
clock_points[CLK_MCO] = mcoclk;
return false;
}
/**
* @brief Configures full clock settings.
*
* @param[in] ccp pointer to clock a @p halclkcfg_t structure
* @return The clock configuration result.
* @retval false if the clock switch succeeded
* @retval true if the clock switch failed
*
* @notapi
*/
static bool hal_lld_clock_raw_config(const halclkcfg_t *ccp) {
/* Restoring default PWR settings related clocks and sleep modes.*/
PWR->CR1 = PWR_CR1_VOS_0;
/* Waiting for all regulator status bits to be cleared, this means that
power levels are stable.*/
while ((PWR->SR2 & (PWR_SR2_VOSF | PWR_SR2_REGLPF)) != 0U) {
/* Waiting for the regulator to be ready.*/
}
/* If the clock source is not HSI then we switch to HSI and reset some
other relevant registers to their default value.*/
if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
/* Making sure HSI is activated and in use.*/
hsi16_reset();
/* Resetting flash ACR settings to the default value.*/
flash_set_acr(STM32_FLASH_ACR_RESET);
/* Resetting all other clock sources and PLLs.*/
RCC->CR = STM32_RCC_CR_RESET;
while ((RCC->CR & RCC_CR_HSERDY) != 0U) {
/* Waiting for oscillators to shut down.*/
}
}
/* HSE setup, if required, before starting the PLL.*/
if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) {
hse_enable();
}
#if STM32_RCC_HAS_HSI48
/* HSI48 setup, if required, before starting the PLL.*/
if ((ccp->rcc_cr & RCC_CR_HSI48ON) != 0U) {
hsi48_enable();
}
#endif
/* PLL setup.*/
RCC->PLLCFGR = ccp->rcc_pllcfgr;
/* PLLs enabled if specified, note, HSI16 is kept running.*/
RCC->CR = ccp->rcc_cr | RCC_CR_HSION;
/* PLL activation polling if required.*/
while (true) {
if (((ccp->rcc_cr & RCC_CR_PLLON) != 0U) && pll_not_locked()) {
continue;
}
break;
}
/* MCO and bus dividers first.*/
RCC->CFGR = (RCC->CFGR & RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & ~RCC_CFGR_SW_Msk);
/* Final flash ACR settings.*/
flash_set_acr(ccp->flash_acr);
/* Final PWR modes.*/
PWR->CR1 = ccp->pwr_cr1;
PWR->CR2 = ccp->pwr_cr2;
/* Waiting for the correct regulator state.*/
if ((ccp->pwr_cr1 & PWR_CR1_LPR) == 0U) {
/* Main mode selected.*/
while ((PWR->SR2 & PWR_SR2_REGLPF) != 0U) {
/* Waiting for the regulator to be in main mode.*/
}
}
else {
/* Low power mode selected.*/
while ((PWR->SR2 & PWR_SR2_REGLPF) == 0U) {
/* Waiting for the regulator to be in low power mode.*/
}
}
/* Switching to the final clock source.*/
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & RCC_CFGR_SW_Msk);
while ((RCC->CFGR & RCC_CFGR_SWS) != ((ccp->rcc_cfgr & RCC_CFGR_SW_Msk) << RCC_CFGR_SWS_Pos)) {
/* Waiting for clock switch.*/
}
/* If HSI16 is not in configuration then it is finally shut down.*/
if ((ccp->rcc_cr & RCC_CR_HSION) == 0U) {
hsi16_disable();
}
return false;
}
#if 0
/**
* @brief Configures clock switch-only settings.
* @note This is a fast reconfiguration, clock sources settings are not
* touched, only switches and dividers are reprogrammed.
*
* @param[in] cwp pointer to clock a @p halclkswc_t structure
* @return The clock configuration result.
* @retval false if the clock switch succeeded
* @retval true if the clock switch failed
*
* @notapi
*/
static bool hal_lld_clock_raw_switch(const halclkswc_t *cwp) {
/* PWR modes.*/
PWR->CR1 = (PWR->CR1 & ~STM32_PWR_CR1_SAFE_ONLY_MASK) |
(cwp->pwr_cr1 & STM32_PWR_CR1_SAFE_ONLY_MASK);
/* Flash ACR settings.*/
flash_set_acr(cwp->flash_acr);
/* Switching to the final clock source.*/
RCC->CFGR = cwp->rcc_cfgr;
while ((RCC->CFGR & RCC_CFGR_SWS) != ((cwp->rcc_cfgr & RCC_CFGR_SW_Msk) << RCC_CFGR_SWS_Pos)) {
/* Waiting for clock switch.*/
}
return false;
}
#endif
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
/*===========================================================================*/
/* Driver interrupt handlers. */
@ -657,7 +177,6 @@ void hal_lld_init(void) {
irqInit();
}
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/**
* @brief STM32G0xx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
@ -667,49 +186,6 @@ void hal_lld_init(void) {
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Reset of all peripherals.*/
rccResetAHB(~0);
rccResetAPBR1(~0);
rccResetAPBR2(~0);
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false);
#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, true);
#endif
/* Static PWR configurations.*/
hal_lld_set_static_pwr();
/* Backup domain made accessible.*/
PWR->CR1 |= PWR_CR1_DBP;
/* Backup domain reset.*/
bd_reset();
/* Static clocks setup.*/
lse_init();
lsi_init();
/* Static clocks setup.*/
hal_lld_set_static_clocks();
/* Selecting the default clock/power/flash configuration.*/
if (hal_lld_clock_raw_config(&hal_clkcfg_default)) {
osalSysHalt("clkswc");
}
/* Backup domain initializations.*/
bd_init();
#endif /* STM32_NO_INIT */
}
#else /* !defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Reset of all peripherals.*/
rccResetAHB(~0);
@ -727,30 +203,18 @@ void stm32_clock_init(void) {
/* Static PWR configurations.*/
hal_lld_set_static_pwr();
/* Additional PWR configurations.*/
PWR->CR2 = STM32_PWR_CR2;
/* Core voltage setup.*/
PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
; /* stable. */
/* Backup domain reset.*/
bd_reset();
/* Clocks setup.*/
lse_init();
lsi_init();
hsi16_init();
hsi48_init();
hse_init();
/* Backup domain initializations.*/
bd_init();
/* PLLs activation, if required.*/
pll_init();
/* Static clocks setup.*/
hal_lld_set_static_clocks();
@ -768,50 +232,5 @@ void stm32_clock_init(void) {
#endif /* STM32_NO_INIT */
}
#endif /* !defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/**
* @brief Switches to a different clock configuration
*
* @param[in] ccp pointer to clock a @p halclkcfg_t structure
* @return The clock switch result.
* @retval false if the clock switch succeeded
* @retval true if the clock switch failed
*
* @notapi
*/
bool hal_lld_clock_switch_mode(const halclkcfg_t *ccp) {
if (hal_lld_clock_check_tree(ccp)) {
return true;
}
if (hal_lld_clock_raw_config(ccp)) {
return true;
}
/* Updating the CMSIS variable.*/
SystemCoreClock = hal_lld_get_clock_point(CLK_HCLK);
return false;
}
/**
* @brief Returns the frequency of a clock point in Hz.
*
* @param[in] clkpt clock point to be returned
* @return The clock point frequency in Hz or zero if the
* frequency is unknown.
*
* @notapi
*/
halfreq_t hal_lld_get_clock_point(halclkpt_t clkpt) {
osalDbgAssert(clkpt < CLK_ARRAY_SIZE, "invalid clock point");
return clock_points[clkpt];
}
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
/** @} */

648
os/hal/ports/STM32/STM32C0xx/hal_lld.h
View File

@ -75,13 +75,13 @@
*/
#define CLK_SYSCLK 0U
#define CLK_HSISYSCLK 1U
#define CLK_HSIKERCLK 1U
#define CLK_HCLK 2U
#define CLK_PCLK 3U
#define CLK_PCLKTIM 4U
#define CLK_MCO1 5U
#define CLK_MCO2 6U
#define CLK_ARRAY_SIZE 7U
#define CLK_HSIKERCLK 2U
#define CLK_HCLK 3U
#define CLK_PCLK 4U
#define CLK_PCLKTIM 5U
#define CLK_MCO 6U
#define CLK_MCO2 7U
#define CLK_ARRAY_SIZE 8U
/** @} */
/**
@ -246,13 +246,6 @@
#define STM32_NO_INIT FALSE
#endif
/**
* @brief Enables the dynamic clock handling.
*/
#if !defined(STM32_CLOCK_DYNAMIC) || defined(__DOXYGEN__)
#define STM32_CLOCK_DYNAMIC FALSE
#endif
/**
* @brief PWR CR3 register initialization value.
*/
@ -481,11 +474,6 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/* Clock handling mode selection.*/
#if STM32_CLOCK_DYNAMIC == TRUE
#define HAL_LLD_USE_CLOCK_MANAGEMENT
#endif
/*
* Configuration-related checks.
*/
@ -533,11 +521,6 @@
#define STM32_ADCCLK_MAX 350000000
#define STM32_0WS_THRESHOLD 24000000
#define STM32_1WS_THRESHOLD 48000000
#define STM32_2WS_THRESHOLD 64000000
#define STM32_3WS_THRESHOLD 0
#define STM32_4WS_THRESHOLD 0
#define STM32_5WS_THRESHOLD 0
/** @} */
/* Clock handlers.*/
@ -546,69 +529,6 @@
#include "stm32_hsi48.inc"
#include "stm32_hse.inc"
/*
* HSI16 related checks.
*/
#if STM32_HSI16_ENABLED
#else /* !STM32_HSI16_ENABLED */
#if STM32_SW == STM32_SW_HSISYS
#error "HSI16 not enabled, required by STM32_SW"
#endif
#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
/* NOTE: Missing checks on the HSI16 pre-muxes, it is also required for newer
L4 devices.*/
#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
(STM32_I2S1SEL == STM32_I2S1SEL_HSI16) || \
(STM32_I2S2SEL == STM32_I2S2SEL_HSI16) || \
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI16))
#error "HSI16 not enabled, required by STM32_MCOSEL"
#endif
#if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_USART1SEL"
#endif
#if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
#error "HSI16 not enabled, required by STM32_USART2SEL"
#endif
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_LPUART1SEL"
#endif
#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV)
#error "HSI16 not enabled, required by STM32_CECSEL"
#endif
#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_I2C1SEL"
#endif
#if (STM32_I2S1SEL == STM32_I2S1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_I2S1SEL"
#endif
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_LPTIM1SEL"
#endif
#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16)
#error "HSI16 not enabled, required by STM32_LPTIM2SEL"
#endif
#if (STM32_RNGSEL == STM32_RNGSEL_HSI16)
#error "HSI16 not enabled, required by STM32_RNGSEL"
#endif
#if (STM32_ADCSEL == STM32_ADCSEL_HSI16)
#error "HSI16 not enabled, required by STM32_ADCSEL"
#endif
#endif /* !STM32_HSI16_ENABLED */
/*
* HSI48 related checks.
*/
@ -616,12 +536,28 @@
#if STM32_HSI48_ENABLED
#else /* !STM32_HSI48_ENABLED */
#if STM32_SW == STM32_SW_HSISYS
#error "HSI48 not enabled, required by STM32_SW"
#endif
#if STM32_MCOSEL == STM32_MCOSEL_HSI48
#error "HSI48 not enabled, required by STM32_MCOSEL"
#endif
#if (STM32_USBSEL == STM32_USBSEL_HSI48) && (HAL_USE_USB == TRUE)
#error "HSI48 not enabled, required by STM32_USBSEL"
#if STM32_MCO2SEL == STM32_MCO2SEL_HSI48
#error "HSI48 not enabled, required by STM32_MCO2SEL"
#endif
#if (STM32_ADCSEL == STM32_ADCSEL_HSIKER)
#error "HSI48 not enabled, required by STM32_ADCSEL"
#endif
#if (STM32_I2C1SEL == STM32_I2C1SEL_HSIKER)
#error "HSI48 not enabled, required by STM32_I2C1SEL"
#endif
#if (STM32_USART1SEL == STM32_USART1SEL_HSIKER)
#error "HSI48 not enabled, required by STM32_USART1SEL"
#endif
#endif /* !STM32_HSI48_ENABLED */
@ -637,16 +573,12 @@
#error "HSE not enabled, required by STM32_SW"
#endif
#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
#if STM32_MCOSEL == STM32_MCOSEL_HSE
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
(STM32_FDCANSEL == STM32_FDCANSEL_HSE) || \
(STM32_USBSEL == STM32_USBSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#if STM32_MCO2SEL == STM32_MCO2SEL_HSE
#error "HSE not enabled, required by STM32_MCO2SEL"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
@ -669,6 +601,10 @@
#error "LSI not enabled, required by STM32_MCOSEL"
#endif
#if STM32_MCO2SEL == STM32_MCO2SEL_LSI
#error "LSI not enabled, required by STM32_MCO2SEL"
#endif
#if STM32_LSCOSEL == STM32_LSCOSEL_LSI
#error "LSI not enabled, required by STM32_LSCOSEL"
#endif
@ -689,142 +625,101 @@
#error "LSE not enabled, required by STM32_MCOSEL"
#endif
#if STM32_MCO2SEL == STM32_MCO2SEL_LSE
#error "LSE not enabled, required by STM32_MCO2SEL"
#endif
#if STM32_LSCOSEL == STM32_LSCOSEL_LSE
#error "LSE not enabled, required by STM32_LSCOSEL"
#endif
#if (STM32_USART1SEL == STM32_USART1SEL_LSE)
#error "LSE not enabled, required by STM32_USART1SEL"
#endif
#endif /* !STM32_LSE_ENABLED */
/**
* @brief STM32_HSIDIV field.
*/
#if (STM32_HSIDIV_VALUE == 1) || defined(__DOXYGEN__)
#define STM32_HSIDIV STM32_HSIDIV_1
#define STM32_HSIDIV STM32_HSIDIV_DIV1
#elif STM32_HSIDIV_VALUE == 2
#define STM32_HSIDIV STM32_HSIDIV_2
#define STM32_HSIDIV STM32_HSIDIV_DIV2
#elif STM32_HSIDIV_VALUE == 4
#define STM32_HSIDIV STM32_HSIDIV_4
#define STM32_HSIDIV STM32_HSIDIV_DIV4
#elif STM32_HSIDIV_VALUE == 8
#define STM32_HSIDIV STM32_HSIDIV_8
#define STM32_HSIDIV STM32_HSIDIV_DIV8
#elif STM32_HSIDIV_VALUE == 16
#define STM32_HSIDIV STM32_HSIDIV_16
#define STM32_HSIDIV STM32_HSIDIV_DIV16
#elif STM32_HSIDIV_VALUE == 32
#define STM32_HSIDIV STM32_HSIDIV_32
#define STM32_HSIDIV STM32_HSIDIV_DIV32
#elif STM32_HSIDIV_VALUE == 64
#define STM32_HSIDIV STM32_HSIDIV_64
#define STM32_HSIDIV STM32_HSIDIV_DIV64
#elif STM32_HSIDIV_VALUE == 128
#define STM32_HSIDIV STM32_HSIDIV_128
#define STM32_HSIDIV STM32_HSIDIV_DIV128
#else
#error "invalid STM32_HSIDIV_VALUE value specified"
#endif
/**
* @brief PLL input clock frequency.
* @brief STM32_HSIKER field.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
#if (STM32_HSIKER_VALUE == 1) || defined(__DOXYGEN__)
#define STM32_HSIKER STM32_HSIKER_DIV1
#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
#define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
#elif STM32_HSIKER_VALUE == 2
#define STM32_HSIKER STM32_HSIKER_DIV2
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLCLKIN 0
#elif STM32_HSIKER_VALUE == 3
#define STM32_HSIKER STM32_HSIKER_DIV3
#elif STM32_HSIKER_VALUE == 4
#define STM32_HSIKER STM32_HSIKER_DIV4
#elif STM32_HSIKER_VALUE == 5
#define STM32_HSIKER STM32_HSIKER_DIV5
#elif STM32_HSIKER_VALUE == 6
#define STM32_HSIKER STM32_HSIKER_DIV6
#elif STM32_HSIKER_VALUE == 7
#define STM32_HSIKER STM32_HSIKER_DIV7
#elif STM32_HSIKER_VALUE == 8
#define STM32_HSIKER STM32_HSIKER_DIV8
#else
#error "invalid STM32_PLLSRC value specified"
#error "invalid STM32_HSIKER_VALUE value specified"
#endif
/*
* PLL enable check.
*/
#if (STM32_SW == STM32_SW_PLLRCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
(STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \
(STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \
(STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
(STM32_I2S2SEL == STM32_I2S2SEL_PLLPCLK) || \
(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
(STM32_USBSEL == STM32_USBSEL_PLLQCLK) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
*/
#define STM32_ACTIVATE_PLL TRUE
#else
#define STM32_ACTIVATE_PLL FALSE
#endif
/**
* @brief STM32_PLLREN field.
*/
#if (STM32_SW == STM32_SW_PLLRCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLREN (1 << 28)
#else
#define STM32_PLLREN (0 << 28)
#endif
/**
* @brief STM32_PLLQEN field.
*/
#if (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \
(STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \
(STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
(STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
(STM32_USBSEL == STM32_USBSEL_PLLQCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLQEN (1 << 24)
#else
#define STM32_PLLQEN (0 << 24)
#endif
/**
* @brief STM32_PLLPEN field.
*/
#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
(STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
(STM32_I2S2SEL == STM32_I2S2SEL_PLLPCLK) || \
defined(__DOXYGEN__)
#define STM32_PLLPEN (1 << 16)
#else
#define STM32_PLLPEN (0 << 16)
#endif
/* Inclusion of PLL-related checks and calculations.*/
#include <stm32_pll_v2.inc>
/**
* @brief HSISYS clock frequency.
*/
#define STM32_HSISYSCLK (STM32_HSI16CLK / STM32_HSIDIV_VALUE)
#define STM32_HSISYSCLK (STM32_HSI48CLK / STM32_HSIDIV_VALUE)
/**
* @brief HSIKER clock frequency.
*/
#define STM32_HSIKERCLK (STM32_HSI48CLK / STM32_HSIKER_VALUE)
/**
* @brief System clock source.
*/
#if STM32_NO_INIT || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_HSISYSCLK
#elif (STM32_SW == STM32_SW_HSISYS)
#if (STM32_SW == STM32_SW_HSISYS)
#define STM32_SYSCLK STM32_HSISYSCLK
#elif (STM32_SW == STM32_SW_HSE)
#define STM32_SYSCLK STM32_HSECLK
#elif (STM32_SW == STM32_SW_PLLRCLK)
#define STM32_SYSCLK STM32_PLL_R_CLKOUT
#elif (STM32_SW == STM32_SW_LSI)
#define STM32_SYSCLK STM32_LSICLK
@ -854,15 +749,12 @@
#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
#define STM32_MCODIVCLK STM32_SYSCLK
#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
#define STM32_MCODIVCLK STM32_HSI16CLK
#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
#define STM32_MCODIVCLK STM32_HSI48CLK
#elif STM32_MCOSEL == STM32_MCOSEL_HSE
#define STM32_MCODIVCLK STM32_HSECLK
#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK
#define STM32_MCODIVCLK STM32_PLL_R_CLKOUT
#elif STM32_MCOSEL == STM32_MCOSEL_LSI
#define STM32_MCODIVCLK STM32_LSICLK
@ -904,6 +796,62 @@
#error "invalid STM32_MCOPRE value specified"
#endif
/**
* @brief MCO2 divider clock frequency.
*/
#if (STM32_MCO2SEL == STM32_MCO2SEL_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_MCO2DIVCLK 0
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
#define STM32_MCO2DIVCLK STM32_SYSCLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_HSI48
#define STM32_MCO2DIVCLK STM32_HSI48CLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_HSE
#define STM32_MCO2DIVCLK STM32_HSECLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_LSI
#define STM32_MCO2DIVCLK STM32_LSICLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_LSE
#define STM32_MCO2DIVCLK STM32_LSECLK
#else
#error "invalid STM32_MCO2SEL value specified"
#endif
/**
* @brief MCO2 output pin clock frequency.
*/
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO2CLK STM32_MCO2DIVCLK
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV8
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 8)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV16
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 16)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV32
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 32)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV64
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 64)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV128
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 128)
#else
#error "invalid STM32_MCO2PRE value specified"
#endif
/**
* @brief RTC clock frequency.
*/
@ -932,8 +880,8 @@
#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
#define STM32_USART1CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
#define STM32_USART1CLK STM32_HSI16CLK
#elif STM32_USART1SEL == STM32_USART1SEL_HSIKER
#define STM32_USART1CLK hal_lld_get_clock_point(CLK_HSIKERCLK)
#elif STM32_USART1SEL == STM32_USART1SEL_LSE
#define STM32_USART1CLK STM32_LSECLK
@ -942,116 +890,6 @@
#error "invalid source selected for USART1 clock"
#endif
/**
* @brief USART2 clock frequency.
*/
#if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__)
#define STM32_USART2CLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
#define STM32_USART2CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
#define STM32_USART2CLK STM32_HSI16CLK
#elif STM32_USART2SEL == STM32_USART2SEL_LSE
#define STM32_USART2CLK STM32_LSECLK
#else
#error "invalid source selected for USART2 clock"
#endif
/**
* @brief USART3 clock frequency.
*/
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
#if (STM32_USART3SEL == STM32_USART3SEL_PCLK) || defined(__DOXYGEN__)
#define STM32_USART3CLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
#define STM32_USART3CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_USART3SEL == STM32_USART3SEL_HSI16
#define STM32_USART3CLK STM32_HSI16CLK
#elif STM32_USART3SEL == STM32_USART3SEL_LSE
#define STM32_USART3CLK STM32_LSECLK
#else
#error "invalid source selected for USART3 clock"
#endif
#else
#define STM32_USART3CLK hal_lld_get_clock_point(CLK_PCLK)
#endif
/**
* @brief UART4 frequency.
*/
#define STM32_UART4CLK hal_lld_get_clock_point(CLK_PCLK)
/**
* @brief UART5 frequency.
*/
#define STM32_UART5CLK hal_lld_get_clock_point(CLK_PCLK)
/**
* @brief UART6 frequency.
*/
#define STM32_UART6CLK hal_lld_get_clock_point(CLK_PCLK)
/**
* @brief LPUART1 clock frequency.
*/
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__)
#define STM32_LPUART1CLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
#define STM32_LPUART1CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
#define STM32_LPUART1CLK STM32_HSI16CLK
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
#define STM32_LPUART1CLK STM32_LSECLK
#else
#error "invalid source selected for LPUART1 clock"
#endif
/**
* @brief LPUART2 clock frequency.
*/
#if defined(STM32G0B1xx) || defined(STM32G0C1xx) || defined(__DOXYGEN__)
#if (STM32_LPUART2SEL == STM32_LPUART2SEL_PCLK) || defined(__DOXYGEN__)
#define STM32_LPUART2CLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_LPUART2SEL == STM32_LPUART2SEL_SYSCLK
#define STM32_LPUART2CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_LPUART2SEL == STM32_LPUART2SEL_HSI16
#define STM32_LPUART2CLK STM32_HSI16CLK
#elif STM32_LPUART2SEL == STM32_LPUART2SEL_LSE
#define STM32_LPUART2CLK STM32_LSECLK
#else
#error "invalid source selected for LPUART2 clock"
#endif
#endif
/**
* @brief CEC clock frequency.
*/
#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV) || defined(__DOXYGEN__)
#define STM32_CECCLK (STM32_HSI16CLK / 448)
#elif STM32_CECSEL == STM32_CECSEL_LSE
#define STM32_CECCLK STM32_LSECLK
#else
#error "invalid source selected for CEC clock"
#endif
/**
* @brief I2C1 clock frequency.
*/
@ -1061,8 +899,8 @@
#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
#define STM32_I2C1CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
#define STM32_I2C1CLK STM32_HSI16CLK
#elif STM32_I2C1SEL == STM32_I2C1SEL_HSIKER
#define STM32_I2C1CLK hal_lld_get_clock_point(CLK_HSIKERCLK)
#else
#error "invalid source selected for I2C1 clock"
@ -1077,8 +915,8 @@
#elif STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK
#define STM32_I2S1CLK hal_lld_get_clock_point(CLK_PLLPCLK)
#elif STM32_I2S1SEL == STM32_I2S1SEL_HSI16
#define STM32_I2S1CLK STM32_HSI16CLK
#elif STM32_I2S1SEL == STM32_I2S1SEL_HSIKER
#define STM32_I2S1CLK hal_lld_get_clock_point(CLK_HSIKERCLK)
#elif STM32_I2S1SEL == STM32_I2S1SEL_CKIN
#define STM32_I2S1CLK 0 /* Unknown, would require a board value */
@ -1087,93 +925,14 @@
#error "invalid source selected for I2S1 clock"
#endif
/**
* @brief LPTIM1 clock frequency.
*/
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__)
#define STM32_LPTIM1CLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
#define STM32_LPTIM1CLK STM32_LSICLK
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
#define STM32_LPTIM1CLK STM32_HSI16CLK
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
#define STM32_LPTIM1CLK STM32_LSECLK
#else
#error "invalid source selected for LPTIM1 clock"
#endif
/**
* @brief LPTIM2 clock frequency.
*/
#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK) || defined(__DOXYGEN__)
#define STM32_LPTIM2CLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
#define STM32_LPTIM2CLK STM32_LSICLK
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
#define STM32_LPTIM2CLK STM32_HSI16CLK
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
#define STM32_LPTIM2CLK STM32_LSECLK
#else
#error "invalid source selected for LPTIM2 clock"
#endif
/**
* @brief RNGDIV field.
*/
#if (STM32_RNGDIV_VALUE == 1) || defined(__DOXYGEN__)
#define STM32_RNGDIV (0U << 28U)
#elif STM32_RNGDIV_VALUE == 2
#define STM32_RNGDIV (1U << 28U)
#elif STM32_RNGDIV_VALUE == 4
#define STM32_RNGDIV (2U << 28U)
#elif STM32_RNGDIV_VALUE == 8
#define STM32_RNGDIV (3U << 28U)
#else
#error "invalid STM32_RNGDIV_VALUE value specified"
#endif
/**
* @brief RNG clock frequency.
*/
#if (STM32_RNGSEL == STM32_RNGSEL_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_RNGCLK 0
#elif STM32_RNGSEL == STM32_RNGSEL_HSI16
#define STM32_RNGCLK (STM32_HSI16CLK / STM32_RNGDIV_VALUE)
#elif STM32_RNGSEL == STM32_RNGSEL_SYSCLK
#define STM32_RNGCLK (hal_lld_get_clock_point(CLK_SYSCLK) / STM32_RNGDIV_VALUE)
#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
#define STM32_RNGCLK (hal_lld_get_clock_point(CLK_PLLQCLK) / STM32_RNGDIV_VALUE)
#else
#error "invalid source selected for RNG clock"
#endif
/**
* @brief ADC clock frequency.
*/
#if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__)
#define STM32_ADCCLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK
#define STM32_ADCCLK hal_lld_get_clock_point(CLK_PLLPCLK)
#elif STM32_ADCSEL == STM32_ADCSEL_HSI16
#define STM32_ADCCLK STM32_HSI16CLK
#elif STM32_ADCSEL == STM32_ADCSEL_HSIKER
#define STM32_ADCCLK hal_lld_get_clock_point(CLK_HSIKERCLK)
#else
#error "invalid source selected for ADC clock"
@ -1189,32 +948,6 @@
#define STM32_TIMPCLK (STM32_PCLK * 2)
#endif
/**
* @brief TIM1 clock frequency.
*/
#if (STM32_TIM1SEL == STM32_TIM1SEL_TIMPCLK) || defined(__DOXYGEN__)
#define STM32_TIM1CLK STM32_TIMPCLK
#elif STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK
#define STM32_TIM1CLK hal_lld_get_clock_point(CLK_PLLQCLK)
#else
#error "invalid source selected for TIM1 clock"
#endif
/**
* @brief TIM15 clock frequency.
*/
#if (STM32_TIM15SEL == STM32_TIM15SEL_TIMPCLK) || defined(__DOXYGEN__)
#define STM32_TIM15CLK STM32_TIMPCLK
#elif STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK
#define STM32_TIM15CLK hal_lld_get_clock_point(CLK_PLLQCLK)
#else
#error "invalid source selected for TIM15 clock"
#endif
/**
* @brief Clock of timers connected to APB1.
*/
@ -1225,59 +958,14 @@
*/
#define STM32_TIMCLK2 hal_lld_get_clock_point(CLK_PCLKTIM)
#if STM32_HAS_TIM1617_ERRATA
/* TIM16 and TIM17 require special handling and checks on some devices, see
the errata: "TIM16 and TIM17 are unduly clocked by SYSCLK".*/
#define STM32_TIM16CLK hal_lld_get_clock_point(CLK_SYSCLK)
#define STM32_TIM17CLK hal_lld_get_clock_point(CLK_SYSCLK)
#endif
/**
* @brief FDCAN clock point.
*/
#if (STM32_FDCANSEL == STM32_FDCANSEL_PCLK) || defined(__DOXYGEN__)
#define STM32_FDCANCLK hal_lld_get_clock_point(CLK_PCLK)
#elif STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK
#define STM32_FDCANCLK hal_lld_get_clock_point(CLK_PLLQCLK)
#elif STM32_FDCANSEL == STM32_FDCANSEL_HSE
#define STM32_FDCANCLK STM32_HSECLK
#else
#error "invalid source selected for FDCAN clock"
#endif
/**
* @brief USB clock point.
*/
#if (STM32_USBSEL == STM32_USBSEL_HSI48) || defined(__DOXYGEN__)
#define STM32_USBCLK STM32_HSI48CLK
#elif STM32_USBSEL == STM32_USBSEL_PLLQCLK
#define STM32_USBCLK hal_lld_get_clock_point(CLK_PLLQCLK)
#elif STM32_USBSEL == STM32_USBSEL_HSE
#define STM32_USBCLK STM32_HSECLK
#else
#error "invalid source selected for USB clock"
#endif
/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0
#elif STM32_HCLK <= STM32_1WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_0
#elif STM32_HCLK <= STM32_2WS_THRESHOLD
#define STM32_FLASHBITS FLASH_ACR_LATENCY_1
#else
#define STM32_FLASHBITS (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)
#define STM32_FLASHBITS FLASH_ACR_LATENCY_0
#endif
/*===========================================================================*/
@ -1289,39 +977,10 @@
*/
typedef unsigned halclkpt_t;
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/**
* @brief Type of a clock point frequency in Hz.
*/
typedef uint32_t halfreq_t;
/**
* @brief Type of a clock configuration and switch structure.
*/
typedef struct {
uint32_t pwr_cr1;
uint32_t pwr_cr2;
uint32_t rcc_cr;
uint32_t rcc_cfgr;
uint32_t rcc_pllcfgr;
uint32_t flash_acr;
} halclkcfg_t;
/**
* @brief Type of a clock switch-only structure.
*/
typedef struct {
uint32_t pwr_cr1;
uint32_t rcc_cfgr;
uint32_t flash_acr;
} halclkswc_t;
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
#if !defined(HAL_LLD_USE_CLOCK_MANAGEMENT)
/**
* @brief Returns the frequency of a clock point in Hz.
* @note Static implementation.
@ -1335,15 +994,13 @@ typedef struct {
#define hal_lld_get_clock_point(clkpt) \
((clkpt) == CLK_SYSCLK ? STM32_SYSCLK : \
(clkpt) == CLK_HSISYSCLK ? STM32_HSISYSCLK : \
(clkpt) == CLK_PLLPCLK ? STM32_PLL_P_CLKOUT : \
(clkpt) == CLK_PLLQCLK ? STM32_PLL_Q_CLKOUT : \
(clkpt) == CLK_PLLRCLK ? STM32_PLL_R_CLKOUT : \
(clkpt) == CLK_HSISYSCLK ? STM32_HSIKERCLK : \
(clkpt) == CLK_HCLK ? STM32_HCLK : \
(clkpt) == CLK_PCLK ? STM32_PCLK : \
(clkpt) == CLK_PCLKTIM ? STM32_TIMPCLK : \
(clkpt) == CLK_MCO ? STM32_MCOCLK : \
(clkpt) == CLK_MCO2 ? STM32_MCO2CLK : \
0U)
#endif /* !defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
/*===========================================================================*/
/* External declarations. */
@ -1358,20 +1015,11 @@ typedef struct {
#include "stm32_rcc.h"
#include "stm32_tim.h"
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) && !defined(__DOXYGEN__)
extern const halclkcfg_t hal_clkcfg_reset;
extern const halclkcfg_t hal_clkcfg_default;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void stm32_clock_init(void);
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
bool hal_lld_clock_switch_mode(const halclkcfg_t *ccp);
halfreq_t hal_lld_get_clock_point(halclkpt_t clkpt);
#endif /* defined(HAL_LLD_USE_CLOCK_MANAGEMENT) */
#ifdef __cplusplus
}
#endif

4
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -36,9 +36,7 @@
/**
* @brief Flash ACR reset value.
*/
#define STM32_FLASH_ACR_RESET (FLASH_ACR_DBG_SWEN | \
FLASH_ACR_ICEN | \
FLASH_ACR_LATENCY_0WS)
#define STM32_FLASH_ACR_RESET 0x00040600U
/**
* @brief RCC CR reset value.

20
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -1067,6 +1067,7 @@
#if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_I2C1SEL"
#endif
#if (STM32_I2S1SEL == STM32_I2S1SEL_HSI16)
#error "HSI16 not enabled, required by STM32_I2S1SEL"
#endif
@ -1121,17 +1122,23 @@
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
(STM32_FDCANSEL == STM32_FDCANSEL_HSE) || \
(STM32_USBSEL == STM32_USBSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
#if STM32_FDCANSEL == STM32_FDCANSEL_HSE
#error "HSE not enabled, required by STM32_FDCANSEL"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#error "HSE not enabled, required by STM32_RTCSEL"
#endif
#if STM32_USBSEL == STM32_USBSEL_HSE
#error "HSE not enabled, required by STM32_USBSEL"
#endif
#endif /* !STM32_HSE_ENABLED */
/*
@ -1172,6 +1179,10 @@
#error "LSE not enabled, required by STM32_LSCOSEL"
#endif
#if (STM32_USART1SEL == STM32_USART1SEL_LSE)
#error "LSE not enabled, required by STM32_USART1SEL"
#endif
#endif /* !STM32_LSE_ENABLED */
/**
@ -1292,10 +1303,7 @@
/**
* @brief System clock source.
*/
#if STM32_NO_INIT || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_HSISYSCLK
#elif (STM32_SW == STM32_SW_HSISYS)
#if (STM32_SW == STM32_SW_HSISYS)
#define STM32_SYSCLK STM32_HSISYSCLK
#elif (STM32_SW == STM32_SW_HSE)

201
tools/ftl/processors/conf/mcuconf_stm32c0x1xx/mcuconf.h.ftl Normal file
View File

@ -0,0 +1,201 @@
[#ftl]
[#--
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--]
[@pp.dropOutputFile /]
[#import "/@lib/libutils.ftl" as utils /]
[#import "/@lib/liblicense.ftl" as license /]
[@pp.changeOutputFile name="mcuconf.h" /]
/*
[@license.EmitLicenseAsText /]
*/
/*
* STM32C0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
#define STM32C0xx_MCUCONF
#define STM32C011_MCUCONF
#define STM32C031_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWUL)"}
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
#define STM32_PWR_PUCRA ${doc.STM32_PWR_PUCRA!"(0U)"}
#define STM32_PWR_PDCRA ${doc.STM32_PWR_PDCRA!"(0U)"}
#define STM32_PWR_PUCRB ${doc.STM32_PWR_PUCRB!"(0U)"}
#define STM32_PWR_PDCRB ${doc.STM32_PWR_PDCRB!"(0U)"}
#define STM32_PWR_PUCRC ${doc.STM32_PWR_PUCRC!"(0U)"}
#define STM32_PWR_PDCRC ${doc.STM32_PWR_PDCRC!"(0U)"}
#define STM32_PWR_PUCRD ${doc.STM32_PWR_PUCRD!"(0U)"}
#define STM32_PWR_PDCRD ${doc.STM32_PWR_PDCRD!"(0U)"}
#define STM32_PWR_PUCRF ${doc.STM32_PWR_PUCRF!"(0U)"}
#define STM32_PWR_PDCRF ${doc.STM32_PWR_PDCRF!"(0U)"}
#define STM32_HSIDIV_VALUE ${doc.STM32_HSIDIV_VALUE!"4"}
#define STM32_HSIKER_VALUE ${doc.STM32_HSIDIV_VALUE!"3"}
#define STM32_HSI48_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
#define STM32_SW ${doc.STM32_SW!"STM32_SW_HSI48"}
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
#define STM32_PPRE ${doc.STM32_PPRE!"STM32_PPRE_DIV1"}
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
#define STM32_MCO2SEL ${doc.STM32_MCOSEL!"STM32_MCO2SEL_NOCLOCK"}
#define STM32_MCO2PRE ${doc.STM32_MCOPRE!"STM32_MCO2PRE_DIV1"}
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
/*
* Peripherals clocks and sources.
*/
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_PCLK"}
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK"}
#define STM32_I2S1SEL ${doc.STM32_I2S1SEL!"STM32_I2S1SEL_SYSCLK"}
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_ADCSEL_HSIKER"}
/*
* Shared IRQ settings.
*/
#define STM32_IRQ_EXTI0_1_PRIORITY ${doc.STM32_IRQ_EXTI0_1_PRIORITY!"3"}
#define STM32_IRQ_EXTI2_3_PRIORITY ${doc.STM32_IRQ_EXTI2_3_PRIORITY!"3"}
#define STM32_IRQ_EXTI4_15_PRIORITY ${doc.STM32_IRQ_EXTI4_15_PRIORITY!"3"}
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"2"}
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"2"}
#define STM32_IRQ_TIM1_UP_PRIORITY ${doc.STM32_IRQ_TIM1_UP_PRIORITY!"1"}
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"1"}
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"1"}
#define STM32_IRQ_TIM14_PRIORITY ${doc.STM32_IRQ_TIM14_PRIORITY!"1"}
#define STM32_IRQ_TIM16_PRIORITY ${doc.STM32_IRQ_TIM16_PRIORITY!"1"}
#define STM32_IRQ_TIM17_PRIORITY ${doc.STM32_IRQ_TIM17_PRIORITY!"1"}
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
#define STM32_ADC_ADC1_CFGR2 ${doc.STM32_ADC_ADC1_CFGR2!"ADC_CFGR2_CKMODE_ADCCLK"}
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"2"}
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"2"}
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"3"}
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"}
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
/*
* RTC driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 ${doc.STM32_SIO_USE_USART1!"FALSE"}
#define STM32_SIO_USE_USART2 ${doc.STM32_SIO_USE_USART2!"FALSE"}
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"2"}
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"2"}
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"17"}
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
#endif /* MCUCONF_H */

29
tools/updater/update_mcuconf_stm32c0x1xx.sh Normal file
View File

@ -0,0 +1,29 @@
#!/bin/bash
if [ $# -eq 2 ]
then
if [ $1 = "rootpath" ]
then
find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32c0x1xx.sh "{}" \;
else
echo "Usage: update_mcuconf_stm32c0x1xx.sh [rootpath <root path>]"
fi
elif [ $# -eq 1 ]
then
declare conffile=$(<$1)
if egrep -q "STM32C011_MCUCONF" <<< "$conffile" || egrep -q "STM32C031_MCUCONF" <<< "$conffile"
then
echo Processing: $1
egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt
if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32c0x1xx
then
echo
echo "aborted"
exit 1
fi
cp ./mcuconf.h $1
rm ./mcuconf.h ./values.txt
fi
else
echo "Usage: update_mcuconf_stm32c0x1xx.sh [rootpath <root path>]"
echo " update_mcuconf_stm32c0x1xx.sh <configuration file>]"
fi